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"Vladislav Muravin" <muravinv@advantech.ca> wrote in message news:h5pHe.780$z91.148816@news20.bellglobal.com... > > I have a V2 3000 device, and I am using BUFGMUX, the one located at P7 > location (for this synthesis, I do not lock them). This BUFGMUX guy > multiplexes between one external and one internal clock. I output all 4 > signals of BUFGMUX on the test pins and I see that when S is '1', the > output is not equal to I1 input !!! > I verify at least by FPGA Editor that the connections of BUFGMUX are ok. > > So, I am going for another board with another FPGA and I will also check > that the pins are not shorted, but any other suggestions from everybody > are always welcome. > Here's a suggestion, in the V2 datasheet it says that "As long as the presently selected clock is High, any level change of S has no effect .". Is that your problem? Cheers, Syms.Article: 87826
"Monica" <monica_dsz@yahoo.com> schrieb im Newsbeitrag news:1122972550.821754.20550@f14g2000cwb.googlegroups.com... > Hi all, > > I am Monica from Germany,I am new to FPGA programming.I have very > little experience with Altera cyclone FPGA development and Quartus > software.I dont have any experience with Xilinx tools.Now our company > want to try Xilinx because xilinx offers J.83 Annex A/C Modulator QAM > IP core. > > We have received a AVNET Xilinx Spartan3 board with xc3s1500 FPGA.Our > company wants me to test the board with a sample program.But I am > having hard time to test the board.The examples(Hello World!) are for > EDK software.But we dont have EDK software.We just want to download a > sample project and see "Hello World!" on screen. > > So I tried to use impact software which came with free ISE webpack and > tried to download "download.bit",it says that "download.msk" doesnt > exist. > > then I tried to download "system.bit" it says that "programmed > sucessfully" but I dont observe any "hello world" on console. > > Am I missing something?Is this approach not correct?Do we really need > EDK software? > > Please help me regarding this problem.If I have to read any > documentation please provide pointers. > > Thanks in advance. > Monica DSouza, > Germany > hi Monica system.bit is only FPGA part of the design and does not contain the app software in it, so there would be no 'hello' try the download.bit and uncheck 'verify' then it will program ok if you want to use Xilinx Microblaze then yes you need EDK license what is $495 USD AnttiArticle: 87827
Hi Antti, It looks like Steven Knapp have been very busy lately! Luiz CarlosArticle: 87828
Try to find out if the different FPGA manufacturers offer embedded hardware blocks which will make your life easier when trying to implement DDR/DDR2. Of course there are also IP cores provided by the manufacturers. Contact some FAEs. If you want to implement DDR on your own "from scratch" it will be a hard job in my opinion. Rgds Andr=E9Article: 87829
Hi, is there any place where I can download the mentioned sources to compile the modules for my Debian SID? On the Xilinx Website you can only find the link ftp://ftp.xilinx.com/pub/utilities/fpga/linuxdrivers.tar.gz but Kernel 2.6 is not supported and I can't compile it. I found the following link when googling http://www.jungo.com/download/WD621LN.tgz But I'm not sure if it is save to use. Any Ideas or suggestions how I can get them work? Thanks AmirArticle: 87830
Why do you have to convert the design at all ? Would it not be worthwhile to learn VHDL or Verilog ? Of course NOW it would be the easiest step to convert your proven schematic design. But in the long run it might be better to be able to change the VHDL / Verilog description. How do you simulate your designs? Rgds Andr=E9Article: 87831
Morpheus, First, if you work in avionics industry, then probably FAEs & sales reps will jump onto you as you ask them this question, because avionics can afford anything... Second, if you want to convert schematic to HDL and certification of the design is critical, find a good FPGA design engineer to do the job at high-level code, because instead of generating this high-level code and synthesizing it (which is what you will probably do) you can synthesize the schematic directly. It's just weird to me to certify the code generated by tool, because usually it is better to design high-level code than to generate it, as well it is easier to blame somebody than some tools, which, just as the Matrix, may be not perfect :):):). (No hard feelings, Morph. could not resist :) ) Vladislav "morpheus" <saurster@gmail.com> wrote in message news:1122950126.543093.39170@f14g2000cwb.googlegroups.com... > Does anyone know of a tool that actually converts a schematic entry > design to Verilog/VHDL. I know tools like Quartus can do it but the > conversion is at the device level(correct me if I'm wrong). I need > conversion to maybe behavioural level(I know I might be dreaming). > I work in the avionics industry and certification of the design is > critical. > Any clues will be appreciated > cheers y'all > MORPHEUS >Article: 87832
Brad, As far as I recall, the speed grade affects only timing analysis (xilinx people would correct me if i am wrong). Downloading a bit file which was synthesized with a different speed grade only is ok. But if the device is different in size, then you have to resynthesize it, in which case a suitable script would do the job. Vladislav "Brad Smallridge" <bradsmallridge@dslextreme.com> wrote in message news:11et3q5p4gbnn22@corp.supernews.com... >I have a board with three Spartan3s on it. > Right now, under sources in project, I have > the project name, then xc3s400-4pq208, > and under that > top1-behavioral(top1.vhd), > top2-behavioral(top2.vhd), > top3-behavioral(top3.vhd) > > and stuf under those like the top1.ucf, etc. > > So what happens if one of the Xilinx parts > gets upgraded or downgrade in speed or > size? Can I assign the xc3s400 spec to > each top level design? > > Brad > > >Article: 87833
Brad, There are two types of reset. One, hardware reset, is typically sourced by an external pin. Two, software reset, is typically sourced by a bit written by CPU & any other host controller. It all depends on what you are up to. Sometimes, you might want to reset parts of the design upon some synchronization reached or something like this. Vladislav "Brad Smallridge" <bradsmallridge@dslextreme.com> wrote in message news:11estoihe350a2f@corp.supernews.com... > Up to now, I have been doing much of my work with ModelSim and > a BMP file reader and writer. Most of my VHDL designs have clk > and reset. I know where to attach the clk but what do I use for > reset. An external pin? The Done pin? Or a DCM lock signal? > > Brad Smallridge > b r a d @ a i v i s i o n . c o m > >Article: 87834
Pavel, I can see at least one fundamental problem, which is registered output. No need for references. Simply keep in mind that usually, bidirectional bus with tri-state is implemented without FFs, because when you sample 1'bz, the result is always 'X', BY LAW. Try the following : // sample dout assign dout = en ? dout1 : 1'bz; assign din = dout; Hope this helps. Vladislav "Telenochek" <interpasha@hotmail.com> wrote in message news:1122919805.341703.215660@g14g2000cwa.googlegroups.com... > Hello everyone! > I am having a problem in ModelSim XE 5.8c with a very simple > bidirectional bus. > ModelSim outputs a bunch of XXXX's where its supposed to output data. > I am using test bench waveforms with Xilinx ISE 6.303i. > > Basically there are only 3 signals: the bidir. bus, wr_enable and clk. > The idea behind this simple code is: > if WR_EN is HIGH -> store bus data into a flip-flop on next clock edge. > > else WR_EN is LOW -> output a constant value on the bus (in practice, I > want to output something more useful, of course.) > > Unfortunately, ModelSim outputs X's (don't cares) for every bit where > the data in flip-flop conflicts with the constant. > Let's say that 11110000 was stored in the flip-flop when WR_EN was > high. > And suppose that the constant to put on the bus is 00110000, when WR_EN > goes low. > When WR_EN actually does go low, ModelSim will output XX110000 instead > of 00110000. > > I think the problem might be with the way I designed the bus with VHDL. > But I can't figure out where the problem is, and the code is VERY > simple. > Any help on this and maybe references to reading materials on > bidirectional/tristate bus implementation in VHDL would be highly > appreciated! > Thanks, > Pavel > > Here is the code: > ------------------------------ > library IEEE; > use IEEE.STD_LOGIC_1164.ALL; > ------------------------------ > ENTITY bidir_bus IS > PORT( > bidir : INOUT STD_LOGIC_VECTOR (7 DOWNTO 0); > WR_en, clk : IN STD_LOGIC); > END bidir_bus; > ------------------------------ > ARCHITECTURE Behavioral OF bidir_bus IS > SIGNAL a : STD_LOGIC_VECTOR (7 DOWNTO 0); -- DFF that stores > -- value from input. > BEGIN > PROCESS (WR_en, clk) > BEGIN > IF( WR_en = '1') THEN > bidir <= "ZZZZZZZZ"; > IF(clk'EVENT and clk='1') THEN > a <= bidir; > END IF; > ELSE > bidir <= "11110000"; -- simply output a constant on the bus > -- of course, in practice I would like to > -- output something else. > END IF; > END PROCESS; > END Behavioral; > ------------------------------ >Article: 87835
Amir Tabatabaei wrote: > Hi, > > is there any place where I can download the mentioned sources to > compile the modules for my Debian SID? > > On the Xilinx Website you can only find the link > > ftp://ftp.xilinx.com/pub/utilities/fpga/linuxdrivers.tar.gz > > but Kernel 2.6 is not supported and I can't compile it. I found the > following link when googling > > http://www.jungo.com/download/WD621LN.tgz > > But I'm not sure if it is save to use. > > Any Ideas or suggestions how I can get them work? > > Thanks > Amir You found the right stuff on jungo.com. Just compile the redist part and you'll be fine. -- BrianArticle: 87836
Thanks Antti, It works. We dont need EDK for this project because we are not using any processor but we need ISE full software.So we have ordered ISE software instead of EDK. Thanks for the help. MonicaArticle: 87837
<oen_no_spam@yahoo.com.br> schrieb im Newsbeitrag news:1122984488.187170.289000@g47g2000cwa.googlegroups.com... > Hi Antti, > > It looks like Steven Knapp have been very busy lately! > > Luiz Carlos > you mean so busy that not updating the availability info? my bet so far was S3E general availabiliy : september 2005 or later. it looks like my guess may have been more correct than the promises made by Xilinx employees. hm... Antti PS I have some background info about some S3E silicon been shipped to some small companies. but that doesnt mean that threre is general availability as was indicated by Xilinx for mid July 2005.Article: 87838
No, Symon. I am afraid not, my problem is a real problem. It's something very simple and fundamental. I am switching between the two clocks when I loop one data path to another. But thanks, appreciate it. Can you think of anything else? Vladislav. "Symon" <symon_brewer@hotmail.com> wrote in message news:42ef578f$0$18641$14726298@news.sunsite.dk... > "Vladislav Muravin" <muravinv@advantech.ca> wrote in message > news:h5pHe.780$z91.148816@news20.bellglobal.com... >> >> I have a V2 3000 device, and I am using BUFGMUX, the one located at P7 >> location (for this synthesis, I do not lock them). This BUFGMUX guy >> multiplexes between one external and one internal clock. I output all 4 >> signals of BUFGMUX on the test pins and I see that when S is '1', the >> output is not equal to I1 input !!! >> I verify at least by FPGA Editor that the connections of BUFGMUX are ok. >> >> So, I am going for another board with another FPGA and I will also check >> that the pins are not shorted, but any other suggestions from everybody >> are always welcome. >> > Here's a suggestion, in the V2 datasheet it says that "As long as the > presently selected clock is High, any level change of S has no effect .". > Is that your problem? > Cheers, Syms. >Article: 87839
Latest version supports up to XC3S1500. XC3S400 has been support since 6.1-6.3 time. -- John Adair Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 Development Board. http://www.enterpoint.co.uk "Chris Carlen" <crcarleRemoveThis@BOGUSsandia.gov> wrote in message news:dclt200130k@news3.newsguy.com... > Hi: > > I am reading the FAQ on Spartan3 here: > > http://www.xilinx.com/products/spartan3/faq105_s3.pdf > > which says only XC3S50 is supported by WebPack 5.2i. I realize this is an > old version (though the one I am still using since I had trouble with > 6.1i). Now we are at 7.1i, which indicates support for Spartan3 of course > here: > > http://www.xilinx.com/ise/logic_design_prod/webpack.htm > > but doesn't indicate the details about whether it supports larger Spartan3 > devices or not. > > Specifically, I am considering XC3S400. > > Does WebPack 7.1i support that or do I need to start spending $$$ ? > > > Thanks for input. > > > Good day! > > > -- > _______________________________________________________________________ > Christopher R. Carlen > Principal Laser/Optical Technologist > Sandia National Laboratories CA USA > crcarleRemoveThis@BOGUSsandia.gov > NOTE, delete texts: "RemoveThis" and "BOGUS" from email address to reply.Article: 87840
Dear I need some comments on managing the 'global reset' in ISE6.3(XST) from experienced one. I am post-placement-and-routing simulating in Modelsim. This module has input reset port. During synthesis/mapping, there is no warning/error. During the simulation, followings are observed, which are maybe or maybe not be problematic. - In behavioral simulation, it works, even though no value is assigned to reset signal in test vector. - After placement-and-routing simulation, it works, only when we put reset signal is '0' in test vector. I am wondering if this is problematic.Article: 87841
Hi all, I am using j83a/c modulator IP core of Xilinx in ISE.I have synthesised and implemented the design.I did not any errors.But when I tried to create a symbol for toplevel entity,I got some errors saying that "c_mux_bus_v7_0 does not exist in library xilinxcorelib". Can anybody help me how to get these libraries? I wonder how the design was implemented without any errors if some libraries are really missing. Please guide me if there is some documentation or reference design to use j83a/c modulator IP core. Thanks in advance. Monica Started process "Create Schematic Symbol". Compiling vhdl file "F:/Projects/IPCore/ipCore/j83ac_netlist_v1_0/j83ac_netlist_v1_0/Spar tan3/fourch/syn/../syn/j83ac_rrc_comp.vhd" in Library work. Package <j83ac_rrc_comp> compiled. Compiling vhdl file "F:/Projects/IPCore/ipCore/j83ac_netlist_v1_0/j83ac_netlist_v1_0/Spar tan3/fourch/syn/conv_pkg.vhd" in Library work. Package <conv_pkg> compiled. Package body <conv_pkg> compiled. Package <clock_pkg> compiled. Compiling vhdl file --snip-- ERROR:HDLParsers:3281 - "F:/Projects/IPCore/ipCore/j83ac_netlist_v1_0/j83ac_netlist_v1_0/S partan3/fourch/syn/j83ac_4ch_dut_files.vhd" Line 2322. behavioral is not an architecture body for c_mux_bus_v7_0 in library XilinxCoreLib. WARNING:HDLParsers:3024 - Can not read library unit c_mux_bus_v7_0. It has been stored before the predefined library unit standard of library std. Clean your dump directory and recompile your design again. WARNING:HDLParsers:3024 - Can not read library unit prims_constants_v7_0. It has been stored before the predefined library unit standard of library std. Clean your dump directory and recompile your design again. ERROR:HDLParsers:3016 - "F:/Projects/IPCore/ipCore/j83ac_netlist_v1_0/j83ac_netlist_v1_0/S partan3/fourch/syn/j83ac_4ch_dut_files.vhd" Library unit prims_constants_v7_0 required for unit c_mux_bus_v7_0 does not exist in library xilinxcorelib. ERROR:HDLParsers:3281 - "F:/Projects/IPCore/ipCore/j83ac_netlist_v1_0/j83ac_netlist_v1_0/S partan3/fourch/syn/j83ac_4ch_dut_files.vhd" Line 2372. behavioral is not an architecture body for c_mux_bus_v7_0 in library XilinxCoreLib. --snip-- Entity <j83ac_4ch_dut> compiled. Entity <j83ac_4ch_dut> (Architecture <structural>) compiled. vhdtdtfi:Declaration (Module top_j83ac) not found. tdtfi(vhdl) completed with errors. ERROR: vhdtdtfi failedArticle: 87842
Thanks Brian, but make make install [...] mkdir -p /lib/modules/2.6.12/kernel/drivers/misc cp LINUX.2.6.12/windrvr6.ko /lib/modules/2.6.12/kernel/drivers/misc ./wdreg windrvr6 FATAL: Error inserting windrvr6 (/lib/modules/2.6.12/kernel/drivers/misc/windrvr6.ko): Invalid module formatmake: *** [install] Error 1 The module can't be inserted! :-( Any Ideas? On Tue, 02 Aug 2005 15:47:37 +0200, Brian Dam Pedersen wrote: > You found the right stuff on jungo.com. Just compile the redist part and > you'll be fine. > > -- BrianArticle: 87843
I inherited some code for the Actel fpga. The author said he downloaded the demo toolset (early version) from Actel and then reset his PC clock until he was able to finish. My understanding is that the toolchain has changed substantially since he wrote the code. I need two things: 1 - to be able to read the code/project and determine what it does 2 - to be able to revise/maintain the code. I would like recommendations as to what toolchain to port this code to. Money is an issue - ROI is quite low. -- --------------------------------------------------------------------- DataGet & PocketLog www.dataget.com Data Collectors www.baxcode.com --------------------------------------------------------------------Article: 87844
Vladislav, what you just wrote is correct. Speed grade does not affect bitstream, only performance. That is true for all Xilinx parts. Peter AlfkArticle: 87845
Amir Tabatabaei wrote: > Thanks Brian, but > > make > make install > > [...] > mkdir -p /lib/modules/2.6.12/kernel/drivers/misc > cp LINUX.2.6.12/windrvr6.ko /lib/modules/2.6.12/kernel/drivers/misc > ./wdreg windrvr6 > FATAL: Error inserting windrvr6 > (/lib/modules/2.6.12/kernel/drivers/misc/windrvr6.ko): Invalid module > formatmake: *** [install] Error 1 > > The module can't be inserted! :-( > Any Ideas? > > > On Tue, 02 Aug 2005 15:47:37 +0200, Brian Dam Pedersen wrote: > > >>You found the right stuff on jungo.com. Just compile the redist part and >>you'll be fine. >> >>-- Brian > > Hm. Normally this would indicate that the kernel version that the module is compiled for is not the one that is actually running. I tried this with success on a SUSE 9.1 (patched 2.6.9 kernel). I can't tell if something has happened in 2.6.12 to make it incompatible with the jumbo stuff. -- BrianArticle: 87846
While I'm waiting for EDK to be delivered I thought I'd play around with a hardware-only design. I made a trivial LED flasher, and went to download it through Parallel Cable IV / JTAG. I'm using ISE 6.3. When I use impact 6.3.03i to load the LX25 bit file (I'm bypassing the other three devices) I get: WARNING:iMPACT:1049 - Startup Clock has been changed to 'JtagClk' in the bitstream stored in memory, but the original bitstream file remains unchanged. If I ignore this and program anyway, I get six errors on verify. Multiple write/verify cycles always give six errors. The design seems to work though. What am I doing wrong? The V4 is ES if that's significant. Thanks PeteArticle: 87847
nahum_barnea@yahoo.com wrote on 02/08/05 10:50: > Hi. > > I would need to begin a new fpga design intefacing with external SODIMM > at a rate of 400 Mbit/sec/pin. > > I have 2 alternatives DDR-SODIMM and DDR2-SODIMM. > >>From fpga interface prespective, which of them is advantagious ? Depends on what FPGA you want to use... If it's a Xilinx Virtex2Pro or Virtex-4, then you can use free, ready-to-use IP-cores from Xilinx for both DDR and DDR2, no need to design the controller yourself. And, trust me, you don't really want to design a DDR memory controller yourself if it isn't absolutely neccessary. Designs like that are usually a PITA with all the phase-shifting and data valid windows and crap like that... I have never worked with Altera parts, but as far as I know they too have free memory controllers you can use with their newer parts. So, I suppose, from the FPGA standpoint it really doesn't matter if you use DDR or DDR2. You could argue that DDR2 is newer and therefore will be around longer, so it will be easier to get DDR2-SODIMMs in the long run. And you could argue that DDR2 offers higher possible performance... so if you find out later that 400Mbit/sec isn't enough, you can run it at 533 or even 600 (with a really fast FPGA), whereas with DDR that's about as high as you can go, AFAIR. cu, SeanArticle: 87848
I'm sorry if this is a trivial question, but I haven't found anything on this topic in the Xilinx site: is it possible to implement a programmable frequency synthesizer with Spartan3 DCMs? With "programmable" I mean programmable at runtime (just like you can do with a programmable PLL synthesizer), not just at design time. Thank you! -- asdArticle: 87849
Yes, it can be done, but it's far more flexible to use Direct Digital Synthesis to generate arbitrary frequencies over a very wide range. Here is the description of a Frequency Synthesizer that we recently built 250 copies of. Very popular in our lab and with FAEs. We are looking at the next generation going to a few GHz using MGT outputs. Fun project... Xilinx Programmable Clock Source, Product Description Outputs: 2 SMA connectors: LVDS, 440 mV diff., +1.20 V common mode, 1 Hz to 640 MHz 1 SMA connector: LVCMOS33 single-ended, limited to < 80 MHz Performance: Frequency range: 1 Hz to 640 MHz, 1 Hz resolution over full range Frequency indication: 9-digit LCD display Frequency accuracy and stability: < 2ppm Cycle-to-cycle jitter: <100 ps peak-to-peak Frequency adjustment: Rotary knob with two operating modes: Either adjust frequency value or adjust decimal position. Change mode by pressing knob inward. Number of frequencies that can be stored on EEPROM and recalled: 1000 Power input: 5-V, + center-conductor, max 2 W, Dimensions: 125mm x 55mm x 25 mm, = 5" x 2.25" x 1" P.A. 2-22-05
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