Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarAprMayJunJulAugSepOctNovDec2017
2018JanFebMarAprMayJunJulAugSepOctNovDec2018
2019JanFebMarAprMayJunJulAugSepOctNovDec2019
2020JanFebMarAprMay2020

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search

Messages from 91700

Article: 91700
Subject: Re: open-sourced FPGA (vhdl, verilog, C variants) design libraries, working toward a GNU (for hardware) paradigm
From: air_bits@yahoo.com
Date: 10 Nov 2005 18:49:35 -0800
Links: << >>  << T >>  << A >>
Actually you are quite wrong on this point. Programmers write tight
and efficient code for embedded micro applications all the time.

Exactly the same processes come into play as we mentor programmers
on projects that use an FPGA as the compute engine.

Good tools, reasonable training/mentoring, and design standards avoid
gross mistakes when they matters.

When they don't, who cares?


Article: 91701
Subject: Re: open-sourced FPGA (vhdl, verilog, C variants) design libraries, working toward a GNU (for hardware) paradigm
From: air_bits@yahoo.com
Date: 10 Nov 2005 18:55:43 -0800
Links: << >>  << T >>  << A >>
So what's the point other than a gross management failure to properly
train and mentor the responsible engineers .... maybe so they can
beat their chests?

I've seen similar failures with EE's that thought they could write
programs
just because they learned to code C, or Fortran, or Basic, and then
fell
flat on their faces trying to implement trivial algorithms that any
third year
Computer Science student would do in their sleep.

I've seen similar failures with both EE's and CSc students fresh out of
school
lock up when faced with their first real development job simply because
the
lacked the confidence and experience (and mentoring management) to
learn
their first job.

So, what's your point really? .... that FPGA's are only for REAL
EXPERIENCED
EE's?

sorry ...


Article: 91702
Subject: SDRAM controller.
From: bohr_singh@hotmail.com
Date: 10 Nov 2005 18:56:10 -0800
Links: << >>  << T >>  << A >>
Hi Guys,

I am writing a SDRAM controller (for the first time), its a Micron
MT48LC16M16 sdram. I am having a little trouble coding it, i've written
some code for it but i am not sure if i am going along the right path
or not ? Does neone has a little tutorial on how to code a sdram
controller or perhaps a sdram controller that they wrote (doesnt matter
for which SDRAM), nething that i could use as a reference to learn
more. Ne help would be appreciated !! Thanks.


Article: 91703
Subject: Re: open-sourced FPGA (vhdl, verilog, C variants) design libraries, working toward a GNU (for hardware) paradigm
From: Eric Smith <eric@brouhaha.com>
Date: 10 Nov 2005 18:57:22 -0800
Links: << >>  << T >>  << A >>
I wrote:
> For example, typical C code for a discrete cosine transform can be found
> here:
> 
> 	http://www.bath.ac.uk/elec-eng/pages/sipg/resource/c/fastdct.c
> 
> But I suspect that code will synthesize to something at least an
> order of magnitude larger and an order of magnitude slower than a
> typical HDL implementation.

To be fair, I wasn't trying to compare floating point C code to integer-only
HDL code.  So I would make the same claim for a typical C DCT implementation
that does NOT use floating point:

	http://www.brouhaha.com/~eric/software/jpeg-6b/jfdctint.c

Article: 91704
Subject: Re: open-sourced FPGA (vhdl, verilog, C variants) design libraries, working toward a GNU (for hardware) paradigm
From: Eric Smith <eric@brouhaha.com>
Date: 10 Nov 2005 18:59:16 -0800
Links: << >>  << T >>  << A >>
air_bits@yahoo.com writes:
> Actually you are quite wrong on this point. Programmers write tight
> and efficient code for embedded micro applications all the time.

Certainly.  That's what I do for a living.  But the tight and efficient
code I write for execution on a microcontroller is not likely to
synthesize to an efficient FPGA implementation, because that wasn't
what I was targetting.  When I design hardware, I use very different
optimization criteria.

Article: 91705
Subject: Re: open-sourced FPGA (vhdl, verilog, C variants) design libraries,
From: Jim Granville <no.spam@designtools.co.nz>
Date: Fri, 11 Nov 2005 16:09:08 +1300
Links: << >>  << T >>  << A >>
air_bits@yahoo.com wrote:

> There is a small setup overhead for the main, but for example
> this certainly does NOT synthesize "to a large collection of
> gates and flip-flps" as you so errantly assert cluelessly:
> 
> main()
> {
> 
> int a:1,b:1,c:1,d:1;
> #pragma inputport (a);
> #pragma inputport (b);
> #pragma inputport (c);
> #pragma inputport (d);
> 
> int sum_of_products:1;
> #pragma outputport (sum_of_products);
> 
>    while(1) {
>         sum_of_products = (a&b) | (c&d);
>    }
> }
<snip XNF>

  That's a good example; can you add to this, code for a HC161/HC163, 
which is a 4 bit binary UP counter, with Sync preload, and  Async/Sync 
reset ?

  Are there other output choices, besides XNF ?

  How do you verify operation ?

-jg



Article: 91706
Subject: Re: open-sourced FPGA (vhdl, verilog, C variants) design libraries, working toward a GNU (for hardware) paradigm
From: air_bits@yahoo.com
Date: 10 Nov 2005 19:12:12 -0800
Links: << >>  << T >>  << A >>
Eric Smith writes:
>How would you write it if you did NOT want a flip-flop, but only
>a combinatorial output?

Depends on the tool.  TMCC/FpgaC registers the state of every
variable by default, and it takes a minor edit of the output netlist
to remove the register. Or since it's open source, add a pragma
option for output port to skip the register and customize the compiler
for the project if there we more than a few that a script would
easily fix.


Article: 91707
Subject: Re: open-sourced FPGA (vhdl, verilog, C variants) design libraries, working toward a GNU (for hardware) paradigm
From: air_bits@yahoo.com
Date: 10 Nov 2005 19:42:09 -0800
Links: << >>  << T >>  << A >>
Jim Granville writes:
> That's a good example; can you add to this, code for a HC161/HC163,
> which is a 4 bit binary UP counter, with Sync preload, and  Async/Sync
> reset ?

With the existing TMCC/FpgaC compilers, probably not. But I'm sure this
particular example was ment to force that answer. Certainly hand
editing
the VHDL or xnf output is pretty easy to effect that.

Can I modify TMCC/FpgaC to produce that from a specific form, as you
would write for Verilog, sure, and it's probably not that hard.
Optimization
like those are not native to Verilog, or VHDL either, but are custom
hacks
that occur as the products mature for a specific target architecture.

>Are there other output choices, besides XNF ?

Dave sent me an interesting hack that outputs as a VHDL netlist.
    -target vhd          generate VHDL format
    -target stratix_vqm  generate Altera Stratix VQM format
    -target xnf-gates    generate XNF AND/OR/INV format
    -target xnf-roms     generate XNF ROM format
    -target xnf-eqns     generate XNF EQN format (default)
    -target flex8000     generate XNF AND/OR/INV format for Altera FLEX
8K

it's not particularly readable, but useful to inputing into other
tool chains. See below.

I just grabbed a copy of xnf2edf.exe from my older ISE release, and
have a perl script to edit the output so I can target current Virtex,
Virtex-II
and Virtex-Pro parts. You probably noticed that the part specified was
the
XCV2000E's on my DINI DN2000K boards.

>How do you verify operation ?

For this compiler, which is very simple, with some regression tests on
the limited set of building blocks, and then generally trust the tools.

As with any design, you build into the process real on hardware testing
at a functional level as well.

Since I'm mostly interested in reconfigurable computing in my use of
FpgaC,
I write, debug and test on a traditional processor ... and move
pretested
code to the FPGA.

For some past projects with TMCC I used several hardware test benches,
which include two HP15600's with 1G DSO's and a couple hundred channels
of 16555D's, plus some older HP1650/3's.

I've also rigged a VGA monitor and done typical software based printf
outputs
to the VGA monitor and single stepping on software break points at a
level
pretty close to the triggers in the HP's just by building in the
debugging hardware
as I needed it.

In a few cases I've done mixed tool designs with schematics and Verilog
along
with FpgaC blocks.

I've played a little with Celoxica Handel-C as well, they have a
different
strategy for building control state machines, but it works, and pretty
well.

Other than the usefulness of being C, it's just another tool for
getting projects
done.

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity example is port(
        CLK : in std_logic;
        RESET : in std_logic;
        a : in std_logic;
        b : in std_logic;
        c : in std_logic;
        d : in std_logic;
        sum_of_products : out std_logic
);
end;

architecture arch_example of example is

        signal T0_1_0Running : std_logic;
        signal T0_1_0Zero : std_logic;
        signal T0_2_L10_curstate : std_logic;
        signal T0_4_a : std_logic;
        signal T0_4_b : std_logic;
        signal T0_4_c : std_logic;
        signal T0_4_d : std_logic;
        signal T0_10_sum_of_products : std_logic;
        signal T0_14L31_T0_10_sum_of_products : std_logic;
        signal FFin_T0_1_0Running : std_logic;
        signal FFin_T0_1_0Zero : std_logic;
        signal FFin_T0_10_sum_of_products : std_logic;


begin

        T0_4_a <= a;
        T0_4_b <= b;
        T0_4_c <= c;
        T0_4_d <= d;
        sum_of_products <= T0_10_sum_of_products;

        FFin_T0_1_0Running <= not T0_1_0Zero;
        FFin_T0_1_0Zero <= T0_1_0Zero;
        T0_2_L10_curstate <= not T0_1_0Running;
        FFin_T0_10_sum_of_products <= T0_14L31_T0_10_sum_of_products;
        T0_14L31_T0_10_sum_of_products <= (T0_4_d and T0_4_c) or
(T0_4_b and T0_4_a);


process(RESET, CLK) begin


        if (RESET = '1') then

                T0_1_0Running <= '0';
                T0_1_0Zero <= '0';
                T0_10_sum_of_products <= '0';

        elsif (CLK'event and CLK = '1') then

                T0_1_0Running <= FFin_T0_1_0Running;
                T0_1_0Zero <= FFin_T0_1_0Zero;
                if (T0_2_L10_curstate = '1') then
                        T0_10_sum_of_products <=
FFin_T0_10_sum_of_products;
                end if;
        end if;

end process;

end arch_example;


Article: 91708
Subject: Re: open-sourced FPGA (vhdl, verilog, C variants) design libraries,
From: Ray Andraka <ray@andraka.com>
Date: Thu, 10 Nov 2005 22:44:58 -0500
Links: << >>  << T >>  << A >>

For what it is worth, I've seen some pretty dismal FPGA designs come out 
of people who are supposedly digital designers too.  It generally does 
take someone seasoned to turn out an FPGA design that uses the resources 
somewhat efficiently, that is going to be reliable, and that isn't going 
to spend a large part of the time to market in some lab chasing down 
countless naive design errors.

-- 
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com  
http://www.andraka.com  

 "They that give up essential liberty to obtain a little 
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 91709
Subject: Re: open-sourced FPGA (vhdl, verilog, C variants) design libraries, working toward a GNU (for hardware) paradigm
From: Eric Smith <eric@brouhaha.com>
Date: 10 Nov 2005 19:45:28 -0800
Links: << >>  << T >>  << A >>
air_bits@yahoo.com writes:
> Depends on the tool.  TMCC/FpgaC registers the state of every
> variable by default, and it takes a minor edit of the output netlist
> to remove the register. Or since it's open source, add a pragma
> option for output port to skip the register and customize the compiler
> for the project if there we more than a few that a script would
> easily fix.

How many real-world designs have NO combinatorial outputs?

How does TMCC/FpgaC know *which* clock to use to register a given
variable?

Article: 91710
Subject: Re: SDRAM controller.
From: "mughat" <mughat@gmail.com>
Date: Fri, 11 Nov 2005 05:01:37 +0100
Links: << >>  << T >>  << A >>
You can take a look at this one in opencores.org -->
http://www.opencores.org/projects.cgi/web/ddr_sdr/overview

<bohr_singh@hotmail.com> wrote in message 
news:1131677770.461805.276770@g49g2000cwa.googlegroups.com...
> Hi Guys,
>
> I am writing a SDRAM controller (for the first time), its a Micron
> MT48LC16M16 sdram. I am having a little trouble coding it, i've written
> some code for it but i am not sure if i am going along the right path
> or not ? Does neone has a little tutorial on how to code a sdram
> controller or perhaps a sdram controller that they wrote (doesnt matter
> for which SDRAM), nething that i could use as a reference to learn
> more. Ne help would be appreciated !! Thanks.
> 



Article: 91711
Subject: Re: open-sourced FPGA (vhdl, verilog, C variants) design libraries, working toward a GNU (for hardware) paradigm
From: air_bits@yahoo.com
Date: 10 Nov 2005 20:04:04 -0800
Links: << >>  << T >>  << A >>
Eric Smith writes:
> How many real-world designs have NO combinatorial outputs?

In reconfigurable computing, using FPGA's as a processor? ALL
The reason is pretty simple, every variable is assumed to be some form
of persistant memory in the C programming model. So, suprise, every
statement which effects a variable assignment is assumed registered.
After all, we are emulating CPU's and memory in reconfigurable
computing.

> How does TMCC/FpgaC know *which* clock to use to register a given
> variable?

Each program file in the TMCC/FpgaC model is assumed to use the same
clock for a particular thread of execution.

You can bind different clocks to different files/threads.

To communicate between them requires building global variables
which are written by one thread, and read by another. In the software
world, these are mailboxes for communications. For more complex
and higher bandwidth projects I have in the past built FIFO's in other
tools, and included them in the FpgaC design at place and route.


Article: 91712
Subject: Re: open-sourced FPGA (vhdl, verilog, C variants) design libraries, working toward a GNU (for hardware) paradigm
From: air_bits@yahoo.com
Date: 10 Nov 2005 20:13:24 -0800
Links: << >>  << T >>  << A >>
Eric Smith writes:
>How many real-world designs have NO combinatorial outputs?

How many PIC's and other microprocessors have combinatorial outputs?
Maybe None?
So why would using an FPGA to replace a CPU/memory be expected to be
any different?


Article: 91713
Subject: Re: SDRAM controller.
From: Ray Andraka <ray@andraka.com>
Date: Thu, 10 Nov 2005 23:15:56 -0500
Links: << >>  << T >>  << A >>
bohr_singh@hotmail.com wrote:

>Hi Guys,
>
>I am writing a SDRAM controller (for the first time), its a Micron
>MT48LC16M16 sdram. I am having a little trouble coding it, i've written
>some code for it but i am not sure if i am going along the right path
>or not ? Does neone has a little tutorial on how to code a sdram
>controller or perhaps a sdram controller that they wrote (doesnt matter
>for which SDRAM), nething that i could use as a reference to learn
>more. Ne help would be appreciated !! Thanks.
>
>  
>
HOw about Xilinx's SDRAM controller.  I'm pretty sure the source is on 
their website along with the app-note.

-- 
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com  
http://www.andraka.com  

 "They that give up essential liberty to obtain a little 
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 91714
Subject: Re: Anybody understand this ISE 7.1 error, and what to do about it???
From: Ken McElvain <ken@synplicity.com>
Date: Thu, 10 Nov 2005 21:00:01 -0800
Links: << >>  << T >>  << A >>
This isn't true in Synplify.   We can infer resetable
static and dynamic read address SRLs and map them into
the the primitive SRL16s in a way that we preserve the
reset behavior.

- Ken McElvain
Synplicity, Inc.

Simon Peacock wrote:

> its important to note that IF you ever user a reset on a shift register, the
> a SRL16 CAN'T be inferred as it doesn't have a reset!
> 
> "Ray Andraka" <ray@andraka.com> wrote in message
> news:P7Jbf.2$Mi5.0@dukeread07...
> 
>>Antti Lukats wrote:
>>
>>
>>>AGREE 100%
>>>
>>>SRL16 is way useful but I do not see it nearly possible that they will be
>>>used the best
>>>way with regular synthesis. so the customer should be at least aware of
> 
> what
> 
>>>is needed
>>>to get the SRL16 being used (automatically) or then use them directly.
>>>
>>>Antti
>>>
>>>
>>>
>>
>>Current synthesis pretty much only instantiates the SRL16 as a fixed
>>length shift register, and then only if the designer didn't put resets
>>on the registers.  There is supposedly a magic incantation in Synplicity
>>that will infer a dynamic shift, but for th elife of me I have not been
>>able to get it to infer that consistently, and the words to the
>>incantation seem to change with each revision of the software.  I find
>>it to require less effort just to instantiate the SRL16, especially if
>>you are actually using the dynamic capability.  Also, a common mistake
>>with inferred fixed length shift registers is the synthesis often does
>>not infer a flip-flop at the SRL16 outputs, which kills clock
>>performance.  Synplify will put a flip-flop at the output of a delay,
>>but if you have a register deeper than 17 clocks, it strings together
>>SLR16's with no flip-flops between, which again kills the performance.
>>(This may have been fixed in later versions, I haven't checked).
>>
>>-- 
>>--Ray Andraka, P.E.
>>President, the Andraka Consulting Group, Inc.
>>401/884-7930     Fax 401/884-7950
>>email ray@andraka.com
>>http://www.andraka.com
>>
>> "They that give up essential liberty to obtain a little
>>  temporary safety deserve neither liberty nor safety."
>>                                          -Benjamin Franklin, 1759
>>
>>
> 
> 
> 


Article: 91715
Subject: Re: open-sourced FPGA (vhdl, verilog, C variants) design libraries,
From: Jim Granville <no.spam@designtools.co.nz>
Date: Fri, 11 Nov 2005 18:15:55 +1300
Links: << >>  << T >>  << A >>
air_bits@yahoo.com wrote:
<snip>
>>Are there other output choices, besides XNF ?
> 
> 
> Dave sent me an interesting hack that outputs as a VHDL netlist.
>     -target vhd          generate VHDL format
>     -target stratix_vqm  generate Altera Stratix VQM format
>     -target xnf-gates    generate XNF AND/OR/INV format
>     -target xnf-roms     generate XNF ROM format
>     -target xnf-eqns     generate XNF EQN format (default)
>     -target flex8000     generate XNF AND/OR/INV format for Altera FLEX
> 8K
> 
> it's not particularly readable, but useful to inputing into other
> tool chains. See below.

  I think Xilinx now do the same, for their Abel flow - they output
a 'not that readable, [but better than binary :)] VHDL' - the
advantage being the simulation tools for VHDL then are available for
ABEL.
  From those I now using this flow, Xilinx went backwards a little, then
forwards, ( as one does..) and it now works very well.

-jg



Article: 91716
Subject: Re: open-sourced FPGA (vhdl, verilog, C variants) design libraries,
From: Jim Granville <no.spam@designtools.co.nz>
Date: Fri, 11 Nov 2005 18:21:57 +1300
Links: << >>  << T >>  << A >>
air_bits@yahoo.com wrote:

> Jim Granville writes:
> 
>>That's a good example; can you add to this, code for a HC161/HC163,
>>which is a 4 bit binary UP counter, with Sync preload, and  Async/Sync
>>reset ?
> 
> 
> With the existing TMCC/FpgaC compilers, probably not. But I'm sure this
> particular example was ment to force that answer. 

  It would requires more of the designer, but what about a pragma like 
the ASM one, in many C's ? - it would accept VHDL (or verilog), and
pass on to the downstream tools.
  The advantage is it would understand the variable names, and scopes, of
the other source ( much like in line asm does now ? ).
  If a LOT of HDL code was needed, then separate code modules would be 
better.

-jg




Article: 91717
Subject: Re: Installing FPGA Advantage on Linux machine
From: "fad" <fahad.arif@gmail.com>
Date: 10 Nov 2005 21:51:31 -0800
Links: << >>  << T >>  << A >>
Thank you Hans, Mike for these helping suggestions. I have already got
FPGA ADv installed on WIndows machine but want to move Linux. I am a
bit apprehensive because this move is gonna cost me alot of time unto
things get smooth.
I have Msim SE in my bundle. And have nodelock license (put in server),
to which rest of systems on network pick the license. We have 5
licenses.
Still looking for suggestions,
Regards,


Article: 91718
Subject: Re: In Xilinx, how do I delay a signal by a fraction of a clock cycle?
From: backhus <nix@nirgends.xyz>
Date: Fri, 11 Nov 2005 08:26:36 +0100
Links: << >>  << T >>  << A >>
Symon schrieb:
> "backhoes" <nix@nirgends.xyz> wrote in message 
> news:dkur6u$jgj$1@hermes1.rz.hs-bremen.de...
> 
>>Hi Frank,
>>I would recommend you to use or generate somehow a higher Clock frequency. 
>>50MHz would be just fine. Unfortunately you may be unable to generate this 
>>Clock from your 12.5 MHz with the builtin DLLs/DCMs for these require some 
>>minimum frequency (see the datasheets for details).
>>
> 
> Eilert,
> You can use the DCMs with clock inputs down to 1MHz as long as you use 
> "frequency synthesis" mode, i.e. use the CLKFX output(s). The output clock 
> must be greater than 24 MHz. I'm using the "datasheets for details"! ;-)
> Cheers then, Syms. 
> 
> 

Hi Symon,
Thank you for clarifying this on DCMs. I knew there was some limit, but 
hadn't had the time to look it up.
But for DLLs a Minimim Input Frequency of 25 MHz is required (VirtexE 
Datasheet, Module 3 P.22), which may bother Frank with his 12.5 MHz 
Clock. Unfortunately he didn't mention his target device family.

Best regards
    Eilert

Article: 91719
Subject: Re: Anybody understand this ISE 7.1 error, and what to do about it???
From: "Simon Peacock" <simon$actrix.co.nz>
Date: Fri, 11 Nov 2005 21:50:39 +1300
Links: << >>  << T >>  << A >>
I would like to know how.. .. maybe you should check what's generated and
the read xapp465
SRL16's have no reset capability.  You can however put another ff on the
output and reset that instead... but that can't reset the shift register.
The only way to do that is to hold the input low (or high) and let it run
for 16 clocks.

taken from the xapp
When a shift register is described in generic HDL code, synthesis tools
infer the use of the SRL16 component. Since the SRL16 does not have either
synchronous or asynchronous set or reset inputs, and does not have access to
all bits at the same time, using such capabilities precludes the use of the
SRL16, and the function is implemented in flip-flops. The cascadable shift
register (SRLC16) may be inferred if the shift register is larger than 16
bits or if only the Q15 is used.

In fact, adding a reset is one way to force a synthesis tool to use
flip-flops instead of the SRL16 when flip-flops are preferred for
performance or other reasons. If a reset is not needed, simply connect a
dummy signal and use an appropriate KEEP attribute to prevent the synthesis
tool from optimizing it out of the design.

Although the SRL16 shift register does not have a parallel load capability,
an equivalent function can be implemented simply by anticipating the load
requirement and shifting in the proper data. This requires predictable
timing for the load command.

since you are inferring hardware that isn't present, it would be rather cool
to be able to get it to work as a reset... probably patentable too

Simon





"Ken McElvain" <ken@synplicity.com> wrote in message
news:qzVcf.48310$Tf5.3952@newsread1.mlpsca01.us.to.verio.net...
> This isn't true in Synplify.   We can infer resetable
> static and dynamic read address SRLs and map them into
> the the primitive SRL16s in a way that we preserve the
> reset behavior.
>
> - Ken McElvain
> Synplicity, Inc.
>
> Simon Peacock wrote:
>
> > its important to note that IF you ever user a reset on a shift register,
the
> > a SRL16 CAN'T be inferred as it doesn't have a reset!
> >
> > "Ray Andraka" <ray@andraka.com> wrote in message
> > news:P7Jbf.2$Mi5.0@dukeread07...
> >
> >>Antti Lukats wrote:
> >>
> >>
> >>>AGREE 100%
> >>>
> >>>SRL16 is way useful but I do not see it nearly possible that they will
be
> >>>used the best
> >>>way with regular synthesis. so the customer should be at least aware of
> >
> > what
> >
> >>>is needed
> >>>to get the SRL16 being used (automatically) or then use them directly.
> >>>
> >>>Antti
> >>>
> >>>
> >>>
> >>
> >>Current synthesis pretty much only instantiates the SRL16 as a fixed
> >>length shift register, and then only if the designer didn't put resets
> >>on the registers.  There is supposedly a magic incantation in Synplicity
> >>that will infer a dynamic shift, but for th elife of me I have not been
> >>able to get it to infer that consistently, and the words to the
> >>incantation seem to change with each revision of the software.  I find
> >>it to require less effort just to instantiate the SRL16, especially if
> >>you are actually using the dynamic capability.  Also, a common mistake
> >>with inferred fixed length shift registers is the synthesis often does
> >>not infer a flip-flop at the SRL16 outputs, which kills clock
> >>performance.  Synplify will put a flip-flop at the output of a delay,
> >>but if you have a register deeper than 17 clocks, it strings together
> >>SLR16's with no flip-flops between, which again kills the performance.
> >>(This may have been fixed in later versions, I haven't checked).
> >>
> >>-- 
> >>--Ray Andraka, P.E.
> >>President, the Andraka Consulting Group, Inc.
> >>401/884-7930     Fax 401/884-7950
> >>email ray@andraka.com
> >>http://www.andraka.com
> >>
> >> "They that give up essential liberty to obtain a little
> >>  temporary safety deserve neither liberty nor safety."
> >>                                          -Benjamin Franklin, 1759
> >>
> >>
> >
> >
> >
>



Article: 91720
Subject: Clock signal for an external peripheral
From: "Marco" <marcotoschi@nospam.it>
Date: Fri, 11 Nov 2005 09:53:20 +0100
Links: << >>  << T >>  << A >>
Hallo,
which is the best way to create a clock signal into a Spartan-3 for an 
external peripheral?

I have thought to use a dcm and connect clkfx_out to 1 of the 8 GCLK pin.

Any suggestion?

Many Thanks
Marco 



Article: 91721
Subject: Re: Clock signal for an external peripheral
From: "Simon Peacock" <simon$actrix.co.nz>
Date: Fri, 11 Nov 2005 22:06:21 +1300
Links: << >>  << T >>  << A >>
It doesn't really matter how you create it.. as long as its in the right
phase for what you need to do... just try to avoid outputting the output of
a GBUF.
I think the best output is a divide of one of the system (internal)clocks.

Simon


"Marco" <marcotoschi@nospam.it> wrote in message
news:dl1m60$7ed$1@nnrp.ngi.it...
> Hallo,
> which is the best way to create a clock signal into a Spartan-3 for an
> external peripheral?
>
> I have thought to use a dcm and connect clkfx_out to 1 of the 8 GCLK pin.
>
> Any suggestion?
>
> Many Thanks
> Marco
>
>



Article: 91722
Subject: fastest possible USB
From: "colin" <colin_toogood@yahoo.com>
Date: 11 Nov 2005 01:07:38 -0800
Links: << >>  << T >>  << A >>
Hi

Does anyone have some advice for the fastest say to get many MBytes of
data from a Spartan3 fifo to the hard disk of a PC via usb. I assume
that it is a combination of the best USB interface next to the FPGA and
perhaps a USB chipset in the PC that can do some very clever DMA.
I don't want to mess with custom RAID stuff I just want to dump it to a
standard hard disk & controller.

Any pointers appreciated.

Colin


Article: 91723
Subject: Re: fastest possible USB
From: Uwe Bonnes <bon@hertz.ikp.physik.tu-darmstadt.de>
Date: Fri, 11 Nov 2005 09:26:06 +0000 (UTC)
Links: << >>  << T >>  << A >>
colin <colin_toogood@yahoo.com> wrote:
> Hi

> Does anyone have some advice for the fastest say to get many MBytes of
> data from a Spartan3 fifo to the hard disk of a PC via usb. I assume
> that it is a combination of the best USB interface next to the FPGA and
> perhaps a USB chipset in the PC that can do some very clever DMA.
> I don't want to mess with custom RAID stuff I just want to dump it to a
> standard hard disk & controller.

Look at the Cypress cy7c68013a

-- 
Uwe Bonnes                bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

Article: 91724
Subject: Re: Clock signal for an external peripheral
From: "Marco" <marcotoschi@nospam.it>
Date: Fri, 11 Nov 2005 10:38:01 +0100
Links: << >>  << T >>  << A >>

"Simon Peacock" <simon$actrix.co.nz> wrote in message 
news:43745f0f@news2.actrix.gen.nz...
> It doesn't really matter how you create it.. as long as its in the right
> phase for what you need to do... just try to avoid outputting the output 
> of
> a GBUF.
> I think the best output is a divide of one of the system (internal)clocks.
>
> Simon
>
>

Sorry Simon, but I don't have understood.

Could you explain please?

Thanks
Marco 





Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarAprMayJunJulAugSepOctNovDec2017
2018JanFebMarAprMayJunJulAugSepOctNovDec2018
2019JanFebMarAprMayJunJulAugSepOctNovDec2019
2020JanFebMarAprMay2020

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search