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Peter Alfke wrote: > > Didi wrote: > > > Does anyone know anything about the Z80'000 that I've got a prelim > > > datasheet/usermanual for? It seemed like a chip ahead of its time... Actually, I wrote that... :) --Toby.Article: 94301
ftp://ftp.altera.com/outgoing/release/ Here is the one where you can find the software. GuidoArticle: 94302
Thanks for the advice, however there is still have one issue. After the internal signal is added to the waveform and the simulation is restarted (by reissuing the .do command) the simulation restarts, but the newly add signal is removed from the waveform. What am I missing? -Brendan "Brian Drummond" <brian_drummond@btconnect.com> wrote in message news:8cfvr1tslmm23tqn196n631hvfoi96r3d5@4ax.com... > On Fri, 6 Jan 2006 16:37:52 -0800, "Brendan Illingworth" > <billingworth@electrascan.com> wrote: > > >Hi All, > > > >I am using Xilinx ISE 7.1 and ModelSim XE III 6.0 to analze flip-flop and > >routing behavior in a Virtex II part. Ports that are declared in my VHDL > >entity declaration are simulated and shown in the wave window in ModelSim. > >My question is this; how does one specify in Xilinx ISE additional signals > >(that are not routed to IOB's) to be simulated in ModelSim? Using the "add > >probe" feature seems to route the signals to IOB pads and then simulates the > >result of that, I need to see the signal inside a slice (or at least right > >before or after the slice). > > In Modelsim, once the design has been loaded, using the GUI interface, > you can open windows displaying the design structure (as a directory > type tree), and the named signals. Navigate to the design sub-unit you > need to monitor; its signals are listed in the "signals" window. Select > those you need, right click, and "add selected signals to Wave window". > > Now simulate and they will be displayed. > > If you missed some, add them, restart, and simulate again. > > You can also do the same via TCL script of course; the GUI approach > simply generates the relevant script commands. Or you can save the Wave > window format as a ".do" script to recreate this test later. > > Caveat: above refers to ModelSim SE; I believe it's true of XE but I'm > not 100% certain) > > - BrianArticle: 94303
"Gilles GEORGES" <georges@irisa.fr> schrieb im Newsbeitrag news:dpu2ud$had$1@amma.irisa.fr... > Antti Lukats wrote: >> "Antti Lukats" <antti@openchip.org> schrieb im Newsbeitrag >> news:dptig7$jk$01$1@news.t-online.com... >> >>>"Gilles GEORGES" <georges@irisa.fr> schrieb im Newsbeitrag >>>news:dpteh3$9hk$1@amma.irisa.fr... >>> >>>>Dear, >>>> >>>>I received last week a Xilinx USB Platform Cable. >>>>Using ISE 7.1.04i and EDK 7.1.2 under Fedora core 2 with kernel >>>>2.6.6-1.435.2.3smp, the precompiled driver is not suitable. >> >> [snip] >> >>>>Firmware version = 1018. >>>>CPLD file version = 0006h. >>>>CPLD version = 1648h. >>> >>>that is weird on WinXP the file version and CPLD version are the same as >>>displayed >> >> sorry I meant displayed should be >> >> CPLD file version = 0006h. >> CPLD version = 0006h. >> >> antti >> >> >> > Dear Antti, > > I just tried the cable with same board on a Win XP computer and it works. > I previously downgrade to cpld firmware V4 (taken in a ISE 6.3 linux > install) => not working under linux but working under windows. Then i > upgrade to version 6 and still working under windows. > > Going back to my Linux workstation nothing works. > > There is a strange thing with Impact, the "CPLD version" differs with the > "CPLD file version" while the two match on Windows. > > Connecting to cable (Usb Port - USB22). > Checking cable driver. > File version of /local/xilinx/bin/lin/xusbdfwu.hex = 1018(dec), 03FA. > File version of /etc/hotplug/usb/xusbdfwu.fw/xusbdfwu.hex = 1018(dec), > 03FA. > Max current requested during enumeration is 150 mA. > Cable Type = 3, Revision = 0. > Setting cable speed to 6 MHz. > Cable connection established. > Firmware version = 1018. > CPLD file version = 0006h. > CPLD version = 0021h. > > Any idea. > > Gilles tell Xilinx to hire professianals to write and test their software seriously Linux support just is behind, so all Linux users just have to accept WAY more problems as WinXP users. also different departments of Xilinx have their own JTAG drivers and low level access API so when one departments gets something working then others do not, then comes new Cable or firmware/PLD update and the game begins all over, something will brake each time either impact or XMD server or Chipscope will fail not really fun AnttiArticle: 94304
rickman wrote: > I am looking at using a CRC to provide single bit error correction and > multiple bit error detection. I have worked with CRCs before and know > how to implement them. But I am lacking some of the theoretical > background on how to choose the polynomial. My data packets are a > total of 191 bits with a 31 bit header containing the CRC and 160 data > bits. The header will have its own error correction. I am trying to > determine an optimal CRC polynomial for the whole packet. Currently > there is space in the header for a CRC-8. I may be able to find a few > spare bits to make the CRC 10 or 12 bits if I have to. > > Any pointers to show me how to evaluate a polynomial? Or any shortcuts > that can be recommended? I guess this has been done before. Thanks for all the replys. I am aware of the various tradeoffs and I don't require help with the code for a CRC. I was trying to pick a polynomial that would be useful for a data packet of this size. There was one resource mentioned in the thread. I'll see if I can find it.Article: 94305
I once read about a (successful) lawsuit against a flying club. The issue was a liability waiver that used the phrase "bodily injury". Well, the poor guy was killed and his heirs argued in court that death was different from "bodily injury", and they won! In my mind death is just extreme bodily injury, but not, in this case, to the jury. TomArticle: 94306
On 9 Jan 2006 09:51:32 -0800, soar2morrow@yahoo.com wrote: >I once read about a (successful) lawsuit against a flying club. The >issue was a liability waiver that used the phrase "bodily injury". >Well, the poor guy was killed and his heirs argued in court that death >was different from "bodily injury", and they won! In my mind death is >just extreme bodily injury, but not, in this case, to the jury. > >Tom I am with the jury on this one. You can argue that anything from scrapes to loss of both legs to full paralysis from the neck down are instances of "bodily injury" but in my opinion there is a difference of quality between "DEAD" and any of those things which are again, in my opinion, differences of degree.Article: 94307
Doh.. I missed on the parity bits. You need to flip INITP00 lines so that MSB (init3F(35 downto 32) appears first.. same for the other INITP0x's. Too fast copy and paste.. :pArticle: 94308
What you're trying to do is an expression with operators (&) that requires execution. This cannot be aliased. An alias must be of all, or a contiguous part, of an existing object, with no execution required. You could alias to a slice of an array, but not to a concatenation of bits in an array. Otherwise, what Mike said. AndyArticle: 94309
Brendan Illingworth wrote:
> Thanks for the advice, however there is still have one issue. After the
> internal signal is added to the waveform and the simulation is restarted (by
> reissuing the .do command) the simulation restarts, but the newly add signal
> is removed from the waveform. What am I missing?
A cut and past of the ADD WAVE command
from the modelsim command line to
the .do file.
-- Mike Treseler
Article: 94310Jude, ES marking implies that the: -test program is not final (parts are almost ready for production release) or -the verification and characterization is not complete (early silicon, not all errata are known, or there is still work to do to characterize the parts) or -the part is from a lot that has not finished process qualification (also early silicon, but all process qual tests may still be incomplete) Once we have the final test program coverage we require, and the verification and characterization os signed off, and the process qualification is complete, then we stop marking parts as "ES." Stepping relates to the features. Stepping 1 may have more features than stepping 0 (and may also have fewer errata, or no errata at all). The stepping program makes it such that a newer stepping is backward (bitstream) compatible with an older stepping (the old bitstream provides the same performance). To gain the new features, a new bitstream may be required. AustinArticle: 94311
Ray Andraka wrote:
> Do the on-line updates repair/replace all of the windows files?
No, just some.
> I keep the system updated with the windoze updates, and none of the updates
> have fixed it.
OK that's not it.
> I've been reluctant to do the windows repair from the CD
> because my experience in the past with NT meant doing that and then
> going back and redoing all the updates, service packs etc, plus the
> occasional reinstall of applications. I suppose doing the repair from
> the CD is the next step, I'm jsut dreading it because it probably also
> means a day lost getting things back to where they are now.
A day if you're lucky.
Sometimes it's more efficient to
go to Fry's and pick up another
box preloaded with the latest XP.
> My main machine is an Athon 64x2 hypersonic cyclone ocx.
Is the the XP 64 bit version much of an advantage
for your applications?
> Moving to this
> I more or less abandoned the two machine set up I had previously,
> although I still have the second machine here untouched but not powered
> up unless I need it. The previous set-up was a dual P3-800 for the
> docuementation, design entry, sim, internet access etc and a dual
> K7-1800 for par and synthesis. My hearing was getting affected by the
> vacuum cleaner like sound emanating from those two machines, and the
> excess heat in the room was rather impressive.
I hear you on the noise.
I am now using a dell optiplex gx520.
It has a fan, but that is inaudible from 2 feet away.
> Part of the reason I
> retired the dual P3-800 was to get back onto a single machine to reduce
> the noise and heat load, as well as to avoid the network bottleneck
> between machines.
Hmm. It seems that a 100M ethernet network
ought to keep up a hard drive. What caused
the bottleneck?
> Simulation as well as the synth and par do run
> noticibly faster on the cyclone, provided I can open everything I need
> opened. It is also quite a bit cooler, and with the liquid cooling is
> virtually silent compared with the vacuum cleaner.
A single application machine is my goal as well.
Right now, I have one machine running
emacs, modelsim, quartus and open office on Suse Linux
and a separate windows machine for Leo
and Fluke Networks winXP applications.
The key for me is to use an external file
server for 100% of all data files, and to
keep nothing but OS and applications
on my local machine.
Good luck.
-- Mike Treseler
Article: 94312On 9 Jan 2006 10:55:15 -0800, "Andy" <jonesandy@comcast.net> wrote: >What you're trying to do is an expression with operators (&) that >requires execution. I realise that & is probably not the right operator.. >This cannot be aliased. An alias must be of all, >or a contiguous part, of an existing object, with no execution >required. All I want do do is alias a group of bits that are not consecutive in the original signal, so I can assign values to them as a group in a fashion that is logical for my application, instead of assinging to each bit seperately. If I can make an alias of bits 3,2 and 1 of a vector signal, why can't I do the same thing with bits, say, 8, 4 and 2 instead? All I want to do is the same thing where the bits are not consecutive - There is no execution required. Seems a bizarre limitation if this is not possible but then again the more I use VHDL the more I'm surprised at how primitive and unfriendly it is in some respects...!Article: 94313
You're welcome. When I read that your outputs were inverted I knew what the problem was immediately. I lost about a week's work on this one last year and really tore into the Xilinx FAEs about not posting the patch directly on the download page. It is precisely this sort of attitude by Xilinx that has me using Altera for all new designs (start the Xilinx vs. Altera debate!). Marc cdsmith69@gmail.com wrote: > I tried to post this several times yesterday through google > groups and it never showed up, so I got a real newsreader > installed now. If it shows up multiple times it's google's > fault. :-) > > In article <1136560656.002159.239020 > @g49g2000cwa.googlegroups.com>, news.guardiani@gmail.com says... > > >The solution is simple, but far from obvious. You need to > >download and apply the patch for ISE 7.1 or install the > >latest service pack (4). There is a bug that inverts all of > >the outputs of CPLDs (with no service pack and also > >maybe SP1). > > Bingo. That fixed everything. After downloading the 7.1.04 > update, which was something like 325 megabytes, nearly as big as > the full download, everything is working fine. My counter > counts right, the outputs aren't inverted, and I can even > directly assign pins to a value and have it work. > > >Xilinx has refused to post this information to their download > >page. I even talked to a factory FAE and he could not get > >them to post it. The only way you can find out about it is to > >search their site for key words that match the article. > > I spent a long time a couple nights ago searching their whole > knowledge base section and reading everything I could find on > the 9500 family CPLDs and never found this information. I only > found it after I went to the download page for the service pack, > and found the link that said something like "read this before > installing" and somewhere in there was a list of what the update > fixed, and in there was a short sentence or two saying that it > fixed an issue with CPLD outputs being inverted. It never did > mention fixing the problem where I couldn't directly assign a > pin to 1 or 0 and have it work. Either way it came out as a > high. Now it works with 7.1.04. > > Right now, there isn't much I can say in polite company about > how this makes me feel. This bug has cost me several days time. > If I had been working on a real project at work, instead of > hobby tinkering at home, it would have cost the company a lot of > money in engineering time. > > I think it is rather irresponsible of them to not at least have > a notice on the download page for 7.1 saying you NEED the update > to 7.1.04 if you are using CPLDs. And what they really should > have done is taken down the 7.1 update and replaced it with a > 7.1.04 full download, and also have the 7.1.04 update available > for those who already have 7.1 installed. > > Many thanks to you Marc, and to everyone else who posted their > ideas. Now I can get on with my original project, and maybe > have some fun and learn something with CPLDs and FPGAs.Article: 94314
Mike Harrison wrote:
> I realise that & is probably not the right operator..
Andy is correct.
I can't use any operator as an alias.
An alias is just an alternate name for a slice
of an existing variable or signal.
Your example is more than a simple rename.
> Seems a bizarre limitation if this is not possible but then again the more I use VHDL the more I'm
> surprised at how primitive and unfriendly it is in some respects...!
It's not the only one.
VHDL started as a simulation language.
There are many language features
like alias, block, wait, etc that
seem like they ought to be useful
for synthesis, but just aren't.
-- Mike Treseler
ps:
David Bishop said it best:
"VHDL was written by a bunch of software guys who knew nothing about
designing hardware. We beat on it until you could do hardware with it.
Verilog was written by a bunch of hardware guys who knew nothing about
designing software. We beat on it until you could do software with it.
Neither does the job they were originally intended to do, but they work."
Article: 94315On Mon, 09 Jan 2006 11:07:39 -0800, Mike Treseler <mike_treseler@comcast.net> wrote: >Brendan Illingworth wrote: >> Thanks for the advice, however there is still have one issue. After the >> internal signal is added to the waveform and the simulation is restarted (by >> reissuing the .do command) the simulation restarts, but the newly add signal >> is removed from the waveform. What am I missing? > >A cut and past of the ADD WAVE command >from the modelsim command line to >the .do file. Or a save of the (modified) wave.do file ( = "save" in the wave window) - BrianArticle: 94316
Thanks All. Much appreciated. -Brian "Brian Drummond" <brian_drummond@btconnect.com> wrote in message news:o8j5s1t3g1kmk52ssv2vnrrb2dm1jjokll@4ax.com... > On Mon, 09 Jan 2006 11:07:39 -0800, Mike Treseler > <mike_treseler@comcast.net> wrote: > > >Brendan Illingworth wrote: > >> Thanks for the advice, however there is still have one issue. After the > >> internal signal is added to the waveform and the simulation is restarted (by > >> reissuing the .do command) the simulation restarts, but the newly add signal > >> is removed from the waveform. What am I missing? > > > >A cut and past of the ADD WAVE command > >from the modelsim command line to > >the .do file. > > Or a save of the (modified) wave.do file ( = "save" in the wave window) > > - BrianArticle: 94317
Thanks for the reply, John_H. My demod is from about 10MHz to 35MHz with a sample rate of 117MHz. I don't need much frequency resolution, say 1Hz or so, but I do require significant SFDR, 96dB. I started with the Xilinx System Generator CORDIC SINCOS block and modified it to take in a Z input and increased the number of iterations or PEs. It looks like I may be running into arithmetic errors as you suggested. I don't if the Xilinx cores are using quarter-wave tables or not, but I do know that there data sheets claim the lower phase res. blocks uses full-wave and the larger phase DDS's do not. I don't know if it's half-wave or quarter-wave or what, but I would think the ROM address behavior should give me a clue.Article: 94318
Subhasri krishnan wrote: > Thanks for the reply. But consider the following scenario. After the > power up sequence, I open a row in bank n followed by multiple > read/writes. The last read/write to the current bank has auto precharge > enabled. So when I want to activate a row in bank m for the first time, > should I issue an active command and is that meaningful because there > is no example showing read/write with auto precharge interrupted by > active command to another bank (or has this not been shown because > during row activation we dont care about the DQ's? ). When the datasheet talks about interrupting, they mean that a read or write burst is interrupted by another read or write cycle. Once the precharge happens, you have to wait Trp time before issuing another command. From page 10: "The bank(s) will be available for a subsequent row access a specified time (tRP) after the PRECHARGE command is issued." and "Once a bank has been precharged, it is in the idle state and must be activated prior to any READ or WRITE commands being issued to that bank." > enabled. So when I want to activate a row in bank m for the first time, > should I issue an active command Yes, you have to issue an active command after a bank has been precharged, but each bank can have a row open simultaneously - you don't have to precharge Bank n in order to activate a row in Bank m. --- Joe Samson Pixel VelocityArticle: 94319
Thanks for the reply, Ray. I think the 6dB per bit makes sense intuitively. I will be experimenting with it. I believe I am running into rounding errors with the Xilinx reference design as is, and need to control the LSBs as you mentioned above. I will also look at smarter look-up table approaches as well. This application is for a channelizer and synthesizer that is moderately large (24x2 downconverted channels, 24 upconverted channels) and may be too large for a traditional DDC type approach. I am looking at FFT approaches as well such as Polyphase DFT and WOLA. However, I don't want to completely rule out a "smart" DDC design, especially with very large oversampling, 400+.Article: 94320
Mike, It is like there is a limit on the number of files that can be open. I jsut ran into it trying to open Xilinx ISE7. Memory usage was only at around 790M out of 2GB. It just wouldn't let Xilinx project manager open. Closing Synplify let me open Xilinx.Article: 94321
Marc Guardiani wrote: > You're welcome. When I read that your outputs were inverted I knew what > the problem was immediately. > > I lost about a week's work on this one last year and really tore into > the Xilinx FAEs about not posting the patch directly on the download > page. It is precisely this sort of attitude by Xilinx that has me using > Altera for all new designs (start the Xilinx vs. Altera debate!). Yes, they do seem to have lowered emphasis on CPLD - Xilinx's are now the oldest families on the market, with both Altera & Lattice having newer CPLD families. The OP should stick with the SW that works, but I'd also suggest future download of the V8.1 into a parallel install, just to see what they have added - and it is quick to go back... Good SW version control, archives the tools with the designs, and this is another example of why this matters... Since the OP knows ABEL, but is new to both Xilinx tools, and their CPLDs, I'd also suggest some parallel ABEL code, just to check 'what's possible', if a similar issue occurs again... -jgArticle: 94322
Brady Gaughan wrote: > Thanks for the reply, Ray. I think the 6dB per bit makes sense > intuitively. I will be experimenting with it. I believe I > am running into rounding errors with the Xilinx reference design as is, > and need to control the LSBs as you mentioned above. > > I will also look at smarter look-up table approaches as well. > > This application is for a channelizer and synthesizer that is > moderately large (24x2 downconverted channels, 24 upconverted channels) > and may be too large for a traditional DDC type approach. I am looking > at FFT approaches as well such as Polyphase DFT and WOLA. However, I > don't want to completely rule out a "smart" DDC design, especially with > very large oversampling, 400+. > Brady, What kind of sample rates are you dealing with? 24 channels isn't much if the sample rates are reasonable. 24 Channels is fairly light for a polyphase channelizer, so the FFT can be physically quite small even for high data rates. The polyphase channelizer means the channels are equally spaced instead of being independently tuned, but you already know that. For example, I did a 160 channel DDC for a customer about 2 years ago in a 2v6000 that had input sample rates ate 2M and output sample rates at 50K. Each channel is independently tuned, and the output rate is the same for all 160 channels. I just finished a 10 channel DDC design in a V4SX55 that samples at 500MHz and has variable downsampling from 62.5MHz on down for a beamforming reciever. Each channel is independently tuned (each FPGA services one antenna element). It's 70% or so full 4VSX55, clocked at 250 Mhz.Article: 94323
The pci bridge used is powerspan II from tundra http://tundra.com/DST/PowerSpanII.cfm I dont think so I need a pci core. I am not sure about the pci core function but I feel it is same as what on-board pci bridge does. Right now At reset the powerpc running linux on it does the initialization I guess. I think I have to customize the vhdl interface at the front end which interfaces the fpga with the bridge and add a functionality of configuration.What I reaaly need to do after that is configure the bridge with right images in the registers at powerup. Then I need to figure out a way to do DMA transfer. I am trying to create a list of powerup functions( images,addresses) and the timing diagram for the data and address phases to do the dma.Then will start writing the code. I hope I am on the right track. Thanks, NiteshArticle: 94324
Ray Andraka wrote: > Mike, > > It is like there is a limit on the number of files that can be open. I > jsut ran into it trying to open Xilinx ISE7. Memory usage was only at > around 790M out of 2GB. It just wouldn't let Xilinx project manager > open. Closing Synplify let me open Xilinx. Does sound more like a files handles type issue - you could do a simple recursive script, that opens a couple of hundred files, and see where that falls over ? That would confirm #Files ceiling, and you could run it on another XP box ? Has it always had the ceiling, from new ? -jg
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