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fpga_toys@yahoo.com wrote: snipping, kind of tired of being told software taking over hardware design, it ain't > The Google description for this group is: Field Programmable Gate Array > based computing systems, under Computer Architecture FPGA. And, after > a few years, I think we are finally getting there .... FPGA based > coputing instead of CPU based computing. > > The days of FPGA's being only for hardware design are slipping away. > While this group has been dominated by hardware designers using FPGA's > for hardware designs, I suspect that we will see more and more > engineers of all kinds here doing computing on FPGA's, at all levels. While thats likely somewhat true and I really welcome anyone with interesting content problems, I suspect it's already too late for new comers without strong EE backgrounds or associates. 15 years ago FPGAs were pretty darn simple and not much use for anything but glue logic. Good ole days when any old CMOS logic slapped together just worked. Synthesis just around the corner. 10 years ago they got big enough but not performance enough to start to make predictions about RC and the possibly of replacement of general purpose cpus with hardware computing ie the 4000 days and a couple of new companies to boot. ASIC design started to get harder. 5 years ago with Virtex I'd say they started to get the ASIC performance with the embedded blocks and specialized IO resources making performance almost even to cover the much slower LUT blocks, and we also got the hugely more complex data sheets. Today most FPGAs seem to have the whole kitchen sink in there to make complex systems more practical if the sink can be made small enough to hide cost when not used. Look at any data sheet for modern parts, maybe 5% or less could be understood by your avg SW engineer (far less I bet), the rest is all electrical stuff, signal integrity, power supplies, packaging, reliabilty, clocking in no particular order. Ask around here for books on FPGA computing, there aren't any, there all old shit 10yrs or more from the easy days. I have one that covers the 3000 series. Ray has one coming and it sure ain't targeted at software guys, he's too busy with real work, as are most EEs with a job to write up their current knowledge. FPGAs are simply moving too fast to be documented for the laissez faire user. SW engineers with the mathematical applications are used to dealing with ready made PC boxen, give enough ventilation and hot math shouldn't faze a P4. There really isn't anything available in the same sense of off the shelf FPGA computing that can be sold as a std board to all the math, idea guys with out HW pain. Yeh there are lots of FPGA PCI cards but they are mostly not useable to software guys without some EE around as well as hardware lab tools. So that means a special application likely needs special boards to be built. Welcome to the real world, power supplies, interfaces, SI, GHz IO's, lead free. They haven't tought that in school in CS ever, and perhaps maybe some EE schools too. I can feel pretty sure that EEs that don't know this won't get much work. I suspect logic classes are going to be with us too for ever. When I interviewed candidates that don't know basic bool algebra but would like to do mil gate designs, I'd say let you know later, or let them know what they need to know. Is that job protection, sure it is, EEs don't want Joe90 liability around, bad ASIC design kills companies. We are going the same place with FPGA systems, bad designs will never work but only the project is lost, not million $ mask sets. My last employer's FPGA project cost far more than previous predecessor full custom mixed signal ASIC, it had lots of nice new math in it to figure out. Even really good EEs make logic mistakes, so some further abstractions are likely but that doesn't help much with all the dirty backend EE stuff. >From time to time we have had a few math, bio guys come here with questions about their interesting problems, but what I noticed is that they seem to be pretty coy about what they are upto. I suspect the days of SW engineers coming to the FPGA party are already over. FPGAs are getting bigger and more interesting but a darn site harder to use and that won't ever get covered up by synthesis tools. Also from what I have seen of some of the applications of FPGAs to computing v PC computing, the FPGA projest didn't even match the PC solution on cost. Not because the FPAG doesn't have the grunt but because too much was left on the table since the design was done by math oriented people. Now as I said before cpu designers have decided to go the same way FPGA are, packing density plus any incremental clock speed so its a parallel race again. My gut tells me that PC computing is still the best way to go if a plain C description works using 32 bit int math and esp FP math. But when the math looks like crypto with S boxes and shuffles or has dedicated IO interface, FPGAs cream all over. Multi disciplined teams are the future but EEs won't be in the back seat. I am done John Jakson transputer guy Marlboro MA BTW I don't know how to change brake pads or do oil changes (or even spell) so none of the above makes diddly squat.Article: 97551
cs_posting@hotmail.com wrote: > Jan Panteltje wrote: > >> Just a partial reply... I think 7400 series should stop way below 200mHz, >> perhaps 50MHz? > > It's either a 74AC04 or possibly a 74HC04 (it's upside down so I can't > tell) and it's self oscillating at 294 mhz - (it's stable enough for > the counter to read... a fast scope shows it approximately as a > sinewave. > > It seems to be oscillating at about 1/tpd... can't even really pull it > much with finger capacitance - only about 10 mhz. > > Interestingly, if I short a the floating input-output pair of an unused > inverter with the scope probe, that runs a bit slower around 260 mhz... > wheras the gate in use has about 20k of resistance in the feedback > path. > >> I would make a small diff amplifier, did something 40 years ago (yes 40!) >> with I think it was BFY90 transistors, then invert with 2 more and drive >> the LVDS input. > > I may give your transistor circuit a try, either with components or > simulation, thanks. There are some newer low voltage CMOS gates that are much faster than AC series, I think they are called LVC and a few other names depending on the manufacturer. The really fast ones don't support 5V supply operation because they are made on a fine geometry process. This also makes them faster. It would be very hard to stop it from self oscillating with no input signal. In order to have a meaningful way of determining if you have satisfied this requirement for not self-oscillating, you would first have to define what is the minimum input amplitude that you expect it to be able to accept and produce an output with reasonable duty cycle etc. Another approach would be to make an input buffer that does self oscillate and make a separate detector that measures the input signal amplitude and disables the measurement when the input amplitude is below a certain threshold. Chris ChrisArticle: 97552
On 23 Feb 2006 05:26:19 -0800, "Nicolas Matringe" <nic_o_mat@msn.com> wrote: >Hello all >I am trying to estimate the size of a project which will include an >ARCnet interface. >I don't have access to the ARCnet spec (not freely available) at the >moment so I can not give any number. >If anyone has good pointers or a quick rule of thumb... >Thanks in advance >Nicolas >PS don't tell me I will need the spec, I already know :o) A *very rough* estimate would be to look at the size of a 10Base-2 Ethernet Phy + MAC. Sure, the implementation will be totally different, but the basic functions and speed are equivalent. You may need a few k bytes of buffer ram, but this may be shared with your system ram if you're short of chip area. IIRC, Arcnet drives a rather large signal (some V p-p) into a 93 ohm cable. You will probably need a heavy duty driver just to get the current. It may turn out to be more cost effective to use a separate chip for that. The last time I designed one of these, I used a fastish opamp (LM6061?) and an LH0002 to drive the cable. That was for a one-off, cost-insensitive project. Regards, AllanArticle: 97553
"Eric Smith" <eric@brouhaha.com> wrote in message news:qhy80169ru.fsf@ruckus.brouhaha.com... > logjam wrote: >> Now on to my question. Is there a simple combinatorial design for >> division? > > No that I've ever heard of. If there was, everyone would be using it. > Sure there is, one can do a division by cascading stages together without using registers and clock. However it a) is really, really, slow for propagation delay. And b) uses a lot of hardware (2 to 3 times as much as for multiplication). Since division is rarely used most designers seem to go with a clocked divider. Why not use use the built in multiply operation of most HDL's ? One can usually code something like a = b * c, and it will generate an optimal design for any given architecture. rob<remove>@birdcomputer.caArticle: 97554
cs_posting@hotmail.com skrev: > The other day I found myself needing a short gate time ~200 mhz > frequency counter for an automated test, and since I had an FPGA board > on hand I whipped one up quickly. Getting it reading and reporting to > my computer was the easy part. > > Ah, the input stage.... > > I've got about 4dBm of RF into 50 ohms to play with - about a volt p-p > or a little more if it's high-Z. The output of the device under test > has a transformer and then a series cap to create an unbalanced output. snip The FPGA already has a balanced input, lvds. have you tried that with a few resistors or maybe a RC filter on signal to set the treshold on one input and the signal on the other input? or maybe even a cap into a cmos input biased to close but not quite vcc/2 1Vpp should be plenty, think the thresholds for ldvs is max 100mv -LasseArticle: 97555
<benn686@hotmail.com> wrote in message news:1138663735.633208.259520@g47g2000cwa.googlegroups.com... >I thought it might be a relatively fun and easy project to do a > audio/video (coax or rca) matrix that can take any number of n inputs > and route them to any n ouputs (1 to 1, 1 to all, etc). > How about using a crosspoint switch chip ? ( I think I got the right term). I was looking at one of these a while ago as an interrupt signal router, but I think they handle analog just fine. RobArticle: 97556
Does anyone else find the cover art of the 1Q2006 Xilinx Xcell journal
to be rather ironic, given how much Xilinx likes to trumpet their low
power consumption compared to the other leading brand (e.g., Xilinx
advertisement on page 28 of the same issue)?
I'm still eagerly awaiting the February 2006 availability of the
Spartan-3E starter kit. Five more days to go, unless it slips again.
Today if I click on the Spartan-3E Starter Kit in the online store,
it takes me to a page declaring:
A technical problem has interrupted your session. We apologize for
the inconvenience this has caused you.
Article: 97557"Eric Smith" <eric@brouhaha.com> wrote in message news:qhpsldd3is.fsf@ruckus.brouhaha.com... > Does anyone else find the cover art of the 1Q2006 Xilinx Xcell journal > to be rather ironic, given how much Xilinx likes to trumpet their low > power consumption compared to the other leading brand (e.g., Xilinx > advertisement on page 28 of the same issue)? > > I'm still eagerly awaiting the February 2006 availability of the > Spartan-3E starter kit. Five more days to go, unless it slips again. > Today if I click on the Spartan-3E Starter Kit in the online store, > it takes me to a page declaring: > > A technical problem has interrupted your session. We apologize for > the inconvenience this has caused you. I got the technical problem some, too, but I didn't get it consistently. The link at the online store for the starter kit info ends in HW-SPAR3E-DK but should end in HW-SPAR3E-SK-US - make that change and you'll see there's now some documentation for the board! Wheeee!!!Article: 97558
<mnemo5@163.com> wrote in message news:1140684469.024703.273840@p10g2000cwp.googlegroups.com... >I am looking for a VHDL/Verilog sample program of Kalman filters. > Anybody > can help? > Implemenation of Kalman filters are highly system specific. A Kalman filters is typically processed algortihmically (cpus or dsps). I've never seen, or heard of, an rtl implemenation. TCArticle: 97559
I want the ability to build the whole computer using TTL logic, but also put it in an FGPA. I'm learning VHDL as I go. Since the code is generated from my TTL schematic, I can test the giant circuit before I produce a PCB and solder hundreds of chips. Just a thought, but wouldn't the delay using cascading stages without a clock take just as much time as if you used a clock? Instead of using the same stage over and over again its just duplicated? I think what I will do is use the 64bit ALU that supports subtraction and addition, throw in two shift registers, and a state machine to control timing.Article: 97560
On Fri, 24 Feb 2006 00:41:09 GMT, "TC" <noone@nowhere.com> wrote: > ><mnemo5@163.com> wrote in message >news:1140684469.024703.273840@p10g2000cwp.googlegroups.com... >>I am looking for a VHDL/Verilog sample program of Kalman filters. >> Anybody >> can help? >> > >Implemenation of Kalman filters are highly system specific. A Kalman filters >is typically processed algortihmically (cpus or dsps). I've never seen, or >heard of, an rtl implemenation. > >TC > Check this one out: http://www.dspia.com/receiver/receiver.html. This is an Extended Kalman filter and it has been implemented in Verilog. The naive implementation has 33 multipliers in it. A reformulated one needs 26 multiplications and the RTL implementation has two multipliers scheduled over 16 cycles.Article: 97561
Hi.. Thanks for your input. > I also had the same problem, but after i patched the UCF for > ml310_base_design.zip everything worked fine... > One of the questions that I have is where is your DDR (on the PLB or on > the OPB)..I have ours set up on the OPB and everything works fine... I've already patched the UCF (rewrite actually - coz I have different net names). I have it on my PLB - that might be the thing that I should try. But, it shouldn't be a problem right? > I've had similar problems with MicroBlaze designs (not PPC). I was > able to use the memory only after reseting the board after programming. Yupp.. it will show successful test for all 3(32-, 16- & 8-bit test) after a few (not one) reset - but still, it's not stable.. it still fail some tests (but not all. -k.az-Article: 97562
"mk" <kal*@dspia.*comdelete> wrote in message news:9amsv19bsqck4s6ai982nsvc0rka1lu0g3@4ax.com... > On Fri, 24 Feb 2006 00:41:09 GMT, "TC" <noone@nowhere.com> wrote: > >> >><mnemo5@163.com> wrote in message >>news:1140684469.024703.273840@p10g2000cwp.googlegroups.com... >>>I am looking for a VHDL/Verilog sample program of Kalman filters. >>> Anybody >>> can help? >>> >> >>Implemenation of Kalman filters are highly system specific. A Kalman >>filters >>is typically processed algortihmically (cpus or dsps). I've never seen, or >>heard of, an rtl implemenation. >> >>TC >> > > Check this one out: http://www.dspia.com/receiver/receiver.html. This > is an Extended Kalman filter and it has been implemented in Verilog. > The naive implementation has 33 multipliers in it. A reformulated one > needs 26 multiplications and the RTL implementation has two > multipliers scheduled over 16 cycles. Thanks for the pointer! TCArticle: 97563
logjam wrote: > I want the ability to build the whole computer using TTL logic, but > also put it in an FGPA. I'm learning VHDL as I go. Since the code is > generated from my TTL schematic, I can test the giant circuit before I > produce a PCB and solder hundreds of chips. > > Just a thought, but wouldn't the delay using cascading stages without a > clock take just as much time as if you used a clock? Instead of using > the same stage over and over again its just duplicated? I think what I > will do is use the 64bit ALU that supports subtraction and addition, > throw in two shift registers, and a state machine to control timing. The thing is though, that this method will use an exorbitant amount of hardware. This will also result in a long path and will be very slow due to propogation delay. On top of that it will depend on your logic family, I believe the 74F series is the fastest? Anyway the TTL chips will either be fairly slow or consume power like crazy. Given the amount of chips you will need I wouldnt be surprised if the current draw of your divider alone hit into the amp range. A clocked division (using the shift and subtract method) is fairly simple to implement in an FSM. Not only that you will be a bit a clock, and all you need is a some registers, some combinatorial logic to determine the next state and the D FF's to hold the current state. That will be easier for you to solder and consume far less power too! A remainder in a few clock cycles I think isnt too much of a compromise.Article: 97564
Fred Bloggs wrote: > >... but what > > would make sense today? > > > > http://www.onsemi.com/PowerSolutions/product.do?id=MC100EPT21DR2 That sounds like a good idea, because theoretically we actually have some on hand somewhere, I'll have to see if I can scare them up. While connecting to the FPGA directly would be simpler, I do like the idea of using an external chip as a bit of a 'fuse'. (Though transformer coupling into the FPGA should reduce some risk)Article: 97565
The whole ALU with multiplier will take around 2.5 amps. :)Article: 97566
logjam wrote: > The whole ALU with multiplier will take around 2.5 amps. :) WOW, ~13W ALU!!! Why not use an FSM based divider?Article: 97567
Thanks for your help. Actually, what I want to do is to make a hardware implementation(FPGA) of an Extended Kalman Filter of a tracking system(It works well in Matlab). I am a beginner of FPGA,so can anybody give me some suggestios? Thank you ~~Article: 97568
Before I tried to put the OPB master port to my custom coprocessor, I
did the
following simple test:
MB1
MB2
|
|
FSL
FSL
(Master and slave) (master
and slave)
|
|
-----------------------------------------------------------------------------
Cutom Coprocessor
So my cutom coprocessor will have two FSL links with each connected to
MB1 and MB2. Becasue creat/import
peripheral wizard only supports one link, I did the following manually,
In my
CustomIP core, I declare:
entity CustomIP is
port
(
-- Contact with MB0
MB0_FSL_Clk : in std_logic;
MB0_FSL_Rst : in std_logic;
MB0_FSL_S_Clk : out std_logic;
MB0_FSL_S_Read : out std_logic;
MB0_FSL_S_Data : in std_logic_vector(0 to 31);
MB0_FSL_S_Control : in std_logic;
MB0_FSL_S_Exists : in std_logic;
MB0_FSL_M_Clk : out std_logic;
MB0_FSL_M_Write : out std_logic;
MB0_FSL_M_Data : out std_logic_vector(0 to 31);
MB0_FSL_M_Control : out std_logic;
MB0_FSL_M_Full : in std_logic;
-- Contact with MB1
MB1_FSL_Clk : in std_logic;
MB1_FSL_Rst : in std_logic;
MB1_FSL_S_Clk : out std_logic;
MB1_FSL_S_Read : out std_logic;
MB1_FSL_S_Data : in std_logic_vector(0 to 31);
MB1_FSL_S_Control : in std_logic;
MB1_FSL_S_Exists : in std_logic;
MB1_FSL_M_Clk : out std_logic;
MB1_FSL_M_Write : out std_logic;
MB1_FSL_M_Data : out std_logic_vector(0 to 31);
MB1_FSL_M_Control : out std_logic;
MB1_FSL_M_Full : in std_logic
);
attribute SIGIS : string;
attribute SIGIS of MB0_FSL_Clk, MB1_FSL_Clk : signal is "Clk";
attribute SIGIS of MB0_FSL_S_Clk, MB1_FSL_S_Clk : signal is "Clk";
attribute SIGIS of MB0_FSL_M_Clk, MB1_FSL_M_Clk : signal is "Clk";
end CustomIP;
{.......}
And in the .mpd file, I declared:
BEGIN CustomIP
## Peripheral Options
##OPTION IPTYPE = PERIPHERAL
OPTION IMP_NETLIST = TRUE
OPTION HDL = VHDL
OPTION CORE_STATE = ACTIVE
OPTION IP_GROUP = MICROBLAZE:PPC:USER
## Bus Interfaces
BUS_INTERFACE BUS = M0SFSL, BUS_TYPE = SLAVE, BUS_STD = FSL
BUS_INTERFACE BUS = M0MFSL, BUS_TYPE = MASTER, BUS_STD = FSL
BUS_INTERFACE BUS = M1SFSL, BUS_TYPE = SLAVE, BUS_STD = FSL
BUS_INTERFACE BUS = M1MFSL, BUS_TYPE = MASTER, BUS_STD = FSL
## Generics for VHDL or Parameters for Verilog
## Ports
PORT M0FSL_Clk = "", DIR = I, SIGIS = Clk, BUS = M0SFSL:M0MFSL
PORT M0FSL_Rst = OPB_Rst, DIR = I, BUS = M0SFSL:M0MFSL
PORT M0FSL_S_Clk = FSL_S_Clk, DIR = O, SIGIS = Clk, BUS = M0SFSL
PORT M0FSL_S_Read = FSL_S_Read, DIR = O, BUS = M0SFSL
PORT M0FSL_S_Data = FSL_S_Data, DIR = I, VEC = [0:31], BUS = M0SFSL
PORT M0FSL_S_Control = FSL_S_Control, DIR = I, BUS = M0SFSL
PORT M0FSL_S_Exists = FSL_S_Exists, DIR = I, BUS = M0SFSL
PORT M0FSL_M_Clk = FSL_M_Clk, DIR = O, SIGIS = Clk, BUS = M0MFSL
PORT M0FSL_M_Write = FSL_M_Write, DIR = O, BUS = M0MFSL
PORT M0FSL_M_Data = FSL_M_Data, DIR = O, VEC = [0:31], BUS = M0MFSL
PORT M0FSL_M_Control = FSL_M_Control, DIR = O, BUS = M0MFSL
PORT M0FSL_M_Full = FSL_M_Full, DIR = I, BUS = M0MFSL
PORT M1FSL_Clk = "", DIR = I, SIGIS = Clk, BUS = M1SFSL:M1MFSL
PORT M1FSL_Rst = OPB_Rst, DIR = I, BUS = M1SFSL:M1MFSL
PORT M1FSL_S_Clk = FSL_S_Clk, DIR = O, SIGIS = Clk, BUS = M1SFSL
PORT M1FSL_S_Read = FSL_S_Read, DIR = O, BUS = M1SFSL
PORT M1FSL_S_Data = FSL_S_Data, DIR = I, VEC = [0:31], BUS = M1SFSL
PORT M1FSL_S_Control = FSL_S_Control, DIR = I, BUS = M1SFSL
PORT M1FSL_S_Exists = FSL_S_Exists, DIR = I, BUS = M1SFSL
PORT M1FSL_M_Clk = FSL_M_Clk, DIR = O, SIGIS = Clk, BUS = M1MFSL
PORT M1FSL_M_Write = FSL_M_Write, DIR = O, BUS = M1MFSL
PORT M1FSL_M_Data = FSL_M_Data, DIR = O, VEC = [0:31], BUS = M1MFSL
PORT M1FSL_M_Control = FSL_M_Control, DIR = O, BUS = M1MFSL
PORT M1FSL_M_Full = FSL_M_Full, DIR = I, BUS = M1MFSL
END
I hope this will work. But it seems that I have to import it for the
CustomIP visible to the XPS project. So I imported it by telling the
system the .mpd file and the source .vhd file and choose no link(OPB,
FSL, PLB....). Then when I tried to declare my connection in system.mhs
file, the system give me the error that there is no interface M1MFSL,
M1SFSL, M0MFSL, M0SFSL as I expected. Also the CustomIP which was
imported in the system show "encrpted source" and won't show my source
.vhd file.
Do I miss somthing here? Would you please give me some suggestion or
what document should I read?
Thank you so much.
Article: 97569
I am so sorry about the figure, here it is:
MB1 MB2
| |
FSL FSL
(master and slave) (master and slave)
| |
---------------------------------------------------------
Custom IP
Article: 97570Logjam, it is hard for a rader of this newsgroup to understand why you are doing what you are doing. Why a combinatorial divider, when division is a rare operation, and sequential circuits are more efficient? And why insist on a 30-year old technology? If you had picked a 50-year old technology, you would use Germanium transistors, diodes, resistors, and capacitors, and you would really learn the very details of circuit design. (I did, it was fun while there was nothing better available!) Or a 20-year old technology, using AMD bit-slice (2900) chips? Or a 10-year-old original FPGA technology (XC3000), where all logic is implemented in LUTs and flip-flops? If you absolutely want to make life tough for yourself, what is so special about 1975-vintage circuits? Just nostalgia, and those lovely yellow books? Peter Alfke, Xilinx Applications ======================= logjam wrote: > Frist a little bit of information before my question. I don't know > where the best place is for this question. I'm building a 64bit ALU > using standard TTL devices. I made a 4bit adder with fast carry, > combined 4 of those with 16 AND gates (ends up as a 4x4=8bit > multiplier), and then combined 64 groups to provide 15 partial products > to a wallace tree (which I also had to make a model for). A final > summing adder takes the two partial products from the wallace tree and > adds them together. This final summing adder is built using 181 and > 182 TTL devices, so I can also subtract and preform basic logic > operations if necessary. > > I basically followed the datasheet from Texas Instruments from 1975. > ;) I had to make models of the 74274 and 74275 because they weren't > included as standard Altera macros I guess (which is very > understandable... ;) ) > > Anyway, my schematic program produces an EDIF netlist which I'm able to > import into Altera's software and compile and simulate my schematic for > their FPGA devices. I've been simulating my project with great > success. So we are on topic with the whole FPGA thing. :) > > Now on to my question. Is there a simple combinatorial design for > division? So far the whole schematic is made using "Combinatorial > logic"? I'm not sure that's the right word. The ALU can perform any > function without clock inputs, its also faster than a lot of the other > methods I've found. For example, calculating one partial product at a > time for multiplication. > > For more info on the multiplication circuit I've described you can look > at the datasheet below. On page 7-398 through 7-400 is a schematic for > a 16x16 bit multiplier. Mine is pretty much the same, except mine is > 4x larger. This is the first time I've used D size schematic layout. > :) For more informatio > > http://www.tech-systems-labs.com/booksdata/TI-DATA-1976.pdf > > Any hints for what I should be looking for or links would be great. > Searching for combinatorial division I found what looked like to be > some good hits, but the website was in the CGI error mood. :(Article: 97571
On Thu, 23 Feb 2006 16:23:13 +1300, Jim Granville <no.spam@designtools.co.nz> wrote: >cs_posting@hotmail.com wrote: >> The other day I found myself needing a short gate time ~200 mhz >> frequency counter for an automated test, and since I had an FPGA board >> on hand I whipped one up quickly. Getting it reading and reporting to >> my computer was the easy part. >> >> Ah, the input stage.... > > Does the FPGA have LVDS option inputs ? >If it is new enough to have those, they are differential >amplifiers, designed for current mode signals, and will work >with thresholds << 1V. > IIRC the LVDS spec has +100mV and -100mV levels. >Normally, they need a common mode bias of just over 1V, and the >better ones will also tolerate rail-rail drive (on ONE ip), >but at reduced speed specs. >-jg Second that. We've tested the Xilinx Spartan3 LVDS inputs and they are excellent, super-fast comparators. JohnArticle: 97572
HI praveen TDO JTAG interfce pin u can give bank voltage it will not create any problem go ahead venkatArticle: 97573
can any one please suggest ways of configuring FPGA/CPLDs with streaming data without using their IDE's . thnksArticle: 97574
Hi ABS, simple answer : Use a free (commandline) tool.
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