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>>>>> Stacey Son <sson@hawaii.et.byu.edu> writes: Peter> You would need a sizeable FPGA for this, especially as the Peter> S-boxes have 6 inputs, and the CLBs have only 5 (how Peter> inconvenient!)... > I implimented DES on XC3090 a few years ago. Although, the S-boxes > did take a lot of resources a full DES design did fit on the 3090... I still think that (if you're doing straight ECB or CBC encryption or decryption) a slave DES processor such as the 95C68/18/09 or 20C03 will be cheaper and just as fast. Check out Newbridge/Tundra. (Of course, a DES cracking application may need a few unconventional hooks...) -- Roger Williams finger me for my PGP public key Coelacanth Engineering consulting & turnkey product development Middleborough, MA wireless * DSP-based instrumentation * ATE tel +1 508 947-8049 * fax +1 508 947-9118 * http://www.coelacanth.com/Article: 4026
Hello FPGA'ers, I am having an increasing need to DC time analyze (with Synopsys DC timing analyzer) back-annotated designs from Altera. More in detail: After exporting the *.edf (Synopsys FPGA-Compiler generated) to MaxPlusII (Rev 6.2), and compiling it with 'Verilog netlist writer - with SDF output' option turned on, I am trying to perform a Synopsys DC Timing Analysis on the Altera generated *.vo VERILOG files - to no avail. Synopsys is unable to read in the Altera GENERATED *.vo Verilog files (it failed on non-synthesizable code). The next step - 'read_timing *.sdf' - is of-course irrelevant - since the first step failed. Is there an available methodology today where I can generate a netlist from Altera, with back-annotated timing, such that Synopsys can read & perform critical paths DC Timing Analysis ? (I have tried the combination of *.edo (Altera EDIF Out) netlist with *.sdf - to no avail). Alex Koegel DSPC Israel Ltd.Article: 4027
Andrew Metcalfe (metcalfe@iaccess.com.au) wrote: : I have a Pentium 166 with 64Mb RAM, 2.1G disk and Win95. Foundation won't : install correctly (crashes). Even the coretools install program crashes... : I believe it is my system, not the tools, but I can't find anything : extraordinary with my system. : Anyone else had problems in this area? I'd certainly appreciate some help! : -Andrew Metcalfe Well, I'm using XACT6.0 and this won't work either with WIN95. The reason is simple : the software needs win32s. So I installed win3.11 and win95 on the same computer, and everything runs fine now. kindly regards, Kim -- ============================================================================== ************************************ * Hofmans Kim * * * * tw38966@vub.ac.be * * khofmans@info.vub.ac.be * * * * Brouwerijstraat 62 * * 1630 Linkebeek * * Belgium * * * * 32-2-3771012 * * * ************************************Article: 4028
We are currently using PC based Xilinx P&R S/W. On a Pentium-133 with 80Meg of RAM it takes anywhere from 1.5 to 2 hours. In order to reduce the run time, we are looking at workstation version of S/W (to run on Ultra Sparc) or purchasing Pentium Pro. Can anyone make recommendation as to which might be a better solution as far as the run time is concerned?Article: 4029
Hi, this is my 2nd request for address, FAX or e-mail
address of XILINX and ALTERA HQ in the States.
Please send the real address with valid FAX number as soon as possible.
Thank you very much in advacnmce for your help.
regards
(MULIANI)
103103350.1222@compuserve.com
--
Article: 4030In article <50kg23$qkd@news.service.uci.edu> cho@newport.ece.uci.edu (Jae Cho) writes: >We are currently using PC based Xilinx P&R S/W. >On a Pentium-133 with 80Meg of RAM it takes >anywhere from 1.5 to 2 hours. In order to reduce >the run time, we are looking at workstation version >of S/W (to run on Ultra Sparc) or purchasing Pentium Pro. >Can anyone make recommendation as to which might be a >better solution as far as the run time is concerned? Floorplan your designs.Article: 4031
In article <50hfgq$3te@quagga.ru.ac.za>, ray@rucus.ru.ac.za (Ray Heasman) wrote: > Mark Smotherman (mark@hubcap.clemson.edu) wrote: > : I would like to get pointers to any work on custom computing > : machines that transform selected C (or Fortran) routines into > : FPGA netlists. I have found papers and links to PRISM-II, being > : done at the Lab for Engineering Man/Machine Systems at Brown > : University. Are there other configuration compilers available, > : either at universities or from vendors? There's a bunch of work on translating software languages (especially C) to hardware. Below are my notes on many of them, which are going into a survey of software for reconfigurable systems that I'm working on. I'll have a less terse version in a week or so. If anyone knows of any others, I'd appreciate pointers to them. Transmogrifier C [Galloway95] - no multiply, divide, pointers, arrays, structures, recursion. Adds pragmas to declare width of variables, and methods for declaring inputs & outputs (w/pin assignments). If statements becomes equations (condition & assignment combined). Control flow becomes control FSMs, with states for each loop, function call, etc. One thread of control per program, but multiple programs can be combined. Spyder [Iseli95] - no multiply or divide, only bitvector variables. Very restricted language. Intended to design operators to be put into FPGA hardware. Then, code is written to run on the processor & use these new execution units. PRISC [Razdan94b] - Automatically goes from assembly to FPGA (won¹t do memory ops, floating point, wide adds, multiplies, divides, variable shifts). Selects which portion is mapped to FPGA logic, though seems somewhat rudimentary. PRISM [Athanas93] - User picks which subroutines to convert to hardware. Converts C to hardware. No global variables or state, restricted bandwidth, fixed iteration count for loops, no floating point, no case or do-while. PRISM-II [Wazlowski93, Agarwal94] - extends PRISM to include variable-length loops, whiles, switch. Still no structs, floats, or pointers. Direct conversion from C to VHDL or X-BLOX. Then optimizes control-flow to speed up control FSM. [Wo94] - RECON¹s compiler. Can¹t handle multiply, division, modulous, function calls. Straightforward C to FPGA. User decides what to map based on profiling, only a complete function can be mapped. [Clark96] - Standard retargettable compiler for DISC. Allows one to include calls to hardware subroutines into the code (though interface code must be hand-made). REFERENCES [Clark96] D. A. Clark, B. L. Hutchings, ³The DISC Programming Environment², IEEE Symposium on FPGAs for Custom Computing Machines, 1996. [Wo94] D. Wo, K. Forward, ³Compiling to the Gate Level for a Reconfigurable Co-processor², IEEE Workshop on FPGAs for Custom Computing Machines, pp. 147-154, 1994. [Wazlowski93] M. Wazlowski, L. Agarwal, T. Lee, A. Smith, E. Lam, P. Athanas, H. Silverman, S. Ghosh, ³PRISM-II Compiler and Architecture², IEEE Workshop on FPGAs for Custom Computing Machines, pp. 9-16, 1993. [Agarwal94] L. Agarwal, M. Wazlowski, S. Ghosh, ³An Asynchronous Approach to Efficient Execution of Programs on Adaptive Architectures Utilizing FPGAs², IEEE Workshop on FPGAs for Custom Computing Machines, pp. 101-110, 1994. [Athanas93] P. M. Athanas, H. F. Silverman, ³Processor Reconfiguration Through Instruction-Set Metamorphosis², IEEE Computer, Vol. 26, No. 3, pp. 11-18, March, 1993. [Iseli95] C. Iseli, E. Sanchez, ³A C++ Compiler for FPGA Custom Execution Units Synthesis², IEEE Symposium on FPGAs for Custom Computing Machines, 1995. [Galloway95] D. Galloway, ³The Transmogrifier C Hardware Description Language and Compiler for FPGAs², IEEE Symposium on FPGAs for Custom Computing Machines, 1995. [Razdan94b] R. Razdan, M. D. Smith, ³A High-Performance Microarchitecture with Hardware-Programmable Functional Units², International Symposium on Microarchitecture, pp. 172-180, 1994. > : What is the state-of-the-art in taking a C function that uses > : floating-point and compiling it to FPGAs? Is there any kind of > : automated scaling for changing floating-point (w/ ranges on the > : input variables) into integer-only replacements, and thus easily > : into FPGAs? (I've seen Dan McCracken's 1957 textbook that shows > : how to do this by hand, but I wonder if it has been automated > : and integrated into a configuration compiler. PRISM-II doesn't > : do flt-pt.) Basically floating-point is one of the big issues with FPGA-based systems. By and large, people don't do it. As you can see from the above list, it just isn't supported. Primarily I beleive the reason is the high hardware costs (you could hit dejaNews about 6 months ago for a discussion in this group on floating point in FPGAs). So, if you want someone else's work to use, I don't think it's out there. If you want an interesting research project, this could be it (however, my take on floating point is that it should be left in a processor/DSP/coprocessor instead of trying to shoehorn it into an FPGA). If you're going to do work on this, make sure to take a look at the DSP community. I think they've had to do a lot of this kind of stuff for fixed-point DSPs, though I'm not an expert on this area. Good luck, and let me know how things turn out. Scott +-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-+ | Scott A. Hauck, Assistant Professor | | Dept. of ECE Voice: (847) 467-1849 | | Northwestern University FAX: (847) 467-4144 | | 2145 Sheridan Road Email: hauck@ece.nwu.edu | | Evanston, IL 60208 WWW: http://www.ece.nwu.edu/~hauck | +-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-+Article: 4032
In article <32261971.60F4@ccm.sc.intel.com> Deepak Tripathi <Deepak_Tripathi@ccm.sc.intel.com> writes:
> From: Deepak Tripathi <Deepak_Tripathi@ccm.sc.intel.com>
> Newsgroups: comp.arch.fpga
> Date: Thu, 29 Aug 1996 15:28:01 -0700
> Organization: Intel Corp.
> Reply-To: Deepak_Tripathi@ccm.sc.intel.com
>
> Hello All,
> This is possibly a FAQ:
> How do I go about getting myself a generic fpga toolkit (PC/Windows NT)?
> This is purely for non-commercial purposes and hence the price tag has
> to be very attractive :-). I would defn. like to get a high-quality
> toolkit but I obviously need information on the kind of trade-offs I'd
> have to make (or be forced to make as would most likely be the case)
> if I don't intend to part with a lot of cash. Also is it too unrealistic
> to expect a completely generic toolkit that can target a variety of fpga
> families in the bargain basement?
>
> Is there a web-site/archive where I might find relevant information? If
> any of you have experience/opinions to share, that'll be very welcome
> as well.
>
> Thanks in advance,
>
> Deepak "How cheap can I get, that's the question" Tripathi.
>
> Deepak_Tripathi@ccm.sc.intel.com
>
> NOTE: The opinions expressed are entirely my own and do not reflect
> those of my employers.
The generic toolkit of choice, IMHO is the Galileo toolkit from
Exemplar Logic (now a part of Antares, www.antaresco.com). It will
allow you to target most all FPGAs, many CPLDs, and also ASICs. I
believe that the PC price tag is not bad, but I don't know what your
budget is.
--
---------------------------------------------------------------------------
Dave Matthews djm@papillonres.com
Papillon Research Corp. http://www.papillonres.com/~papillon
52 Domino Dr.,
Concord, MA 01742 Providing Full Product Development
Phone - 508-371-9115 including:
FAX - 508-371-9175 * System Architecture
* ASIC and FPGA Design
* VHDL/Verilog Modeling & Synthesis
* EMI - EMC Consulting Services
----------------------------------------------------------------------------
Article: 4033
In article <50kg23$qkd@news.service.uci.edu> cho@newport.ece.uci.edu (Jae Cho) writes:
> From: cho@newport.ece.uci.edu (Jae Cho)
> Newsgroups: comp.arch.fpga
> Date: 4 Sep 1996 17:59:31 GMT
> Organization: University of California, Irvine
>
> We are currently using PC based Xilinx P&R S/W.
> On a Pentium-133 with 80Meg of RAM it takes
> anywhere from 1.5 to 2 hours. In order to reduce
> the run time, we are looking at workstation version
> of S/W (to run on Ultra Sparc) or purchasing Pentium Pro.
> Can anyone make recommendation as to which might be a
> better solution as far as the run time is concerned?
Have you tried to an incremental place and route? This uses that
previous place and route information, and only rips up what it has to.
It usually speeds up the process quite a bit.
--
---------------------------------------------------------------------------
Dave Matthews djm@papillonres.com
Papillon Research Corp. http://www.papillonres.com/~papillon
52 Domino Dr.,
Concord, MA 01742 Providing Full Product Development
Phone - 508-371-9115 including:
FAX - 508-371-9175 * System Architecture
* ASIC and FPGA Design
* VHDL/Verilog Modeling & Synthesis
* EMI - EMC Consulting Services
----------------------------------------------------------------------------
Article: 4034
John Cooley <jcooley@world.std.com> wrote:
>The biggest surprise came when I later compiled the 36 additional responses
>from EDA employees. This group was three times as likely (42 percent versus
>the EDA users' 13 percent) to grant Cadence's injunction. And EDA makers
>were twice as likely (53 percent vs. 27 percent) to see the courts as
>competent -- which helps explain why the EDA industry is so litigious!
>
>This result from the survey still kind of stumps me. Why are EDA vendors
>significantly more legalistic than their customers? I can't seem to figure
>this one out. Any insights anyone?
David E. Wallace <wallace@netcom.com> wrote:
>Uh, yeah. Can you say "small sample size"? For a sample of 36 EDA
>employees, the difference between the expected and actual percentages
>is about 9-10 responses. Throw in the fact that it's a self-selected
>sample, and things get even worse. So if EDA employees in general
>hold exactly the same opinions as EDA users, but you also got responses
>from a dozen or so Cadence/ex-Cadence employees who followed the
>company line, you would get the kind of results you report here.
Only two Cadence employees and one Avant! employee responded (which didn't
change the EDA vendor stats significantly.)
Concerning your sample size is too small & self selection reasoning, from
my sometimes questionable memory of a statistics course a zillion years
ago as a sophmore engineering student, I remember that these two arguements
aren't factors here. That is, the 36 EDA Vendors and 311 EDA Users both
used the *same* selection process, so comparisions *can* be made between
the two populations. In addition, there obviously is some sort of real
difference in the way the two groups see the world on *this* issue
because of the strong similarities between these two populations (both
are computer literate engineers who know something about electronic
design software.) The only distinction is that one group buys EDA
software while another group makes EDA software. Not that much of a
disjoint difference. It's not like comparing EDA users to, say...
left-handed, Laplander lesbians.
- John Cooley
Part Time EDA Consumer Advocate
Full Time ASIC, FPGA & EDA Design Consultant
===========================================================================
Trapped trying to figure out a Synopsys bug? Want to hear how 4599 other
users dealt with it ? Then join the E-Mail Synopsys Users Group (ESNUG)!
!!! "It's not a BUG, jcooley@world.std.com
/o o\ / it's a FEATURE!" (508) 429-4357
( > )
\ - / - John Cooley, EDA & ASIC Design Consultant in Synopsys,
_] [_ Verilog, VHDL and numerous Design Methodologies.
Holliston Poor Farm, P.O. Box 6222, Holliston, MA 01746-6222
Legal Disclaimer: "As always, anything said here is only opinion."
Article: 4035I am running a verilog design through synopsys fpga-compiler, and then into the xilinx place and route software. I really want to place things in this design for speed. I can get at least a factor of 2 in speed by careful placement of certain modules. The way things seem to go, every time I run synopsys I have large parts of the placed design become unplaced due to gate names begin changed. Some flop names change too, but these are usually associated with mis-synthesized clocked bidirectional IO pads, and you give up and manyally instantiate those. I try labeling begin-end blocks, and that doesn't help. Module names staying the same doesn't seem to be enough. I try to generate combinational logic manually inside always @(a or b or c) out = a ^ b ^ c; blocks, so that important gates have names that stay constant across synthesis runs. I seem to end up with "U5932" and "N5678", which are trouble. Lots of flops DO stay put. But about 90% of the design is in parts of the design hierarchy called "Primitives" and my favorite "U". These are doomed. I want my placed gates to stay put. If I were to call Xilinx or synopsys, my guess is that they would say "you are the first person to ever ask for that". I wouldn't mind being able to put pragmas in the verilog to do source level relative placement of modules, and bounding boxes on them too. So to you experienced designers, the hundreds of other people who have also been the first one to think of this, are there any tricks that I am missing? LawrenceArticle: 4036
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Article: 4037In article <50kg30$338$1@mhafn.production.compuserve.com>, muliani <103350.1222@CompuServe.COM> wrote: > > Hi, this is my 2nd request for address, FAX or e-mail >address of XILINX and ALTERA HQ in the States. >Please send the real address with valid FAX number as soon as possible. >Thank you very much in advacnmce for your help. >regards >(MULIANI) >103103350.1222@compuserve.com Altera is a very large corporation with hundreds if not thousands of phone and fax numbers as well multiple addresses for differnet buidlings. What do you want to ask about? If we knew that, perhaps we could help. --------------------------- Wayne (waynet@indirect.com)Article: 4038
testArticle: 4039
Hi everybody,
I have a description of a simple, generic ripple-carry adder circuit in our
own Lola HDL, but I would like to translate that description to the more
popular languages VHDL and Verilog. Can anyone give me a hand?
Thanks,
Stefan H-M Ludwig mailto:ludwig@inf.ethz.ch
http://www.inf.ethz.ch/personal/ludwig
Institute for Computer Systems
Swiss Federal Institute of Technology (ETH)
CH-8092 Zurich, Switzerland
Phone: 41-1-632 7301
Fax : 41-1-632 1307
Lola HDL for the definition and use of a generic ripple-carry adder:
MODULE Add;
TYPE AddElem; (* full adder *)
IN x, y, ci: BIT; (* inputs: 2 data, carry *)
OUT s, co: BIT; (* outputs: sum, carry *)
VAR h: BIT; (* half sum *)
BEGIN
h := x-y; s := h-ci; (* two XORs *)
co := x*y + h*ci (* two ANDs and one OR *)
END AddElem;
TYPE Adder(N); (* generic N-bit full adder *)
IN x, y: [N] BIT; ci: BIT; (* inputs: 2 data vectors + carry *)
OUT s: [N] BIT; co: BIT; (* outputs: sum vector + carry *)
VAR add: [N] AddElem; (* using N full adders *)
BEGIN
add.0(x.0, y.0, ci); (* unit assignment: add two bits *)
(* then ripple-carry *)
FOR i := 1 .. N-1 DO add.i(x.i, y.i, add[i-1].co) END;
FOR i := 0 .. N-1 DO s.i := add.i.s END;
co := add[N-1].co
END Adder;
CONST N := 8;
IN x, y: [N] BIT; rd: BIT;
INOUT D: [N] TS;
VAR adder: Adder(N); (* instantiation of generic *)
BEGIN
adder(x, y, '0); (* unit assignment (with vectors *)
(* x and y and the constant zero) *)
FOR i := 0 .. N-1 DO
D.i := rd | adder.s.i (* rd controlled tri-state assignment *)
END
END Add.
Article: 4040
Hi All,
I'm currently in a process of evaluating to select a FPGA
vendor for my next coming task (FPGA based PCI bus interafce design)
If you have any experiences related to FPGA based PCI designs
and want to share the experiences then I would like to hear from you.
Which FPGA vendor out there did you select for your last PCI bus
interface designs.
or Which following FPGA vendors:
Altera
Actel
AT&T (ORCA)
QuickLogic
Xilinx
... and more
who you believe is providing the best FPGA based PCI technology
PCI core (initiator/target) source code available,
PCI 2.1 compliance
Zero wait state for Read/Write burst mode
Design tools (industry supports)
Engineering supports
to customers regarding to cost/performance.
Your opinion/suggestion means a lot to me and are much appreciated
Thanks,
-quy dinh
Article: 4041VHDL System Solutions P/L, based in Melbourne, Australia are looking for additional distributors for Setanta ED, their PC based HDL Editor productivity tool. A 45-day version of Setanta ED is available for download from : http://www.vhdl.com.au Setanta ED runs under Windows 3.1, Windows 95 and Windows NT. Setanta ED is feature rich and is based on ED for Windows, the programmer's source editor of choice. Please send all e-mail responses to: gcro@vhdl.com.auArticle: 4042
Here is information on contacting Xilinx. This is taken from
our Web site at http://www.xilinx.com
HEADQUARTERS
XILINX, Inc.
2100 Logic Drive
San Jose, CA 95124
(408) 559-7778
TWX: 510-600-8750
FAX: 408-559-7114
You can contact a Xilinx technical support engineer using the following
methods:
North American Support
Hotline: 1-800-255-7778 or (408) 879-5199 (M-F 8am-5pm Pacific)
Fax: (408) 879-4442
Email: hotline@xilinx.com
BBS: (408) 559-9327
United Kingdom Support
Hotline: +44 1932 820821 (M-F 9:00am-12:00pm, 1:00-5:30pm)
Fax: +44 1932 828522
Email : ukhelp@xilinx.com
BBS: +44 1932 333540
France Support
Hotline: +33 1 3463 0100 (M-F 9:30am-12:30pm, 2:00-5:30pm)
Fax: +33 1 3463 0109
Email : frhelp@xilinx.com
Germany Support
Hotline: +49 89 991 5490 (M-Th 8:00am-12:00pm, 1:00-5:00pm, F
8:00am-12:00pm, 1:00pm-3:00pm)
Fax: +49 89 904 4748
Email : dlhelp@xilinx.com
Applications : DSP DSP@xilinx.com
PCI PCI@xilinx.com
Plug&Play PnP@xilinx.com
PCMCIA PCMCIA@xilinx.com
Reconfigurable Computing RTR@xilinx.com
Article: 4043Hi! I am looking for a PCI compliant FPGA which has at least 5k Gates. Moreover it must be more than one time programmable and the place & route software should be free or very cheap (since I am a student and need it for my private purposes). As I found out, Motorola offers a free version of their software, but unfortunately their devices aren't PCI compliant. Thank you very much in advance. TobiasArticle: 4044
Sounds pretty damn fast to me :-) Whether it is or not depends on (a) device type/size (b) % utilisation and (c) effort settings used for P&R..... -- Regards AndyGArticle: 4045
I think what your problem is major. In any case, the problem will occur.
ex. Your computer have over 32MB RAM and your computer's VGA chip is S3.
Please try what connect to Xilinx BBS or Xilinx FTP Server, and download
the '/pub/swhlp/aldec/w32s13c.zip' file and install it.
In article <01bb99a5$4f1d6280$fc15aa85@d1pc_fuseda.miya.fujifilm.co.jp>,
fuseda@miya.fujifilm.co.jp says...
>
>Hello
>I have problem using XACT STEP 6.0.1.
>I cannot install win32S software.
>Installation software says "successfully installed."
>But FREE CELL game soft causes MS-DOS error 21.
>And the setup soft does not go on.
>
>The O.S. of my PC is DOS6.2 and windows3.1.
>And any other versions of XACT or Windows
>have not been installed in my PC.
>
>I tryed this setup with Compac Prolinea 5133
>and Fujitsu FMV 5133ED4.
>In both case, I have same result.
>
>Does anyone know a good solution?
>Any help is greatly appreciated.
>
>Thanks in advance,
>
>- Yuichi
----------------------------------------------------------------------
itoh@st.rim.or.jp (private)
itoh@marubun.co.jp (business)
Article: 4046>> Hi, this is my 2nd request for address, FAX or e-mail >>address of XILINX and ALTERA HQ in the States. >>Please send the real address with valid FAX number as soon as possible. >>Thank you very much in advacnmce for your help. >>regards >>(MULIANI) >>103103350.1222@compuserve.com From the Xilinx data book: (408) 559-7778 Fax (408) 559-7114 From the Altera data book: (408) 894-7000 Fax (408) 944-0952Article: 4047
In article <50kg23$qkd@news.service.uci.edu>, cho@newport.ece.uci.edu (Jae Cho) wrote: >We are currently using PC based Xilinx P&R S/W. >On a Pentium-133 with 80Meg of RAM it takes >anywhere from 1.5 to 2 hours. In order to reduce >the run time, we are looking at workstation version >of S/W (to run on Ultra Sparc) or purchasing Pentium Pro. >Can anyone make recommendation as to which might be a >better solution as far as the run time is concerned? Use Altera.Article: 4048
Hi everyone, In many engineering and design publication, I've heard of Warp2, which is a VHDL behavioral synthesis for Cypress programmable logic. They claim that their software offers better synthesis than 20 000.00$ packages, with IEEE standards synthesis, simulation output, auto fitting and plac-and-route, etc. all this for 99.00$. Being a student, I can't afford very expensive FPGA's or PLD's development system, but I'd like to know if anyone of you tried this software, and what was the performance like. Because even at 99.00$ I want to make sure that it's worth the money. Thanks a lot, Patrick Jarry, computer and electronics engineering student --Article: 4049
I am a senior EE student, and I need to do a senior design project by May. I want to use a FPGA to do something useful, and I have a few ideas. Does anyone have any good ideas or suggestions? Let me know, please. Brad bwalla@unf.edu
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