Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
DTHIBAUL <DTHIBAUL@mailgw.sanders.lockheed.com> wrote: >When I run Viewlogics Prosim under Windows 3.11 the program states >that I have only about 1 Meg of memory available (which is not enough to >load anything even moderately big). When I run any of the other Pro >Series tools (i.e. Procapture or Prowave) they report I have 75Meg of >memory available. MSD also says I have plenty of memory. Anyone ever >seen this problem and have any hints??? I'm running ProSim as purchaced from Xilinx. I don't see a 1M message. I just see a message stating that my memory is all used up and would I like to save everything before quitting. ProSim then just bails out, back to PROFlow. This happens after 16000 net name equivalencies have been logged to the screen. CD6.0.1\xbbs\utils\xmem\xmem.exe shows plenty of everything when it quits. This is a real time display of resources you can run while running ProSim. My design uses about 38% of the D-flops in a 4025E (fewer func gens.) Xilinx says, 'ProSim has size limitations.' This will be rectified by the move to WorkView Office with Xilinx's next maintenance release, early November. I suppose you could buy WVO from ViewLogic. $$ I am able to Pro-simulate this same ckt. when I moved it to the XC5215. It's easy. Altran is automatically invoked under Win-doz when you try to switch. Then I move it back to 4025E for P&R and timing analysis. Are we having fun yet? My other DSP blocks are smaller and haven't had this problem. I'm very glad ProSeries is DEAD! I hope WVO is better. ??? Dave DeckerArticle: 4076
Richard Jozefowski <richard@milliped.demon.co.uk> wrote: . . . >So, has anybody got any advice for me? Is it worth attempting to move to >ORCA, bearing in mind that a lot of my designs require signal processing at >13.5 and 27 MHz? What are your views on the Viewlogic PRO Series? Would >Workview Office (or whatever it's called) be better under Windoze '95? >-- >Richard Jozefowski >Millipede Electronic Graphics I've just finished evaluating as many FPGA packages as I could manage, I was looking for DSP specific entry tools, and efficiency (FPGA functions per dollar) of DSP ckts. with a 25MHz. sample rate. This design is about 100k gates. (4 or 5ea 4025Es I'm hoping.) I have the same ORCA demo. It's still sitting on my desk, unopened, for the same reason. We have 3 seats of the "Xilinx only" ProSeries package. No ViewLogic Sentinel key, so can't run the ORCA demo. ORCA support has an XNF to ORCA translation program though, and was kind enough to port and compile a benchmark for me. It was a constant multiply of an 11bit input, requiring 2 adders. Why not ask them to do the same for you? They refused to translate the full FIR filter, claiming it had too many Xilinx macros. (They need a flat design for the translation to be automatic.) The benchmark was not quite as efficient (functions per dollar) as Xilinx 5200 series, but was faster. It was equivalent to the Xilinx 4025E-4. When we checked on big ORCA parts availability though, the prospects were bleak, so we're using 4025E, at least for our bread boards, The above mentioned FIR design, 10 bits in, 10 bits out, 21 taps, with full pipelining, uses 38% of a 4025E's flops, and cannot be simulated by ProSim. Xilinx admits ProSim has some size limitation. I think it may be because I used a lot of 16bit macros (Registers. Adders and AddSubs) from the Unified Library to capture 10, 11 and 12 bit functions. I have a feeling ProSim counts all those unused gates, even though the Xilinx trimming software will later prune them all away. Perhaps, if I constructed adders of just the right size I would not have had this problem. I was able to do a satisfactory functional simulation, however, by using the nice Win-doz based ALTRAN program to quickly move the whole project to the XC5215, for simulation, then back to 4025E for Place and Rout and timing analysis. The design uses fewer CLBs in the 5200 series, of course, since there are 4 flip-flops per CLB. I understand this ProSim size limitation will be rectified, with the next Xilinx maintenance release, early November. This release will switch to WorkView Office but still run on Win 3.1(1). BTW, it took me 4 days on the phone with Xilinx to finally enable the 6.0.1 software for the 4025E chip on my PC. I must have been the first one to try this! Xilinx Hot Line knows the magic combination now, so others shouldn't have the same problem. My advice: Check for chip availability, before you waste much time running demos. If the ORCA chips you need are available in the time frame you want, then ask ORCA support to run a small bench mark for you, from your XNF. If that looks good, then maybe you should buy the tools you need. Dave Decker ddecker@diabloresearch.comArticle: 4077
Since I'm cranked up now, I'm now going to ramble on a little about my search for DSP tools, that started with my cry for help, to this news group, a few weeks ago. Thanks to all who replied with suggestions. For the record, I found no tools for the capture of efficient DSP adders, and constant multipliers, or full multipliers. I could coerce anything to work, but I had to explicitly teach each tool how to do an efficient constant multiplier. I had to explicitly do sign extension on adders etc. etc. If I have to do everything myself, I might as well use schematic capture. Here are a couple of useful things I did find: Philip Freidin (fliptron@netcom.com) showed me an extreemly clever way to make ViewLogic do most of the work of quickly creating low "ones" density constant multipliers using mux $arrays that all disappear 'POOF' after trimming. The mux $arrays are used to select buses representing the input data in the correctly shifted positions for subsiquent addition. Since the mux selection lines are connected only to VCC or GND (via an easy to capture system of schematic 'plugins') the mux arrays degenerate to hard connected wires when the logic is simplified. Philip cautions that although this could work for non Xilinx designs, not all logic trimming software may be as exhaustive as XNFPREP. The Xilinx DSP group, does have some wonderful full multipliers, that can be modified to the size you need. They also have some pre-released software you might be able to talk them out of, which uses "distributed arithmetic" techniques for implimenting DSP functions. Think of doing a FIR with no multipliers! They use look-up tables for LSB multiplies, then accumulate all LSB products accross the whole FIR before shifting the sum and working on the next least significent bits. These FIRs should be nearly as efficient as a custom FIRs, but easialy synthesizable in minutes. No need to worry about low "ones" density coeficients either. Altera's DSP kit is not efficient at all, but the AHDL plus operator, "+" (not part of the DSP kit) seems to work well if the right switch is enabled. All the FPGA houses, and tool venders I talked to said "Come back in 6 months or a year," we're working on just the tools you're looking for. We are having fun now! David Decker ddecker@diabloresearch.comArticle: 4078
In article <Dx8B4o.KBo@world.std.com>, John Cooley <jcooley@world.std.com> wrote: :John Cooley <jcooley@world.std.com> wrote: :>The biggest surprise came when I later compiled the 36 additional responses :>from EDA employees. This group was three times as likely (42 percent versus :>the EDA users' 13 percent) to grant Cadence's injunction. And EDA makers :>were twice as likely (53 percent vs. 27 percent) to see the courts as :>competent -- which helps explain why the EDA industry is so litigious! :>This result from the survey still kind of stumps me. Why are EDA vendors :>significantly more legalistic than their customers? I can't seem to figure :>this one out. Any insights anyone? :David E. Wallace <wallace@netcom.com> wrote: :>Uh, yeah. Can you say "small sample size"? For a sample of 36 EDA :>employees, the difference between the expected and actual percentages :>is about 9-10 responses. Throw in the fact that it's a self-selected :>sample, and things get even worse. So if EDA employees in general :>hold exactly the same opinions as EDA users, but you also got responses :>from a dozen or so Cadence/ex-Cadence employees who followed the :>company line, you would get the kind of results you report here. :Only two Cadence employees and one Avant! employee responded (which didn't :change the EDA vendor stats significantly.) :Concerning your sample size is too small & self selection reasoning, from :my sometimes questionable memory of a statistics course a zillion years :ago as a sophmore engineering student, I remember that these two arguements :aren't factors here. That is, the 36 EDA Vendors and 311 EDA Users both :used the *same* selection process, so comparisions *can* be made between :the two populations. In addition, there obviously is some sort of real :difference in the way the two groups see the world on *this* issue :because of the strong similarities between these two populations (both :are computer literate engineers who know something about electronic :design software.) The only distinction is that one group buys EDA :software while another group makes EDA software. Not that much of a :disjoint difference. It's not like comparing EDA users to, say... :left-handed, Laplander lesbians. Ok, I didn't realize the number of EDA users responding was so big, and the number of Cadence employees responding was so small. Given that, yeah, if you can count on the responses being representative of their respective populations, you do have statistical evidence of a difference between the two groups. At least that's what the formula for the difference of the means of two binomial distributions from my old stat text seems to tell me. (The differences in the proportions are 4.5 and 3.2 standard deviations away from the expected mean if the populations were identically distributed.) I'm still concerned about the self-selection bias, though. I'm concerned that the group of EDA vendors who would respond to such a survey may not be representative of EDA vendors in general in the same way as the group of EDA users responding is representative of EDA users in general. That's because the question is closer to home for the EDA vendors, and may affect some types of vendors more closely than others. Given the small number of EDA vendor responses, even a small self-selection bias might have large effects on the overall results. -- Dave Wallace (wallace@netcom.com) It is quite humbling to realize that the storage occupied by the longest line from a typical Usenet posting is sufficient to provide a state space so vast that all the computation power in the world can not conquer it.Article: 4079
In article <ant0809581cbC&sp@milliped.demon.co.uk>
richard@milliped.demon.co.uk "Richard Jozefowski" writes:
"
"Aren't the ORCA back-end place and route tools written by NeoCAD? If these
"are worse than the Xilinx tools (eg ARP/PPR), then I wonder why Xilinx
"acquired NeoCAD and why Xilinx's much delayed next release will be based on
"the NeoCAD tools. Apparently Lucent (ex AT&T) had rights to the NeoCAD
"source code so, when they were acquired by Xilinx, they took the code and
"(they claim) some of the key NeoCAD development personnel and set up shop
"across the road in Boulder. I wonder how much of this is sales bluster.
"
Yes, you're quite right about this. Xilinx paid an eight-figure sum
for NeoCAD as I recall. Yes, the NeoCAD s/w was better, and yes,
they did take on several NeoCAD people.
IMHO, both the ORCA product and s/w is OK by industry standards (in
fact, very good for some types of design, such as DSP) , as is the
Viewlogic WorkView Office 7.2 toolset.
David Pashley
Article: 4080I wrote: >> the software is a bit more primitive. I have several 2c12 and 2c15 >> designs routed at 50MHz. All of them required extensive hand placement >> and routing which is not easy with the ORCA software. Richard Jozefowski richard@milliped.demon.co.uk responded:: > Aren't the ORCA back-end place and route tools written by NeoCAD? If these > are worse than the Xilinx tools (eg ARP/PPR), then I wonder why Xilinx > acquired NeoCAD and why Xilinx's much delayed next release will be based on > the NeoCAD tools. Apparently Lucent (ex AT&T) had rights to the NeoCAD > source code so, when they were acquired by Xilinx, they took the code and > (they claim) some of the key NeoCAD development personnel and set up shop > across the road in Boulder. I wonder how much of this is sales bluster. I was referring to the primitive user interface. The NeoCad place and route software was probably the best at the time and consistantly beat xilinx in the benchmarks that I did. I don't think ANY software could place and route my designs at 50MHz. The ORCA 7.1 user interface is about 1 generation behind Xilinx. According to some Xilinx folks, the NeoCad routing core was especially good at large designs. I don't think this was the primary reason for Xilinx to buy NeoCad. The real benefit (to Xilinx) was that it closed off an easy and safe migration path from Xilinx to Orca. Why would anyone have bought Xilinx tools when for the same price, you could get a tool for Xilinx, Orca and many others? Since Orca was better (and cheaper), Xilinx would have lost a lot of business. I wrote: >> I use Workview-Office which is even worse than workview-pro. Unfortunately >> wv-office won't work with the current ORCA version unless you throw a fit >> and demand a proper license. Lucent claims to have its 9.0 release out >> soon. If at all possible, I'd try to avoid buying in to viewlogic. Richard Jozefowski richard@milliped.demon.co.uk responded:: > My ORCA Foundry evaluation kit is version 7.1. Sounds like I'm a bit out of > date. No. As far as I know 7.1 is the most current version. I don't know what happened to 8.0. Maybe marketing determined that 9 sounds better than 8. > Are you suggesting there will be another, hopefully better, schematic > entry system available with the 9.0 release? Come to think of it, it is > hard to imagine one worse. The Orca software takes EDIF inputs. Presumably, you could use any CAD system as a front end. My suggestion re. Viewlogic was just a rule of thumb: once you do a design using some tool, you're stuck with the tool till that design is obsolete. I've invested a lot of effort into making libraries and tools for Viewlogic. It would be difficult for me to change now, but if I was starting today, I would certainly look at any alternatives.Article: 4081
Constantin Jean-Claude jclaude.constantin@eiv.vsnet.ch wrote: > We are currently using EPROM 254k Bit from Xilinx to store our XE4000 > configuration. They are bloody expensive. > Do you know any second source or even better a compatible EEPROM ? Atmel has some. Beware of Lucent (AT&T) parts: they STILL have a problem at power up if the power supply rises too slowly.Article: 4082
DTHIBAUL wrote: > > Maya Reuveni wrote: > > > > hi everybody, > > I designed a board with 5 xilinx devices > > 2 xc4013E & 3 xc4005H > > I daisy chained all the parts and connected to the xchecker connector. > > I made a xxx.mcs (xxx.exo too) into a 128K bytes prom > > and the done signal did not go high ..... > > any ideas why ? > > what should I check ? > > thanks > > -- > > > > Maya Reuveni Tel: 972-9-986976 > > Manager of Hardware Department Fax: 972-9-986980 > > HaTaasiya 9, Raanana 43100, Israel. E-mail: maya@asp.co.il > > First thing to check is that the preample is coming out of each chip at > the start of program. It should be present with 1 CCLK delay for each > chip in the daisy chain. Xilinx has an app note with many hint on thier > web site - it's worth downloading. i found xilinx documentation for generating the prom files required when multiple devices are connected in series is minimal. unfortunately there is nothing in the prom generating software to warn you either. with this many xilinx devices daisychained you should have multiple serial proms. check the ceo/ pin out of each prom and verify each one gets enabled. you can see the preamble coming out of each xilinx device and still not complete programming. the problem is probably the way the prom file was generated. first you have to merge all the individual bit files together into one prom file. then copy psplit.exe from the utilities directory of the xact6.0 cd, it doesn't get installed with xact6.0. run psplit to split up the merged prom file into individual prom files, it prompts you for the prom size(s) desired.Article: 4083
Richard Jozefowski wrote: > > I'm looking at moving from using Xilinx to ORCA FPGAs... > The only PC based schematic entry system supported appears to be the > Viewlogic PRO Series running under Windoze 3.1/3.11. Richard - Synario 2.3, just released on CD, supports ORCA via its schematic entry system, as well as ABEL-HDL and VHDL. It runs under Windows 3.11, 95 and NT. A 30 day free evaluation is standard. check out www.synario.com or call 1-888-SYNARIO. -Tom Bowns Synario Design AutomationArticle: 4084
Ray Andraka wrote: > > Brad Wallace wrote: > > > > I am a senior EE student, and I need to do a senior design project by > > May. I want to use a FPGA to do something useful, and I have a few > > ideas. Does anyone have any good ideas or suggestions? Let me know, > > A real good project that would be impressive to your prof, and would give > you a great deal of extra knowledge would be a scientific calculator that > can do the basic four fucntions plus all the trig, inverse trig, > hyperbolic trig and thier inverses, logs, exponents, squares and square > roots, and rectangular-polar conversions. It sounds complex, but don't > panic. ... Well, but what is it good for? So far I cannot see why it would make sense to implement things in FPGAs that you can buy for a few cents elsewhere. Yet there is a similar idea that might be interesting. Somewhere in Hennessy & Patterson's "Computer Architecture" they talk about the ultimate RISC-processor, the SIC (Single instruction computer). the proposed instruction is: sbn a,b,c -- i.e. subtract a from b, write the result to a and branch to c if the result is negative. The code density is bad, the computational speed is compromised too, but it seems to me that such a machine will be actually useful if you need an intelligent processor just for initialisation and similar purposes, but not for number crunching. It costs you not even hundred gates. The job is less HW-intensive (although you can play by making it parameterized (withs, parallel/ bitserial etc.), add a flexible bus interface and sell it as IP), but you can also implement an assembler with some pseudo-instructions (add, shift left,...), a compiler with trig, log, ... subroutines and all the rest. Or has anyone already built the SIC? Let me know what you think about it. Alfred -- My little grey cells speak for themselves, not for my company. But have a look at http://www.siemens.at mailto:alfred.fuchs@siemens.at Phone: 43/1/1707-34113Article: 4085
In article <wallaceDxGG88.MB9@netcom.com> wallace@netcom.com (David E. Wallace) writes:
>In article <Dx8B4o.KBo@world.std.com>,
>John Cooley <jcooley@world.std.com> wrote:
>:John Cooley <jcooley@world.std.com> wrote:
>:>The biggest surprise came when I later compiled the 36 additional responses
>:>from EDA employees. This group was three times as likely (42 percent versus
>:>the EDA users' 13 percent) to grant Cadence's injunction. And EDA makers
>:>were twice as likely (53 percent vs. 27 percent) to see the courts as
>:>competent -- which helps explain why the EDA industry is so litigious!
>
>:>This result from the survey still kind of stumps me. Why are EDA vendors
>:>significantly more legalistic than their customers? I can't seem to figure
>:>this one out. Any insights anyone?
Putting aside the statistics and sample size discussions, consider the
folowing:
The EDA users have expressed their opinion about this area, and it
affects their views of the vendors and probably their buying patterns
(including not buying a product due to disgust with behaviour).
Unless the sample of EDA vendor respondents included CEOs and Prez's etc,
the opinions of the EDA vendor respondents have little to do with what a
company does in this area, as these people have no influence on how or
why or when one EDA company sues another.
"Favorite EDA CEO": dial, dial, dial ...
"EDA CO Employee": ring, ring, ring, ... pickup
ECE: Hi, this is ECE, how may I help you?
FEC: Hi, this is FEC, and I'm calling all employees individualy to
ask their opinion.
ECE: OK!
FEC: Theirs a little company that has a product that does what one
of our products does, only they are better, cheaper, more
customer responsive, fewer bugs, better futures plan, more open,
less fattening, cures cancer, ...
What do you think we should do?
ECE: Sue 'em!
FEC: Great, thanks for your input. By the way, how did you enjoy the
latest re-org, where when all was said and done, we still had the
same people in charge, all the same projects were still being
worked on, my sacred cow project got slightly morre focus, the
reporting structure changed radically but the individual
contributors for each project didn't really change much, and we
spent 3 weeks in turmoil convincing every one that things would
be much better?
ECE: I can't say how much I thought it was a great change!
FEC: OK. bye.
ECE: bye.
Article: 4086Firstly please excuse me if I have commited any dredful wrongs in the way I have posted this but it is the first time I have posted to a newsgroup and I am neither full aware of the rules or exactly what my s/w is doing so please bear with me. On the subject of xchecker cables and downloading to the XC400 series parts in general. Firstly, as correctly stated, the xchecker cable is more than just an RS232/TTL converter. The xchecker cable is more involved because it has the capability of performing a readback of the internal status of the device. Furthermore the xchecker cable can also be reconfigured by the xilinx s/w to act as a TAP (test access port controller in order to perform JTAG downloads to the xc9500 family parts. This said however the circuit given may well work purely as a parallel port downloader but as the gentleman who posted it has only ever used it for xc3000 parts there is one point I would like to make. The xc4000 and xc5000 family parts differ from the xc3000s in that they have separate done and program pins. thus when using the old xilinx download cable for example, which has a done/program connection, the connetion should be made to the done pin. to pace the device in configuration mode simply turn of the power and turn it back on again. Also one question, will your eval kit allow you to save the .bitArticle: 4087
I am working on a little project that uses one XC40003E to implement a variable frequency pulse generator with built-in frequency counter with LED or LCD display. Total range: 200 MHz to 3 kHz in 16 ranges, each 2:1, using an external VCO from minicircuits. The challenge is not so much in the logic design ( that's practically done and takes only 60% of the device ), as in the physical design of the output section, to reduce ringing and maintain a 1 ns rise and fall time at 200 MHz. Output 50 Ohm. The poor man's hp. It's definitely something useful. Interesting variations would be non-50% duty cycle out at lower frequencies, or driving a Brooktree D-to-A converter to generate programmable waveforms. The poor man's Wavetek. e-mail me if you are interested. peter@xilinx.com Peter Alfke, Xilinx ApplicationsArticle: 4088
Hi, We recently baught the Xilinx Viewlogic extended package (DS-VLS-EXT) from Xilinx, because we want to use VHDL to target the Xilinx FPGAs. We were promised that we could both simulate and synthesize VHDL. Synthesizing VHDL is working, but I'm not able to simulate VHDL. My ViewLogic license explicitly says that VHDL simulation is possible, but neither the local Xilinx representatives nor ViewLogic can tell me how I should simulate VHDL with this package. So does anybody out there know if VHDL simulation is possible with this package and better yet how to do it ?Article: 4089
ecla@world.std.com (alain arnaud) wrote: > 3. Has anyone used other synthesis products: > Synopsys FPGA Compiler, > Synplicity Synplify, > Xilinx Foundation (Metamore), > Synopsys FPGA Express, > Data IO Synario, > Minc, > any other? > > 4. What do you like about the above products? > What do you dislike? > Limitations, bugs? > State machine support > On what basis did you select it. cost, functionality, availability, > tech support, platform, other? > > 5. What size devices have you implemented in VHDL? > > 6. Do you use schematic and VHDL or only VHDL? We have just baught the ViewLogic package, so i'm starting with ViewSynthesis, but I've use Synplify from Synplicity with the QuickLogic FPGA's as target. We used Verilog as Synplify supports both Verilog and VHDL. The speed of the compiler is very high, most simple designs are a synthesized in a couple of seconds. The quality of the output is very high. In a large number of cases the result is the same as you would obtain by drawing it with library parts. Only for the most timing critical pieces, I still use hard macro's for which I disable all optimisation. For these designs I mix schematic with HDL input, but for simple designs I only use the HDL. If Viewsynthesis performs as Synplify I would be very happy.Article: 4090
> I don't think this was the primary reason for Xilinx to buy NeoCad. The >real benefit (to Xilinx) was that it closed off an easy and safe migration >path from Xilinx to Orca. Why would anyone have bought Xilinx tools when for >the same price, you could get a tool for Xilinx, Orca and many others? Since >Orca was better (and cheaper), Xilinx would have lost a lot of business. This sounds quite plausible, and maybe you know for sure it is true. But it assumes that Xilinx really make a lot of their money selling software, in which case Xilinx may have simply been worried that Neocad would drop their prices. But Neocad showed little interest in offering value for money, when I last looked at them. They were very expensive tools, and buggy too, at the time. However, one *can* (please correct me if I am wrong) port a Xilinx design to another FPGA, if only one uses a library which is also usable for the other FPGA. I have only ever used *Xilinx* FPGAs, and their libraries. But most of the components in those libraries are trivial, like gates, counters, etc. It would take relatively little work to create a "universal" library which someone would sell to FPGA developers, and which would have all the Xilinx parts in it. The problem with that is that you would need an *unrestricted* version of Workview, which costs a fortune. Or a version of Workview which accepts this "universal" library. We are back to the Viewlogic "magic numbers". Maybe I am missing something. I thought that maybe the Xilinx P&R software accepts *only* netlists produced using Xilinx libraries, but I don't think that is true. I have done XNF files with CUPL -> PALASM -> PDS2XNF -> XNF. And even if Xilinx did this, it would be easy to produce a little program which fixes-up the magic number. Such a program has already been produced for Viewlogic schematics and libraries, some time ago. All you have to do is disassemble PDS2XNF, XNFOPT, or any of the other 3rd party programs which can produce XNF netlists (ABEL, CUPL), to see how these magic numbers are generated. Alternatively, one could go Xilinx -> Orca by translating the final netlist. The Xilinx library part names (e.g. DFF etc) would be replaced with the Orca names. It easy to translate these netlists with a simple C program, or even an AWK script. And going to an ASIC, via EDIF or whatever, is straightforward enough too. I am doing this right now. Having said this, I firmly believe Xilinx charge too much for their P&R tools, and so do Orca and most others. (IMO the firms who do sell their tools cheap are mainly those on the periphery of the FPGA market, whose FPGA products' future is therefore always in doubt). This does not make sense. These high prices are preventing so many small firms using FPGAs. One day, someone will drop a spanner into this club, and the sooner the better. Peter.Article: 4091
Alfred Fuchs wrote: > > Ray Andraka wrote: > > > > Brad Wallace wrote: > > > > > > I am a senior EE student, and I need to do a senior design project by > > > May. I want to use a FPGA to do something useful, and I have a few > > > ideas. Does anyone have any good ideas or suggestions? Let me know, > > > > A real good project that would be impressive to your prof, and would give > > you a great deal of extra knowledge would be a scientific calculator that > > can do the basic four fucntions plus all the trig, inverse trig, > > hyperbolic trig and thier inverses, logs, exponents, squares and square > > roots, and rectangular-polar conversions. It sounds complex, but don't > > panic. ... Before you get too carried away trying to implement a CRAY on your FPGA you may care to stop and consider what exactly you are trying to achieve. Is the point of your project to understand what is involved with implementing a digital design in an FPGA or is it just to understand the issues involved with implementing a complex digital design? If your project is mainly about the former then you would probably be better off choosing a fairly simple digital design to start with (if this is your first FPGA design). There is more than enough to learn going through the exercise of designing a digital circuit rigorously (eg synchronous design issues such as set-up and hold time calculations, metastability) as well as design capture decisions (schematics or VHDL), functionally simulating your design, placing and routing your design and then back-annotating timing information for more simulations. You need to choose what FPGA you are going to use, understand its architecture, understand how you are going to put that FPGA into another circuit to test it when its finished, etc etc .. If you are more concerned with investigating the design of a specific complex circuit you may be better off looking at capturing that design (schematics or VHDL) and then simulating it only. You can spend much time investigating the grillions of issues associated with achieving an optimum implementation of your design before you need get anywhere near an FPGA (eg for the above suggested design you need to decide what processors are to be used to perform the arithmetic, what wordlengths are required to achieve desired accuracy, can you use look-up tables for some functions or will they need to be computed ?? etc ..). It is easy to start off wanting to have the sexiest final year design project but remember its September now and you need to finish by May (dont forget you'll need 3-4 weeks to write up the design report plus all those pesky final year subjects to consider as well). It is easy to get a bit lost with an FPGA design. Of course it is nice to have a working circuit to hold in your hand at the end of the year. Also, if you get through the FPGA design cycle quickly and have a simple design already implemented by January, say, then you can concentrate on implementing a more complicated variant afterwards. Maybe you would be interested in implementing an FIR filter (Xilinx has app notes on this to get you started). This is quite simple to start with and can be expanded later on. You can change the filter coefficients to implement different types of filters and check out tradeoffs in filter length, sampling rate etc ... Have fun .. Andrew Phillips Design Engineer Cooperative Research Centre for Broadband Telecommunications & Networking Perth Western Australia P.S. above comments assume that you havent done much FPGA design before. If you are really good at it then by all means try for the more complex circuit.Article: 4092
Greetings all, I am interested to hear some responses from other designers about which FPGA design tools they use. I am currently using the following tools for Xilinx FPGA design: design entry - MGC Design Architect (schematics) functional simulation - MGC QHPro (mixed VHDL/schematics simulation) - I use Mentor's gen_arch utility to generate an entity and architecture for the top-level schematic I am simulating and then use VHDL testbench files to provide stimulus. map/place/route - Neocad foundry v7 timing simulation - MGC QHPro - I create an EDIF file from my placed and routed Neocad <design>.ncd file, create a design viewpoint using Mentor's ENREAD utility and then create a schematic of the post-layout design using Mentor's SG schematic generator utility. Then I need to use gen_arch to create an entity and architecture for the entire device and use VHDL testbench files to do post-layout simulation. I have not tried using recent XACT map/place & route software as my vendor suggested that its performance was not as good as the Neocad tools that we had already purchased - I am still waiting for the integrated XACT/Neocad tools. (Anyone know when they will be available - are they already available?) I am planning to use Mentor's Autologic 2 to handle VHDL design entry rather than using schematics. What pitfalls have others that have done this found?? Does anyone know whether it is possible to take a post-layout Neocad design and directly generate a VHDL model from it for simulation purposes (rather than having to generate schematics as I currently am). My vendor told me that, given the tools I had available, this was the best design method. Do others agree? Am I doing things the hard way? Thanks in advance for all responses. Andrew Phillips Design Engineer Cooperative Research Centre for Broadband Telecommunications & Networking Perth Western AustraliaArticle: 4093
In article <323483fc.115342@news.alt.net> ft63@dial.pipex.com (Peter) writes: > >However, one *can* (please correct me if I am wrong) port a Xilinx >design to another FPGA, if only one uses a library which is also >usable for the other FPGA. The issue is the version of viewlogic you use, not the library. The libraries from Xilinx (or other FPGA vendor that OEMs VL) contain security codes that stop them from being used with an OEM version of VL from another supplier. The Full feature version of VL from VL can handle any of the VL or OEM libraries. The other constraint (and this is the one that will slow you down ) is the netlister. The OEM versions come with only a netlister for the OEM libraries. So although you could create your own library to run with (for example) the Xilinx OEM version of VL, the symbols you create with that version of VL will have the security codes that will only let it be netlisted to XNF. There are ASIC conversion houses that will take XNF as input for an ASIC. > >I have only ever used *Xilinx* FPGAs, and their libraries. But most of >the components in those libraries are trivial, like gates, counters, >etc. It would take relatively little work to create a "universal" >library which someone would sell to FPGA developers, and which would >have all the Xilinx parts in it. > This would only work if they had the full version of VL. >The problem with that is that you would need an *unrestricted* version >of Workview, which costs a fortune. Or a version of Workview which >accepts this "universal" library. We are back to the Viewlogic "magic >numbers". > right. >Maybe I am missing something. I thought that maybe the Xilinx P&R >software accepts *only* netlists produced using Xilinx libraries, but >I don't think that is true. I have done XNF files with CUPL -> PALASM >-> PDS2XNF -> XNF. There are no security numbers in the XNF. Only in the VL libraries. Anyone can create XNF (and many do), and the spec for it is available to developers from Xilinx, as part of their alliance program. Many people have written their own XNF manipulation software without this spec, because XNF is human readable, and has little complexity to it. As an example, Altera has XNF input capability in their MAX+II software and I seriously doubt that Xilinx told them how to parse it. :-) >And even if Xilinx did this, it would be easy to >produce a little program which fixes-up the magic number. Such a >program has already been produced for Viewlogic schematics and >libraries, some time ago. All you have to do is disassemble PDS2XNF, >XNFOPT, or any of the other 3rd party programs which can produce XNF >netlists (ABEL, CUPL), to see how these magic numbers are generated. See above: no magic numbers in XNF. Disassembling PDS2XNF, XNFOPT, or other 3rd party netlist generator isnt going to help you. Plus it is a violation of the software license. :-) > >Alternatively, one could go Xilinx -> Orca by translating the final >netlist. The Xilinx library part names (e.g. DFF etc) would be >replaced with the Orca names. It easy to translate these netlists with >a simple C program, or even an AWK script. You will need to know both netlist formats to do this, and AWK type substitutions may not quite be enough. >Peter. PhilipArticle: 4094
Philip Freidin fliptron@netcom.com wrote: ft63@dial.pipex.com (Peter) writes: > [A bunch of theories as to how to convert Xilinx to Orca] Orca (NeoCad) software can read xnf or wir files and can use xilinx library parts directly (not xilinx-specific stuff, of course). A general-use Workview license (capture only) is about $2000. Viewlogic gave me $500 credit for my existing Xilinx-only license. (2 years ago). >> >>However, one *can* (please correct me if I am wrong) port a Xilinx >>design to another FPGA, if only one uses a library which is also >>usable for the other FPGA. > >The issue is the version of viewlogic you use, not the library. The >libraries from Xilinx (or other FPGA vendor that OEMs VL) contain >security codes that stop them from being used with an OEM version >of VL from another supplier. The Full feature version of VL from VL >can handle any of the VL or OEM libraries. The other constraint (and >this is the one that will slow you down ) is the netlister. The OEM >versions come with only a netlister for the OEM libraries. So although >you could create your own library to run with (for example) the Xilinx >OEM version of VL, the symbols you create with that version of VL >will have the security codes that will only let it be netlisted to >XNF. > >There are ASIC conversion houses that will take XNF as input for an >ASIC. > >> >>I have only ever used *Xilinx* FPGAs, and their libraries. But most of >>the components in those libraries are trivial, like gates, counters, >>etc. It would take relatively little work to create a "universal" >>library which someone would sell to FPGA developers, and which would >>have all the Xilinx parts in it. >> > >This would only work if they had the full version of VL. > >>The problem with that is that you would need an *unrestricted* version >>of Workview, which costs a fortune. Or a version of Workview which >>accepts this "universal" library. We are back to the Viewlogic "magic >>numbers". >> > >right. > >>Maybe I am missing something. I thought that maybe the Xilinx P&R >>software accepts *only* netlists produced using Xilinx libraries, but >>I don't think that is true. I have done XNF files with CUPL -> PALASM >>-> PDS2XNF -> XNF. > >There are no security numbers in the XNF. Only in the VL libraries. >Anyone can create XNF (and many do), and the spec for it is available >to developers from Xilinx, as part of their alliance program. Many >people have written their own XNF manipulation software without this >spec, because XNF is human readable, and has little complexity to it. >As an example, Altera has XNF input capability in their MAX+II software >and I seriously doubt that Xilinx told them how to parse it. :-) > >>And even if Xilinx did this, it would be easy to >>produce a little program which fixes-up the magic number. Such a >>program has already been produced for Viewlogic schematics and >>libraries, some time ago. All you have to do is disassemble PDS2XNF, >>XNFOPT, or any of the other 3rd party programs which can produce XNF >>netlists (ABEL, CUPL), to see how these magic numbers are generated. > >See above: no magic numbers in XNF. Disassembling PDS2XNF, XNFOPT, >or other 3rd party netlist generator isnt going to help you. Plus >it is a violation of the software license. :-) > >> >>Alternatively, one could go Xilinx -> Orca by translating the final >>netlist. The Xilinx library part names (e.g. DFF etc) would be >>replaced with the Orca names. It easy to translate these netlists with >>a simple C program, or even an AWK script. > >You will need to know both netlist formats to do this, and AWK type >substitutions may not quite be enough. > >>Peter. > >Philip > >Article: 4095
Hi folks, Thanks everyone for your interest and feedback on my PhD thesis on a Xilinx XC6200 based image processing coprocessor. copy available at http://www.cs.qub.ac.uk/~P.Donachy/thesis/ If anyone has anymore queries or I have not replyed to anyone, let me know. Thanks again everyone!! Regards Paul Donachy ----------------------------------------------------------------- p.donachy@qub.ac.uk The Queen's University of BelfastArticle: 4096
In article <50vou8$abp@ss.netgate.net> mush@netgate.net "David Decker" writes: "DTHIBAUL <DTHIBAUL@mailgw.sanders.lockheed.com> wrote: " ">When I run Viewlogics Prosim under Windows 3.11 the program states ">that I have only about 1 Meg of memory available (which is not enough to ">load anything even moderately big). When I run any of the other Pro ">Series tools (i.e. Procapture or Prowave) they report I have 75Meg of ">memory available. MSD also says I have plenty of memory. Anyone ever ">seen this problem and have any hints??? " "I'm running ProSim as purchaced from Xilinx. I don't see a 1M message. "I just see a message stating that my memory is all used up and would I "like to save everything before quitting. ProSim then just bails out, "back to PROFlow. This happens after 16000 net name equivalencies have "been logged to the screen. " <snip> " "I'm very glad ProSeries is DEAD! I hope WVO is better. ??? " Are you sure that you don't have a size-limited version of PROSim? That might explain your problem, and AFAIK this was the case with the Xilinx version. Look near the top of your license.wv file for "MAX_GATES 999999". If instead of 999999 there's a lower number, then you have a restricted version. David PashleyArticle: 4097
can anyone direct me to a professional association in the Silicon valley pertaining to asic or fpga design. kevin kh@wired-world.com or coldiron@contractsvcs.comArticle: 4098
[ Editor's Note: Here's the results of that Cadence user survey I did.
Since I asked for your help on it on the newsgroups, I feel it's my
obligation to give the results back to the newsgroups. - John ]
!!! "It's not a BUG, jcooley@world.std.com
/o o\ / it's a FEATURE!" (508) 429-4357
( > )
\ - / "Cadence: the Good, the Bad, & the Ugly"
_] [_ (published in Integrated System Design in July 1996)
by John Cooley, EDA Consumer Advocate
Holliston Poor Farm, P.O. Box 6222, Holliston, MA 01746-6222
From a customer's point of view, the 1995 International Cadence Users group
(ICU) meeting in Boston (Oct. 1-5) was a positive thing to see. I was
surprised to find board designers happily mixing with IC designers and I've
never ever seen a SysAdmin track at any user conference before! ICU itself
has grown at a maturing rate; a total of 419 people from 90 companies
attended, up roughly 8% from the last time ICU met in Boston two years ago.
Under the diplomatic yet user driven Chairmanship of IC designer Peter Stokes
(founder of comp.cad.cadence) the past wars with Cadence for control of the
meeting and its agenda seems to have been resolved in favor of the customers.
The fact that competitors like Analogy, Simulation Tech., HLD Systems, Design
Acceleration, UniCAD and even fierce rivals like Synopsys, Cooper & Chyan,
and Meta-Soft appeared at their Vendor Fair backs this claim. Out of a 5 day
conference, the Cadence marketing presentations were kept contained in a
single 2 hour block. Additional evidence is in the official ICU proceedings
where only 7 out of the 47 papers were written by Cadence employees. The
biggest indicator was that ICU invited a known EDA rabble-rouser like myself
to give an *unrestricted* report card on Cadence as a keynote address!
Here's what I saw.
A long time ago I learned it was a complete waste of time trying to find
out the truth about an EDA company or its products from their sales/marketing
staff. Either they'd give me only the sunshine and happiness side of things
or completely whitewash over any real problems I *happened* to discover on my
own from *other* sources about their products and services. On the other
hand, the Internet is a lot like a New England town meeting; those who speak
up the most usually have some axe to grind, while those happy with the status
quo tend not to even show up. What follows are the results of a detailed
survey I did with 98 self-selecting Cadence users on the Internet. Although
by promising anonymity this is a great way to find where Cadence is messing
up, please keep in mind that by its very nature, such surveys don't usually
show a company's strengths. Because this is by no means an accurate,
scientific survey -- but more something that gives rough first pass
impressions, in most cases I'm rounding all reported percentages to the
nearest 5% or 10%.
On-Line Docs
------------
Most users seem quite displeased with past versions of Cadence's on-line
browser "OpenBook", because searching with it is a nightmare but they saw it
greatly improved with version 9502. Many described having to call the AE's
to find the bizarre keywords that would help them find what they were
looking for using OpenBook. One user said, "It was awful until 9502.
Finally some Dracula commands which have existed for the last 6 years are
actually documented." Also, in a weird sort of irony, mimicing the long
time Synopsys/Cadence rivalary, two users noted: "Cadence and Synopsys both
use Iview, but we still haven't been able to make them work together.
Basically we have to configure a window to run one or another at this time."
Overall 65% gave positive, 20% mixed, and 15% bad reviews of on-line docs.
HotLine
-------
Instead of the usual "We'll-connect-you-with-someone-who-can-help-you-NOW"
model, Cadence uses a "We'll-call-you-back-in-a-few-hours-with-someone-who-
knows-this-product" model. One who liked it said: "My call is returned
within 2 hr. Usually the person calling can address the issues. When they
can't they can find someone who can." Those who hated it typically said:
"Turnaround ranges from 2 days to 1 month. We even talked with Manny Correia
about the sucko support and he provided us with evidence that they are not
even close to meeting their target response times." A few users commented
that they preferred e-mailing "crc_cadence@cadence.com" over calling the
hotline. An average user comment was: "The initial and secondary callbacks
have always been prompt. But if it's not a straight-forward question that
can be answered by that second call you will be in a long struggle which
usually ends with 'that will be fixed in the next release.'" As expected,
big customers with hundreds of licences reported far better support than the
small customers who bought just a handful of licences. Overall 35% gave
negative, 30% positive, and 15% mixed reviews of the hotline. 20% said they
didn't use the hotline for various (usually non-positive) reasons.
Local Support
-------------
Customers who liked their local support *loved* their local support. About
30% had positive remarks like: "Yes, the guys in Minneapolis are great." or
"Local apps engineers are seasoned. I use them in preference to the
hotline." Comments typical of those who disliked their local support (also
30% of users) were: "The sales guys are around pretending to be support
people." or "Local support? Well we see them when we have a huge problem
and they want to apologize or they think we have money in the budget for new
tools, or if they want to sell consulting. Other than that, local support
doesn't exist."
The 20% who gave mixed reviews said stuff like: "Some AE's are great.
Others couldn't fix a hole in a paper bag with both hands full of Scotch
tape. There is no in-between." or "The local support comes and goes.
Recently it's been great because our AE is very pro-active about solving our
problems. However, it's likely to change; the turn-over at the local office
is tremendous. In the past we've had trouble with the support disappearing
after we've made the purchase." The remaining 20% reported they never used
local support or "I am my own local support."
SourceLink, WWW, & "comp.cad.cadence"
-------------------------------------
Although the Internet may be big news, 50% of the Cadence customers reported
that they hadn't seen neither SourceLink (the Cadence on-line bug database
with search engine) nor the sometimes maligned Cadence marketing WWW page
(which one user described as "one of the many homes of EDA marketing puffery
on the Web.") Of those who have seen SourceLink, *everyone* liked it in its
WWW form with: "SourceLink was difficult to use. WWW page is useful, better
than old SourceLink." and "Very useful. I've downloaded a lot of good info
from it." The newsgroup comp.cad.cadence gets mixed reviews with 60% liking
it and 40% disliking it. "The newsgroup is pretty random -- not useful for
short-term problem solving." and "comp.cad.cadence is helpful. I discovered
at least one bug with their hspice netlister and it was good to have a place
to discuss it." The two users who commented on TalkVerilog (which I didn't
explicitly ask about in my survey) liked it.
Cadence Spectrum Services
-------------------------
From day one I've been a very vocal opponent to the idea of letting any EDA
company take over your company's entire internal CAD and design functions as
Cadence has been pushing through its new Spectrum Services division. It was
refreshing to see 85% of users agree with my stance with 70% saying things
like: "Rectum Services is bad news for Cadence's customers. It causes a
basic conflict of interest between customers and Cadence. There is no
motivation for Cadence to provide good support for customers on maintenance."
and "I do not approve. I don't believe it helps your company keep the edge."
(The phrase "conflict of interest" came up a lot.) The other 15% took the
financial view saying "Too expensive." and "It is REALLY overpriced!!!"
Personal bias aside, I must report another 15% argued "Given the complexity
and instability of their tools, they almost have to provide such a service."
and "It always takes more effort than anticipated when using a new tool for
the first time, and having extra people who have used the tool before would
be a good thing." (I can't help but rebut: "Isn't this called 'training?'")
Cadence Training
----------------
Of those who sat through Cadence training videos, there was almost 100%
agreement they were mostly too long, out-of-date and too simple. "We do have
all the video classes. By far and away, the best class is the one covering
SKILL. Probably could have thrown the rest away after that one, especially
with the incredibly redundant X and UNIX training. Alas, as far as I can
tell, the video courses have not been updated for several years."
Concerning direct training, those taking Verilog, SKILL, Cell3, and Artist
mostly (40%) liked them if they were completely new to the topic. Add VHDL,
Allegro, Synergy, or Verilog for synthesis and you get another 25% of users
saying instruction varies wildly depending on the instructor and the
remaining 35% voicing dissatisfaction. One anecdotal horror story was: "We
sent someone to the East Coast at a sizable expense for an official training
class. When he got there, Cadence parked him in a room by himself with a
videotape. What a waste." One repeated happy comment was about an
instructor who liked to bake chocolate chip cookies for her class.
Cadence Sales
-------------
This being my first comprehensive customer survey, I was surprised to see how
many users ranked Cadence sales in either a neutral or a postive light. I
just did not expect this after hearing years of notoriously mercenary stories
about sales people from all sorts of EDA companies! Yes, I got quotes from
users like: "So many of Cadence products seem to be 'press release ware'.
We've paid for things that didn't exist. Our maintenance costs are sky-high.
They can't figure out what licences we have. Our contract expired and they
treated us like dirt. They never call anymore -- we only call them if
there's an emergency." or "They'll help, but only while you have a budget."
I even laughed when I read: "The old sales guy in my area used to sell used
cars to Dick Nixon." and "If my daughter married a Cadence salesman I'd
disown her and have him killed by the Mafia." (Cadence ranking bellow.)
Customer Ranking Of The Cadence Sales Force
-------------------------------------------
Percent User
Response Choices Offered Users
------------ --------------------------------------------------
0% - "Ghandi has serious competition compared to
my Cadence salesman!" (or)
0% - "I want to base my whole life philosophy
around you." friends (or)
0% - "Please!, Marry my daughter!" good friends (or)
7% xxx - Helpful friends (or)
15% xxxxxxx - Helpful business acqaintances (or)
16% xxxxxxx - Helpful Department store cashiers (or)
13% xxxxxx - Indifferent Department store cashiers (or)
11% xxxxx - New Car salesmen (or)
5% xxx - Door-to-Door vacuum cleaner salesmen (or)
22% xxxxxxxxxx - Used Car salesmen (or)
9% xxxx - Con artists just a few steps ahead of the law (or)
2% x - Congressmen and/or convicted con-artists
fig.1) Customer response when asked: "Going from GREAT to HORRIBLE
please rank the Cadence sales force equal to (choose one)."
Then, mixed in with these predictable user views I found unexpected stories
like: "I usually get a call when my salesman needs to make a sale. On the
other hand, my salesman did help me through a tough problem recently."
Another user related a story where a Cadence salesman actually directed him
to not use a specific Cadence product, because its EDIF in wasn't so hot
and instead recommended a third party tool/service! Whoa!
There was even a bit of sympathy expressed on some user's part with: "I never
got the feeling that our salesdroids were trying to intentionally con us.
They just never seemed to understand our requirements or their own products."
and "They mean well, but aren't very technical. Aren't always aware of all
products offered, or what they do.", "Our salesman will return phone
calls, which is more than I can say about our current Mentor salesman."
and "We don't expect much from sales people, so we are usually not too
disappointed in them."
"Joe-Costello-For-A-Day"
------------------------
To get more open responses I asked users what their most postive and most
negative experiences had been with Cadence and what would they do if they
were "Joe-Costello-For-A-Day." On the postive side *lots* of users were
very excited about Verilog-XL and how bug-free it is. A lot of people
also greatly loved SKILL. Other things users said were: "The folks their
treat me like a first class customer though I know I'm a second class
opportunity for them." "In a 3 year time frame, we pushed over 100 designs
through our system here with very few pitfalls." "Their software usually
works and is a standard." "Their basic core technologies (schematic capture,
place & route, verification) are pretty good." "SourceLink is excellent.
Even better than [Synopsys's] SolvIt-On-The-Web." "Our salesman and all but
one of our AE's did a good job on interactive IC verification (DIVA inside
Virtuoso) -- which is they ONLY reason we picked Cadence over Mentor." "I
called once with a problem in Dracula and got a solution and a patch before
I got off the phone. I'd give that AE whatever it took to keep her!" "Their
installation software works 98%, even across multiple platforms and AFS,
minus one or two little things which are fairly easy to work around." "They
gave us our money back (credits) when something we bought didn't pan out."
"LeapFrog is great!"
Of course there were a few jokers with: "If I were Joe-for-a-day I'd pay off
the house and buy a sports car." and "Personally, the day we bought ViewDraw
[a ViewLogic product] was the best Cadence experience I have had." (More
than a few people complimented Cadence's cafeteria, also!)
On the negative side, users complained about the painful Cadence/Valid
merger, the fact that the Opus database constantly changes and is not in
an ASCII format, and the need to "FIX ALL THE DAMN LITTLE BUGS THAT HAVE
EXISTED FOREVER!!!" As "Joe-For-A-Day" they would: "Nuke Vampire." "I
would ensure all sales were contingent on customer success." "Doc's need
to be more in sync with their software." "I would stop shipping 'release'
quality software which is really alpha test quality." "I'd commit more to
keeping their current customers happy rather than chasing the next sale."
"I'd dump this dead end obsession with Spectrum Consulting to focus on
developing new tools." "LeapFrog sucks!" "cwaves sux" "I would take steps
to push towards truly integrated toolsets that work with Cadence and non-
Cadence tools."
One consultant wrote: "Sales and Marketing people at Cadence threatened
me that if I didn't do what they wanted they'd tell my customer to go to
my competitor." A few ex-Cadence employees reported being badmouthed by
Cadence at their current jobs/contracts.
Best & Worst Tools
------------------
About 45% of users said something extremely positive about Verilog, followed
by another 15% ranted about SKILL. The remaining 40% was roughly equally
divided amongst: Composer, Leapfrog, Virtuoso, Edge, Cell3, CellEnsemble,
Artist, Spectre, Allegro, Library Browser, gr_waves, and Concept. One user
each cited Verilog's debug environment and Synergy's informative error
messages as the best. "SKILL makes me almost able to forgive some errors.
At least if something is broken, I can fix it, unlike with Compass."
The "worst" category was closely grouped around ten products. About 20%
each were bad remarks concerning Composer and Dracula. Another 15% each was
to "anything with a GUI", Cwaves, Synergy, and Opus. The remaining handful
of complaints were about cdsSpice, OpenBook, and the VHDL netlister. "The
worst is Dracula. Features appear in one release and disappear in the next.
It is poorly documented and very user-hostile."
Overall Rating
--------------
About 15% of users ranked Cadence above average. "They seem to have an
almost bug free product with Verilog. Better than I can say about the other
guys." The bulk (55%) saw Cadence as average "much like Hertz rent-a-car,
AT&T phone service, etc." or "I've dealt with companies that had better
support, but less useful tools." The remaining 30% of users condemned
Cadence as below average with: "The only supplier's name to have become a
swear word in our company is 'Cadence.'" and "Definitely worst. I told a
friend of mine who is a Cadence Apps guys that I would rather deal with
the IRS."
Having experience with a lot of EDA companies and what their users think
about them, I'd say Cadence was doing fairly well to average. They rubbed
their customers the wrong way with Spectrum services, the Cadence/Valid
merger, Opus, OpenBook, training videos, and variable service but get major
brownie points for Verilog's incredible robustness, SourceLink on the Web,
SKILL, their user-driven user group, good installs and documentation.
Overall, I'd say Cadence has improved over the last few years from the
customer's viewpoint but suffers from the same big company problems that
its competitors Synopsys, Mentor and ViewLogic continually grapple with.
- John Cooley
part-time EDA Consumer Advocate
P.S. As usual, I'll put together a digest of the letters I get back from
readers on this. Since I don't have the copious free time to chase
down permissions, my default setting is that *anything* I receive via
e-mail is for possible publication unless *clearly* marked otherwise.
You also have the alternative to be "anonymous" -- but you must
*clearly* request this in your letter. (Also, PLEASE DON'T cc this
entire article back to me, OK? At 20 kbytes each, it's a lot of disk!)
--------
Article: 4099In article <50pdgl$tf9@camel0.mindspring.com>, ttooley@atl.mindspring.com wrote: > I have done several designs with Xilinx FPGAs... I am tired of NRE > charges and quantity requirements needed to go to hardwire. > > I am considering alternative vendors like Cypress, Altera, Atmel and > Actel. > I do not understand the logic in this question: There are NO NRE charges whatsoever for Xilinx, Cypress, Altera, Atmel, or Actel programmable parts. You don't have to switch from one vendor to the other to avoid NRE. You just compare device prices, performance and availability, and you do the same for the software, and you make an intelligent choice. If you want to reduce the purchase price per Xilinx device by roughly 50%, Xilinx offers the HardWire option, which has an NRE charge, since it involves dedicated masks. This option, therefore only makes sense above a certain volume. It is easy to calculate the break-even point. But the availability of the lower-cost HardWire option cannot possibly be construed as a reason to abandon Xilinx FPGAs. I may be a little biased, but still... :-) Peter Alfke, Xilinx Applications
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z