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I'm having a bunch of trouble guessing the syntax of the new Xilinx M1 (NEOCAD) .UCF file. Anybody have a good example file? I'll post some of my findings once I've solved my problem... which is... I want to put a specific flop in a CLB and prevent the PLace and Route software from placing any other flops in that CLB. I'm using a synthesis flow using exemplar so it easiest to put placement stuff in a User Configuration File (UCF). I can get my flop into the desired location with: INST "*FLOP_NAME*" LOC = CLB_R12C12 ; and I want to do something along the lines of: CONFIG PROHIBIT CLB_R12C12.ffx ; but the M1.1.1a tools barf on the syntax (even though the documentation says it works...) All I eally need is an example file THAT HAS BEEN RUN THRU THE TOOLS! -- Eric Ryherd eric@vautomation.com VAutomation Inc. Synthesizable VHDL and Verilog Cores 20 Trafalgar Sq. #443 http://www.vautomation.com Nashua NH 03063 (603) 882-2282 FAX:882-1587Article: 6276
In my latest Xlininx design, I used X-BLOX libraries and have been really impressed by how much time it has saved, relative to my previous FPGA schematic capture for Xilinx and Actel. It also dramatically improves schematic readability and flexibility. So now, with the new M1 Xilinx development system, I understand X-BLOX is being dropped! Anyone know why? Anyone else think X-BLOX is a good thing? Robert.Article: 6277
......Test .Article: 6278
In <5kpvsh$i20@hearye.mlb.semi.harris.com>, jws@billy.mlb.semi.harris.com (James W. Swonger) writes: >>Does anybody know what are the advantages/disadvantages for chips that >>were designed for target process CMOS or BiCMOS. [...] Additional BiCMOS advantage (*the* advantage) : BiCMOS digital outputs, whether internal or external, are faster compared to regular CMOS outputs because a MOSFET channel limits the available current for charging/discharging the (parasitic) capacity connected to the output by the load. A bipolar/MOS combined stage can handle such peak currents faster than a pure MOS stage. Greetings Oliver ------------------------------------------------------ Oliver Bartels + Erding, Germany + obartels@bartels.de http://www.bartels.de + Phone: +49-8122-9729-0 Fax:-10 ------------------------------------------------------Article: 6279
I mistakenly connected quicklogic input only pins to outputs on there pASIC 2 devices, does any one know away around this without board rework. ThanksArticle: 6280
Eric, You are not going to like my answer but I want you to know that this has been brought up to the development team. In the future you will be able to isolate a flip flop but right now you can't do it. (I am a FAE with Xilinx and this has been discussed as a needed feature. It was taken as an action item to include in a future release. Other people have requested this.) Let me explain how the M1 software works. The map program decides what logic is put together into a CLB. PAR then decides where to put that entire CLB. PROHIBIT is a PAR command and since PAR only understands entire CLBs it doesn't know what to do with a single FF location. It might have died because it was told to put something into a prohibited location. (I noticed that the documentation says that .ffx is supported as a location. I will look into this.) MAP does not read the PROHIBIT statements since it doesn't do anything with placement only mapping logic. In the future, there will be a way to isolate a single flip-flop into a CLB. The only work around (I already know that this isn't a good solution so don't yell to loudly !) is to put another flip flop that can be tolerated into that CLB using another LOC command. Another possible solution is to create a dummy flip-flop in your design and put that flip-flop in the same CLB. Or duplicate the existing flip-flop so it won't take anymore routing resouces. I personally wish the tools would support this since it would help me out also. Let me know if you have any questions, Kate Meilicke XILINX FAEArticle: 6281
On Wed, 07 May 1997 22:17:19 -0400, Eric Ryherd <eric@vautomation.com> wrote: >I'm having a bunch of trouble guessing the syntax of the >new Xilinx M1 (NEOCAD) .UCF file. Anybody have a good example >file? I'll post some of my findings once I've solved my problem... > >which is... > >I want to put a specific flop in a CLB and prevent the PLace and >Route software from placing any other flops in that CLB. >[snip] >and I want to do something along the lines of: >CONFIG PROHIBIT CLB_R12C12.ffx ; > I remember this used to be really easy for the old XACT tools (though I don't remember off hand the syntax.) >but the M1.1.1a tools barf on the syntax (even though the documentation >says it works...) All I eally need is an example file THAT HAS BEEN >RUN THRU THE TOOLS! I've been finding similar challenges for timespecs. The documentation says one thing, but I can't quite get it to work. (Config par, for example.) I've been able to work around my problems so far, but I'm looking forward to their forthcoming release (which I was told should be on its way, but I haven't seen it yet.) > >-- >Eric Ryherd eric@vautomation.com >VAutomation Inc. Synthesizable VHDL and Verilog Cores >20 Trafalgar Sq. #443 http://www.vautomation.com >Nashua NH 03063 (603) 882-2282 FAX:882-1587 Jason T. Wright EricssonArticle: 6282
Jan Gray wrote: > This week we had some great news, which I'm surprised no one else has > commented on. Xilinx and Prentice Hall have announced they will offer an > inexpensive student edition of Xilinx tools. (Your email address seems > academic.) See http://www.xilinx.com/prs_rls/univers.htm This is outstanding. It will finally make FPGAs accessible to the individual hobbyist as well, which will plant lots of seeds for the future. Kudos to Xilinx! --MikeArticle: 6283
The June issue of Scientific American has, as its cover article, a fine introductory piece on Configurable Computing, that is, FPGA-based computing engines, written by Profs. Villasenor and Mangione-Smith of UCLA. Very nicely done, with good basic explanations and examples, and their usual outstanding graphics. You can see the article now at their web site: http://www.sciam.com . --MikeArticle: 6284
Robert Trent wrote: > > In my latest Xlininx design, I used X-BLOX libraries and have been > really impressed by how much time it has saved, relative to my previous > FPGA schematic capture for Xilinx and Actel. It also dramatically > improves schematic readability and flexibility. > > So now, with the new M1 Xilinx development system, I understand X-BLOX > is being dropped! Anyone know why? Anyone else think X-BLOX is a good > thing? > > Robert. X-Blox is being replaced with something called Logi-blox - I beleive. I've only played with these a little by they appear to have everything X-Blox does, and seem a little more configurable. I've found X-Blox can ease schematic entry but they are very slow when you build. I haven't any practical experiance with Logiblox yet. One nice thing that was removed with Logiblox is you don't need the BUS_IF components very time you want to transition from a standard net to x_blox. Dave T. - speaking for myself.Article: 6285
---------------------------------------------------------------------- This message is being brought to you by Dynamic Mail - the easier and faster's way to explodes your business on the internet. For more information please visit our web site at : http://www.australia.net.au/~apexpi/dynamail.htm ---------------------------------------------------------------------- Hello I am starting up a company in the Netherlands. We are distributor for many products in Europe and outside. We are looking for companies who want to become reseller of some of our products in there country. We have products for every branche in our assortiment. Just mail me and we can discuss this further. We are also looking for programmers since we are developing software ourselves, If you can program good please contact me and we can discuss this. Sincerely Ruben DanielsArticle: 6286
The final program and registration information for IWLS 97 (International Workshop on Logic Synthesis) is available at: http://www.ee.princeton.edu/iwls97.html -- Sharad Malik sharad@ee.princeton.edu Associate Professor 609-258-4625 Dept. of Electrical Engineering 609-258-3745 Fax Princeton University http://www.ee.princeton.edu/~sharadArticle: 6287
I need address/phone/fax list of all semiconductor companines Thank you bharat@antrix.com Bharat.Kurani@add.ssw.abbott.comArticle: 6288
On Mon, 05 May 1997 19:35:33 -0500, Ed Barrett
<ed.barrett@postoffice.worldnet.att.net> wrote:
>Scott Thomas wrote:
>>
>> On Fri, 02 May 1997 12:20:21 -0700, Ed Barrett
>> <ed.barrett@worldnet.att.net> wrote:
>>
>> >
>> >As for speed, the 2032 offers a true 5.0 nsec tpd and 180 Mhz operation.
>> >Also, for CPLD architectures tpd is fixed. The Lattice 5.0 nsec is a
>> >fixed guaranteed worst case delay.
>>
>> Isn't this 5.0 nsec speed only for dedicated inputs (two on the 2032)
>> and no more than 4 product terms? Doesn't the timing change if I/O
>> pins are used as inputs, more prouct terms are used, if routing pools
>> are used? These may be fixed, guaranteed worst case delays, but don't
>> these cause the tPD to exceed 5.0 nsec?
>>
>> The point Steve was making is the equivalent Vantis device
>> (MACH111SP-5) doens't exceed 5.0 nsec.--i.e., Vantis' worst case is
>> Lattice's best case.
>>
>> Scott Thomas
>> Vantis
>
>
>Wrong again. The 5.0 nsec tpd iScott Thomas wrote:
>>
>> On Fri, 02 May 1997 12:20:21 -0700, Ed Barrett
>> <ed.barrett@worldnet.att.net> wrote:
>>
>> >
>> >As for speed, the 2032 offers a true 5.0 nsec tpd and 180 Mhz operation.
>> >Also, for CPLD architectures tpd is fixed. The Lattice 5.0 nsec is a
>> >fixed guaranteed worst case delay.
>>
>> Isn't this 5.0 nsec speed only for dedicated inputs (two on the 2032)
>> and no more than 4 product terms? Doesn't the timing change if I/O
>> pins are used as inputs, more prouct terms are used, if routing pools
>> are used? These may be fixed, guaranteed worst case delays, but don't
>> these cause the tPD to exceed 5.0 nsec?
>>
>> The point Steve was making is the equivalent Vantis device
>> (MACH111SP-5) doens't exceed 5.0 nsec.--i.e., Vantis' worst case is
>> Lattice's best case.
>>
>> Scott Thomas
>> Vantis
>
>--
>Wrong again. The 5.0 nsec tpd is any I/O pin to any other I/O pin just
>like you would expect. No magic No hidden delay.
>
>Ed
Lattice's datasheet explicitly states *two* tPD's--tPD1 and tPD2. They
are derived as follows.
2032 Timing Model*
Best case combinatorial delay, fast slew rate.
tPD1 = 5.0 ns which is derived from:
= tDIN (parameter 21, Dedicated Input Delay)
+ t4PTBPC (parameter 23, 4 Product Term Bypass Path Delay)
+ tORPBP (parameter 37, ORP Bypass Delay)
+ tOB (parameter 38, Output Buffer Delay)
Worst case combinatorial delay, fast slew rate.
tPD2 = tIO (parameter 20, Input Buffer Delay)
+ tGRP (parameter 22, GRP delay)
+ t20PTXOR (parameter 26, 20 Product Term/XOR Path Delay)
+ tGBP (parameter 28, GLB Register Bypass Delay)
+ tORP (parameter 36, ORP Delay)
+ tOB (parameter 38, Output Buffer Delay)
tPD2 = 0.6 + 0.7 + 4.1 + 0.2 + 0.7 + 1.2 = 7.5 ns
* Timing Model, parameters, and values obtained from the March 1997
ispLSI and pLSI 2032 datasheet, pages 5, 7, and 9.
According to Lattice's timing model, delay does change with I/O,
product terms and routing.
It seems as if Lattice's datasheet doesn't agree with your statement.
Scott
Article: 6289>>>>> Peixin Zhong <pzhong@ee.princeton.edu> writes: > Hi, I have just bought a Viewlogic Workview offic v 7.31. I want > to intall it on a Pentium Pro with Windows NT 4.0. However, I > could not get the hardware key correctly. You simply have to install the Sentinel driver (it's in a subdirectory of its own on the WV 7.31 CD) as a new Multimedia Driver. It's straightforward, but if you can't figure it out right away, Viewlogic has an installation help file (complete with screen captures) on their web site. -- Roger Williams finger me for my PGP public key Coelacanth Engineering consulting & turnkey product development Norwell, MA wireless * DSP-based instrumentation * ATE tel +1 617 871-9007 * fax +1 617 871-8363 * http://www.coelacanth.com/Article: 6290
I don't think anybody has a list of ALL semiconductor companies. Try http://www2.arnes.si/~uljfer3/elect/index.html for the beginning. Bharat Kurani <Bharat.Kurani@add.ssw.abbott.com> wrote in article <33725686.3C80@add.ssw.abbott.com>... > I need address/phone/fax list of all semiconductor companines > > Thank you > > bharat@antrix.com > Bharat.Kurani@add.ssw.abbott.com >Article: 6291
LogicWorks, in South Africa, is a VHDL modelling, FPGA and Digital systems development house with 20 years experience in high speed digital design including Actel and Quicklogic FPGA's. The outsource market in South Africa is small and we would like to expand our client base internationally. The Internet is making international co-development viable as specifications, simulation data , signoff etc can readily be communicated. We use Viewlogic's Workview Office tool suite. Please contact Anthony at aelogic@iafrica.com if you have a need for such a service.Article: 6292
On Thu, 08 May 1997 09:39:49 -0500, Mike Horwath <mhorwath@merge.com>
wrote:
>I mistakenly connected quicklogic input only pins to outputs on there
>pASIC 2 devices, does any one know away around this without board
>rework.
>
From your message, I assume that what you need to do is force the
outputs in question to be tri-stated, avoiding conflict with the
signals which are connected to the inputs. Here's how to do it in
Verilog:
Put this line at the top level of your source files. You will need a
line for each pin to be fixed. In my case the pin name is
LADDR_SP_A23.
// Four un-necessary address lines are routed to the parts. Force the
pins
// to be tri-stated.
qltripad spareA23 (.A(gnd), .EN(gnd), .P(LADDR_SP_A23));
Create qltripad.v as follows:
/* Verilog Model Created from SCS Schematic ql2007.sch
Feb 06, 1996 09:50 */
/* Automatically generated by hvveri version 5.1 */
`timescale 1ns/1ns
`define LOGIC 1
`define BIDIR 2
`define INCELL 3
`define CLOCK 4
module qltripad( A, EN, P );
input A, EN;
output P;
parameter ql_gate = `BIDIR;
supply1 VCC;
bicell QL1 ( .I1(VCC), .I2(A), .IE(EN), .IP(P) );
endmodule // qltripad
module bicell( I1, I2, IE, IP, IZ );
input I1, I2, IE;
inout IP;
output IZ;
parameter ql_frag = 1;
assign #1 IP = IE ? (~I1 | I2):1'bz;
assign #1 IZ = IP;
endmodule // bicell
If you're in the dark ages, still drawing schematics, simply drop down
a tri-stateable output cell and ground the EN pin.
If you need further assistance, give their support line a call at
408-990-4100.
Garnett
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Eml: ghamilton@chrysalis-its.com
Article: 6293I want to insert a PCMCIA in an Altera FLEX10K. Anybody has had a positive experience about that and could show me any valid partners that could supply me the core in vhdl description? Thank you. Ivan Rossi, Mantova Italy rossivan@tecna.itArticle: 6294
I just got a pre release of the new M1 router. It looks great. I especially like the macro editor which automatically generates VHDL code. The APS-X84 foundation kits will include all XILINX upgrades for one year which will include the M1. This means you can get a full up VHDL, schematic capture, router, Xchecker cables, FPGA ISA test board, XACT router, and the upgrades to M1 for as little as $650.00 !!! (no VHDL) or $1200.00 with VHDL. This is a great route (forgive the pun) to getting these great XILINX tools plus the FPGA test boards and VHDL examples. And remember, that the router software and FPGA board will work with other synthesizer front ends like Verilog, or ORCAD. If you already have an existing synthesizer front end, you should check out these kits which will work with your existing tools. The APS X84 kits can be seen at: http://www.erols.com/aaps -- _____________________________________________________ Richard Schwarz, President Associated Professional Systems Inc. (APS) 3003 Latrobe Court Abingdon, Maryland 21009 USA email: aaps@erols.com web site: http://www.erols.com/aaps Phone: 410-515-3883 or 410-290-3918 Fax: 410-661-2760 or 410-290-8146Article: 6295
Unfortunatly, in the Pre-Release software, there are several things that don't work in the UCF file but they do work in the PCF file. Configuring PAR is one of the things that I think works if inputted directly into the PCF file. M1.2 is shipping this week so you should see it soon. Some people received it today. KateArticle: 6296
Hi! LogiBLOX is the replacement for XBLOX. Most everything that can be done in XBLOX, can be done in LogiBLOX. The exception is BUSDEF component. You now have to explicitly define the width of your busses. The advantage of that is faster runtime for compiling. LogiBLOX also supports memory which XBLOX didn't. Kate Xilinx FAEArticle: 6297
Hi, we'll get right to the point. We operate one of the finest quality custom color labs in the USA. To introduce you to our service we're offering the following Internet enlargement special: Your color negatives hand printed on Kodak Supra Professional 16x20 inch paper. All negatives printed full frame. Exhibition quality and color corrected---send us any size color negative (35mm up to 4x5 inches). * * * * * * * * * * 16 x 20 inch color enlargement special 5 identical prints from same negative-------$79 10 identical prints from same negative------$129 * * * * * * * * * * Most orders 1 to 2 days in the lab. Add $6 priority mail shipping; international add $10. We accept Visa and Mastercharge. Mail your negative(s) and payment to: TSP CUSTOM LAB P.O. Box 248 Lake Village, IN 46349 USA phone 219-992-2413 fax 219-992-2644 visit our website http://www.centralcontrolsystems.com/saylordesign/photo/prolab.htmArticle: 6298
I'm playing about with the ETH, Zurich, Trianus software for XC6216 development under Win95. If anyone else is using it, could they get in touch with me. Two (or more) heads are better than one! I'm putting together an ISA card for the 6216. Leon -- Leon Heller Amateur radio callsign: G1HSM Email: leon@lfheller.demon.co.uk http://www.lfheller.demon.co.uk Tel: +44 (0) 118 947 1424 (home) +44 (0) 1344 385556 (work)Article: 6299
Hi all! We are frantically trying to design a microcontroller in a
masochistic attempt to expose ourselves to HDL's and FPGA's. This is
our design project for a junior level class in Digital Electronics, NOT
computer architecture... so don't scream at us for having less than
optimal design... :)
We put a little ASCII drawing of the particular problem we have. This
question is specifically geared towards the HDL called PLDasm and the
EPX780 FPGA. However, this question may apply to all HDLs.
______
|\ | |
INPUT ----| >----*--------|D Q|------------
|/ | | A |
| | |______|
| |
| |
\control | control
| |
| ______ |
| | | |\
| |D Q|-----| >----|
| | B | |/ |
| |______| |
| |
|______________________________|
We want to connect two signals to the input of register A. The signals
are tristated to prevent contesting. The two statements we used to
connect the registers are:
A := INPUT.io
A := B.io
with tristating equations:
B.trst = control
A.trst = \control
The .io extension refers to feedback taken after the tristate buffer.
The error that this produces is "Multiple definitions for A". We can
circumvent this using a combinational equation instead of tristate:
A := INPUT * \control + B * control
This, however, requires additional resources (nodes/pins) from the
FPGA. We need to be able to do this using tristate multiplexing to save
as many resources as possible.
We would appreciate any advice you might have for us. Thank you.
Kristopher Miller millerkl@bucknell.edu
Bucknell University
Lewisburg, PA 17837-2082
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