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On Thu, 12 Feb 1998 10:58:13 -0800, Gary Levin <gary_levin@phx.mcd.mot.com> wrote: >Thanks. That is good advice. And it was free :-) <snip> >The problem with PLD and FPGA design is that many devices seem to >require vendor dependent tools. All require their own P&R /Fitter, but all can be designed with one design flow. Namely HDL. Sitting on my PC is a copy of Exemplar's Galileo. Support is there for : Actel ACT1, ACT2, ACT3, 1200XL, 3200DX, Altera MAX5000/7000/9000, FLEX 6K, 8K, and 10K Atmel 6K02, 6K04 Lattice pLSI Lucent 3000, 1C, 2C, 2A Motorola MPA1000 Quicklogic pASIC1, pASIC2 Xilinx 3K, 4K, 5K, 7200A, 7300, 9500 Should be enough for most :-) So the issue is really back end fitters. To be honest, I don't know anybody who charges for their back end tool if you engage with them sensibly. e.g. "Hello Mr. Vendor, I'd like to use 10,000 of your devices. I have a netlist generated by my synthesis tools, and I really don't fancy forking out money to see whether your silicon is up to the job, and cost effective"..... >Personally, I prefer to use Verilog because we design our ASICs here >with Verilog. I just did a bunch of Lattice 2064's and 1016's using >Verilog and Synopsys. That worked out fine. But using Verilog for FPGA >Verilog doesn't always give the best results. Although Verilog is easier >to maintain here. I prefer VHDL, but I guess it's a case of what you learn with first. >For critical designs, for example, one group of designers use Viewlogic >for Xilinx. Another group prefers Altera parts. Our factory likes >Lattice because of ISP and manufacturing issues. Still yet, some older >engineers like ABEL for smaller PLD's. This comes from the history of different vendors OEM'ing different third party packages and hence locking designers into a particular mindset for design. >Our boards are designed using Mentor Graphics DA-LMS. We have older >designs still in Cadence. So as you see, the tools can get out of >control. > >What I'd like to know, before I start a new design and get locked into a >particular vendor is some competitive pricing for a particular class of >device. Unless of course they are mostly cost competitive and it really >doesn't matter to compare. They are all competitive when it comes down to it. Some will appear cheaper than others on a pure gate counting basis, but the wide range of real system performance, features and (worst of all) differing speed grades, makes comparisons a minefield. But... Just for fun, I pulled the following data for SRAM based, nominally 10K gate part, 208 pin QFP where possible. Parts are listed in ascending cost-per-gate. Device 100 up Claimed 4ip Registers Cost Percentage cost Density LUTs per K Increase gates EPF10K20RC2084 $42.50 15000 1152 1341 2.83 0.00% EPF6016QC2083 $22.95 8000 1320 1320 2.87 1.25% OR2T10A2S208 $35.70 12300 1024 1024 2.90 2.44% EPF10K10QC2084 $22.00 7000 576 710 3.14 10.92% OR2C10A2S208 $45.30 12300 1024 1024 3.68 29.99% EPF6016QC2082 $32.50 8000 1320 1320 4.06 43.38% OR2T10A4S208 $51.30 12300 1024 1024 4.17 47.20% EPF10K20RC2083 $63.50 15000 1152 1341 4.23 49.41% EPF10K10QC2083 $32.50 7000 576 710 4.64 63.87% XC4010XL-3PQ208C $49.10 10000 800 1120 4.91 73.29% XC5210-6PQ208C $49.80 10000 1296 1296 4.98 75.76% OR2C10A4S208 $65.20 12300 1024 1024 5.30 87.09% OR2T10A5S208 $66.80 12300 1024 1024 5.43 91.68% XC5210-3PQ160C $81.30 10000 1296 1296 8.13 186.94% XC4010E-4PQ208C $85.70 10000 800 1120 8.57 202.47% XC4010XL-1PQ208C $86.15 10000 800 1120 8.62 204.06% XC4010E-1PQ208C $211.00 10000 800 1120 21.10 644.71% Allowing for marketing "variations" and usability/routability issues, it would appear that Altera and Lucent have a similar position on a cost per gate basis, but only if you can accept a 3.3V device from Lucent. The figure for the 6K part may be a little low, but I have yet to see some real performance/routability information for that family. Xilinx would appear to be well out of the frame on the cost metric, with the "low cost" 5200 series not being so low cost after all. The real glarer is the 4010E-1. Must be some real aggressive bin selection going on here! Read into the numbers what you will. As Altera and Xilinx of these companies have net margins bumping around the 60%+ mark, there is a LOT of room for movement here. Stuart -- For Email remove "die.spammer." from the addressArticle: 9026
On Thu, 12 Feb 1998 19:42:44 -0500, Isabelle Gonthier <igonthie@total.net> wrote: > Look at Xilinx. They are most agressive in that type of quantity. >What density are you looking at? And their market share has been doing what exactly? All vendors will be aggressive where appropriate, but as many have differing features, you will typically find that a certain design gravitates towards one architecture or another. eg for SRAM FPGA's Need low cost, slow, power not an issue, medium density ? Try Xilinx or Altera and start the price war. Need big, slow and cheap, power not an issue? Try Altera. Need very big, fast, with DPRAM at reasonable speed? Try Xilinx Need faster than the rest with bags of features, but not excessive density (at the moment)? Try Lucent. At the low end of the performance and features market where there is a war going on for who can grab the biggest chunk of the (currently holy grail) gate array market, then you can probably start a price war with the two big players. Stuart -- For Email remove "die.spammer." from the addressArticle: 9027
First:, sorry for my redundant post 2/13. Sometimes FreeAgent has
trouble posting an article. It then squirels it away and for ever
more, when ever I close FreeAgent, it tells me I have stuff to post
and asks if I want to post now. I always try to click no, but
eventually I use it when I'm too tired, and accidentally click yes.
Does any one know how to kill pending posts in FreeAgent?
Second: It's a good thing I check DejaNews, because neither rk's
post nor Stuart's post ever made it to my .jps news server. I'm
therefore posting a follow-up to my own message via .jps.
Third: I have one point each for both rk, and Stuart Club:
rk says:
rk:
it's easy enough to break out the terms and simply tell the compiler
to add them up; i.e., x + 8x. i just finished an fir filter done
that way and the.
dd:
Did you check, rk, whether this produced a 9bit or a 12 bit adder?
My experience was that those tools that did synthesize an adder,
use a 12 bit adder, when only a 9 bit adder is required. Could be your
FIR could have been smaller.
stuart wrote:
RESULT <= ext((a & "000"),12) + ext(a,12) ;
Works just fine through Galileo Xtreme. Single 8 bit adder with the
carry out being used.
dd:
I believe a 9 bit adder is really required, and that the carry out
can not be used in this way, for 2's compliment DSP signals.
decimal 8bit/carry sign extension
0 00000000 000000000
+(-1) 11111111 111111111
= -1 011111111 111111111
As you can see, if you you use the carry out, and add an 8 bit -1
to and 8 bit zero you get an answer of +255.
If you use a 9 bit adder with sign extension, you correctly get -1.
Cheers,
Dave Decker
Please use only one 'h' in mush. I'm trying to reduce the spam.
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caught with ourselves in the net of life and time,
fellow prisoners of the splendor and travail of
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Article: 9028Hi: I used altera EPF81500-240AQC2 designing a board. There is a counter in the fpga, but why I mesure the counter's output, I found that if I mesuare another signal, then the counter's output is right, when I take down the probe on another signal, the counter's lowest bit lost some pulse. who meet the same problem. I need help!! yours. ws.Article: 9029
s_clubb@die.spammer.netcomuk.co.uk (Stuart Clubb) writes: > So the issue is really back end fitters. To be honest, I don't know > anybody who charges for their back end tool if you engage with them > sensibly. > > e.g. "Hello Mr. Vendor, I'd like to use 10,000 of your devices. I have > a netlist generated by my synthesis tools, and I really don't fancy > forking out money to see whether your silicon is up to the job, and > cost effective"..... "Well Mr. Customer, $500 doesn's seem too much for a very good P&R tool, does it ? It routes all of our smaller chips. After all, you've forked out twenty grand for your synthesis, this is just peanuts. Excuse me ? You use unix ?! Well, then, the situation is a little bit different, you must be rich, so $1000 is the price, plus 20% for the compulsory one year maintenance. Which chip ? Well, not that one, that's a high end chip. That will be an other grand but then you've everything." Zoltan -- +------------------------------------------------------------------+ | Reply address antispammed. Use ZOLTAN-at-BENDOR-dot-COM-dot-AU | +--------------------------------+---------------------------------+ | Zoltan Kocsi | I don't believe in miracles | | Bendor Research Pty. Ltd. | but I rely on them. | +--------------------------------+---------------------------------+Article: 9030
First we have > No, [all] The storage cells in CPLD are directly involved in the operation, so > they must be "read out" in a few nanoseconds, and they operate all in > parallel. That's what has given CPLD their ( historic ) speed advantage. > > I gave a probable explanation for the slow POR in a different posting to > this newsgroup. > > Peter Alfke, Xilinx Then we have > There is a fairly well-kept secret regarding CPLDs: > > Although most of their configuration is directly EPROM, EEPROM, or > Flash-based and thus does not require any lengthy power-on delay, some > of the configuration bits, although stored in the non-volatile area, > are then read out on power-up and loaded into latches. This applies to > the miscellaneous signals around the macrocells, which cannot be > conveniently or fast controlled from the well-structured non-volatile > memory area. > > Hope that helps. > Peter Alfke, Xilinx Applications Come on Peter, which is it ? AndyArticle: 9031
Peter Alfke <peter.alfke@xilinx.com> writes:
> Achim Gratz wrote:
> > Most likely because some types of EEPROM are slow to read and even
> > slower to write to.
>
> No,The storage cells in CPLD are directly involved in the operation, so
> they must be "read out" in a few nanoseconds, and they operate all in
> parallel. That's what has given CPLD their ( historic ) speed advantage.
>
> I gave a probable explanation for the slow POR in a different posting to
> this newsgroup.
I've read your explanation, but either I'm missing something or you
contradict yourself. If I read your other posting right, you say that
some CPLD are (at least partly) SRAM based and backed by EEPROM. That
only makes sense if you use cheap EEPROM for these bits and that was
actually what I thought of when making my comment. If the same fast
cells as in the signal path (if there are any at all) were used, it
would be a truly stupid circuit design if it took as long as has been
reported. Sorry if I haven't been clear. Come to think of it, if
there's a charge pump for boosting on these chips, it'll also take
it's share of the total POR time to come up.
I've just looked at the MAX9000 data sheet. The fact that they have
a "Turbo mode" would suggest that they can boost while the drawings
for the macrocell hint that the EEPROM storage is seperate from the
select muxes and integrated into the product term matrix as Peter was
explaining. I didn't find the POR time in the data sheet, though.
Achim Gratz.
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Article: 9032Hi all, I'd appreciate it if anyone could give me some advice. I have a schematic design (entered with Mentor Design Architect) targeted at a Lucent ORCA device (OR2C08). I would like to simulate this design using a VHDL testbench, but I'm having problems with the design interface. In order to map the design, chip IOs can't appear on the symbol interface (correct me if I'm wrong) otherwise the pin names are interpreted as pin locations by the Foundry mapper. So my chip IOs are internal nets. The question is, how do I apply stimulus to the device IOs if they are not on the symbol? Thanks for any help. Dave -- REMOVE "spammenot." in address to reply Dave Storrar Development Engineer | e-mail: david.storrar@gecm.com GEC-Marconi Avionics | Tel: +44 (0)131 343 4729 Radar Systems Division | Fax: +44 (0)131 343 4091 --Article: 9033
Hi,
I have a problem with simulation an Xilinx FPGA design after place and
route using the Synopsys tools. The Xilinx tools tell me that the minimum
clock period is 44 ns whereas a simulation with a 4.4 ns clock period is
still fine and I could increase the frequency even further. I don't
believe that the Xilinx timing analysis is so pessimistic that it is off
by more than a factor 10.
Im using: Xilinx M-1.3.7 and Synopsys Version 1997.08 -- Jul 11, 1997
I do: vhdlan -i of the vhdl files and then
vhdldbx -sdf_top testbench/uut -sdf time_sim.sdf CFG_TB
unfortunately I can not use compiled mode as we don't have a c-compiler
for the HP stations.
I'd apreciate any help or pointer to the solution,
Jens
--
------------------------------------------------------------
Jens-Peter Kaps, 79/8 Park Avenue., Worcester, MA 01605, USA
Home: (508) 831-9789; Office: (508) 831-5757; Fax -5491
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Article: 9034Check out new site for technology jobs .....computers/IT, engineering, design, process,CAD, application, software etc. POST RESUME FOR FREE http://www.techjobbank.comArticle: 9035
Andy Whitehouse wrote: > > First we have > > > No, [all] The storage cells in CPLD are directly involved in the > operation, so > > they must be "read out" in a few nanoseconds, and they operate all in > > parallel. That's what has given CPLD their ( historic ) speed advantage. > > Then we have > > > There is a fairly well-kept secret regarding CPLDs: > > > > Although most of their configuration is directly EPROM, EEPROM, or > > Flash-based and thus does not require any lengthy power-on delay, some > > of the configuration bits, although stored in the non-volatile area, > > are then read out on power-up and loaded into latches. This applies to > > the miscellaneous signals around the macrocells, which cannot be > > conveniently or fast controlled from the well-structured non-volatile > > memory area. > > > > Hope that helps. > > Peter Alfke, Xilinx Applications > > Come on Peter, which is it ? > > Andy I have no problem with accepting both - it fits with the behaviour I have seen on CPLD. ( try some brownout tests on your favourite CPLD .. ) In a CPLD there are TWO distinct areas, The AND/OR arrays, and the macrocells. A MacroCell has maybe 16 BITS defining all the options. Given a well structured memory area, with fast parallel access, covering 98% of the fuse terms for AND/OR. If you have, a say 5nS read time on this memory, how do you 'grab' the macrocell info on-the-fly - very hard, and you get 5nS time penaltie(s). Much easier to load the 16 bits into Latches ( so SRAM if you prefer ), that control the macrocell HW directly - now you are into sub nS GATE delays. There are also charge pumps, on some devices, and these will have multi uS delays What I have not seen, from any supplier, is a table showing - Time when outputs are completely undefined, after powerup - Time when outputs are defined, but other specs ( eg delays) are settling - Final time, when 100% spec is met. - Brownout protection - is a full re-PowerUP necessary to glitch recover ? That would be very informative. -jg.Article: 9036
I believe a co. called "V Automation" at www.vautomation.com has
synthesizable cores for the x86. I believe the x86's they're referring to
are the 8086 and 80186; don't believe they have coverage for 286 or above.
Their schtick is that the cores instruction sets are modifiable for
special apps.
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Sr. Engineer
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Joachim Strombergson <emwchim@emw.ericsson.se> wrote in article
<34DEB95A.2BED@emw.ericsson.se>...
> Tja!
>
> I'm looking for soft cores for x86 processors. Does anybody develop and
> sell such beasts? Any help greatly appreciated.
>
> --
> Med vänlig hälsning
>
> Joachim Strömbergson
> ---------------------------------------
> Joachim Strömbergson UN/X
>
> ASIC Technology and System on Silicon
> Ericsson Microwave Systems AB
> SE-431 84 Mölndal
> Joachim.Strombergson@emw.ericsson.se
> ---------------------------------------
>
Article: 9037Peter Alfke wrote: > < snip > > Certain CPLD manufacturers don't like to talk about that, because it > smudges their pristine image of non-volatility. > In reality, as Xilinx FPGAs have proven for the past 12 years, there is > nothing wrong with storing configuration in latches. You just have to > load them properly, and you have to detects Vcc dips. > Peter Alfke, Xilinx Applications So, what do the XILINX 95xx CPLDs do ? Do they POR load Macrocell info, like the others ? If you remove power, to say 1-2V, then reapply, does the part still work ? We have designed various oscillator topologies into CPLD, and found that, for example, an INVERTER does not ALWAYS invert - esp after power supply cycle tests. - jg. -- ======= Manufacturers of Serious Design Tools for uC and PLD ========= = Optimising Modula-2 Structured Text compilers for ALL 80X51 variants = Many reusable object modules - i2c, SPI, SPL, RC5, etc = Safe, Readable & Fast code - Step up from Assembler and C = Emulators / Programmers for ATMEL 89C1051, 2051, 89C51 89S8252 89C55 = *NEW* Bondout ICE for 89C51/89C52/89C55. OptoISP for 89S, AVR, AT17K. = for more info, mailto:DesignTools@xtra.co.nz Subject : c51ToolsArticle: 9038
PENG LIU wrote: > > Hi: > I used altera EPF81500-240AQC2 designing a board. There is a counter in > the fpga, but why I mesure the counter's output, I found that if I > mesuare another signal, then the counter's output is right, when I take > down the probe on another signal, the counter's lowest bit lost some > pulse. > who meet the same problem. I need help!! > > yours. > > ws. I think your problem is probing techniques,are you using good 10X probes with very short ground leads?. Have you try active probes? Regards, JackArticle: 9039
Victor Levandovsky wrote: > > Hi! > > I`m looking material about Walace tree. > Could you help me, please? > > Regardless, > > Victor Levandovsky > > vicNS@alpha.podol.khmelnitskiy.ua > > Remove NS if reply Two good books (I am only certain of the author - not the title) is computer logic design? by Kai Hwang. I used that book as a reference for writting a program for Wtree adder hardware minimization several years ago. This book devotes an entire chapter to the subject and is well worth seeking out. (I loaned mine out three years ago for this very topic and haven't gotten it back yet). Another good multiplier reference is the very old Fairchild F100 ECL user handbook, where an application note demonstrates a high-performance Booth multiplier with wallace trees (at the gate level). It gives 100% of the required info needed to quickly build and understand a multiplier. This is an old book, let me know if you have problems finding it. I inherited mine from a mainframe ASIC designer at my first job out of school. Warm Regards, rickArticle: 9040
Boulder County ASIC Positions Our chips are growing in gate counts and we need designers to join our ASIC R&D team in Longmont, Colorado. ASIC design engineering positions are available, junior through staff levels. We are looking for engineers who can design, develop, and test portions of large ASICs used in RAID storage controllers. Positions require a BSEE or MSEE or equivalent. Desired capabilities may include Verilog, Synopsys, Computer Architecture, ASIC design experience, UNIX, C/C++, Python, perl, PCI, Fibre Channel, SCSI-3,SPARC, ECC and Compression. Fujitsu Ltd. is a $36 billion technology company - the world's second largest computer company. The ASIC engineer positions available are with Fujitsu Computer Products of America, Inc., Intellistor R&D Operation in Longmont, Colorado (EOE). The positions offer an opportunity to work for an R&D division whose charter is to architect, develop, and test large, leading-edge Fujitsu ASICs and ASIC-based systems using high-end, UNIX-based tools. Applicants must possess outstanding technical capabilities (or potential), work well in a team environment, and be comfortable working with a design initiated with a "clean sheet of paper". If you would like to find out more about the company and the opportunities, please contact me via e-mail (rcarmichael@intellistor.com), or via phone at (303) 682-6551. Warm Regards, rickArticle: 9041
Achim Gratz wrote: I didn't find the POR time in the data sheet, though.
The POR time is not in the data sheet. They mention that in their design
guide lines for CPLDs under the section that talks about VCC.
Regards,
Kayvon Irani
Los Angeles. Ca
Article: 9042Hi all: I've got a problem about viewlogic/speedwave, would someon can tell me I 've a design that write in VHDL, and I split it into many entity(use hierarchy design), and now I want to verify its function, but I just can find the signal and results of top entity, all sub-entity(components) are not found by speedwave , I've use the VHDL manager to analyze all vhdl files, and add they into one library, and I use IEEE and SYSNOPSYS for sys library. Can someone tell me how to use hierarchy design in speedwave ? Thanks John HuangArticle: 9043
Zoltan Kocsi wrote: > s_clubb@die.spammer.netcomuk.co.uk (Stuart Clubb) writes: > > > So the issue is really back end fitters. To be honest, I don't know > > anybody who charges for their back end tool if you engage with them > > sensibly. > > > > e.g. "Hello Mr. Vendor, I'd like to use 10,000 of your devices. I have > > a netlist generated by my synthesis tools, and I really don't fancy > > forking out money to see whether your silicon is up to the job, and > > cost effective"..... > > "Well Mr. Customer, $500 doesn's seem too much for a very good P&R tool, > does it ? It routes all of our smaller chips. After all, you've forked > out twenty grand for your synthesis, this is just peanuts. Excuse me ? > You use unix ?! This excuse for charging high prices is starting to get old. A $20k synthesis tool cantarget a lot of different technologies and it doesn't have to run on a Unix box when PCs are starting to outperform them (not to mention the ease of maintenance and instalation of the software). Now if you are in this situation and you intend to use FPGAs, you can't directly compare different FPGAs because you need every vendor's P&R tools running at about $2k each. This has a tendency to lock you in to one or two particular vendors which can be very annoying, and you can't even be sure that you've made the right choice until after you spent your hard-earned cash. I think the vendors underestimate the potential of the small players. As ASIC methodologies are beginning to be applied by traditional PLD designers and as the software migrates towards PCs, I believe that a vendor offering free tools would capture a good part of this growing market. I hope that the arrogance of some of the vendors backfires on them. There aren't only big companies with money to waste out there. > Well, then, the situation is a little bit different, > you must be rich, so $1000 is the price, plus 20% for the compulsory > one year maintenance. Which chip ? Well, not that one, that's a high > end chip. That will be an other grand but then you've everything." > > Zoltan > > -- > +------------------------------------------------------------------+ > | Reply address antispammed. Use ZOLTAN-at-BENDOR-dot-COM-dot-AU | > +--------------------------------+---------------------------------+ > | Zoltan Kocsi | I don't believe in miracles | > | Bendor Research Pty. Ltd. | but I rely on them. | > +--------------------------------+---------------------------------+Article: 9044
Did you get any warnings at the elaboration stage? Elaboration occurs
when you select the top level entity to simulate from the working
library. This is where the simulator builds the hierarchy of the design
from the VHDL source. Even though the VHDL may be correct and compiles
without error in the HDL manager, this does not mean that the
appropriate VHDL configurations have been set up, which essentially
defines the hierarchy. If this is the case you might get warnings along
the line of:
"Configuration for component XXXX is open"
If so, you will need to add the appropriate configuration statements to
the VHDL. If it is simply multiple components at a single level of
hierarchy a default configuration of the form:
CONFIGURATION conf_name OF top_level_entity IS
FOR top_level_arch
END FOR;
END conf_name;
where conf_name is the name you assign to the configuration.
should do the trick. If the hierarchy is more complex then the
configuration statement or statements will also be more complex.
Reference to one of the standard VHDL texts such as VHDL by Douglas L.
Perry ( ISBN 0-07-049434-7 ) should help. After you have analysed this
configuration ( this type of configuration can be in a separate file and
analysed at the end. ), you then need to simulate the configuration
rather than the top level entity.
The interpretation of the VHDL LRM is a little ambiguous when it comes
to default configurations. Some simulators assume them, others require
them. The best thing to do is remove the ambiguity and always have them
where appropriate.
Hope this helps.
Regards
Will
In article <01bd3b7c$3ac4ee50$dec5af8b@ntjohn>, John Huang
<hungi@tpts4.seed.net.tw> writes
>
>Hi all:
> I've got a problem about viewlogic/speedwave, would
>someon can tell me
>
> I 've a design that write in VHDL, and I split it into
>many entity(use hierarchy design), and now I want to verify
>its function, but I just can find the signal and results of
>top entity, all sub-entity(components) are not found by speedwave
>, I've use the VHDL manager to analyze all vhdl files, and add
>they into one library, and I use IEEE and SYSNOPSYS for sys
>library.
> Can someone tell me how to use hierarchy design in speedwave
>?
>
> Thanks
> John Huang
>
--
William White
Article: 9045In article <34E6191E.4479@xtra.co.nz>, jim granville <Jim.Granville@xtra.co.nz> writes >RWilson@oxfordnuclear.com wrote: >> >> We have experienced problems with their classic line (EP1810LC-35T, >> EP910-30T, and EPM5128LC). Since the switch to the new die, the devices >> program and verify OK but they flake out in certain applications. We >> have actually had them generate enough heat to burn labels off of them. >> Altera is not really helping us and claim we are the problem. We have >> procured safety stock of old devices to protect our product lines until >> we can reach a resolution. Interestingly, the market price for older >> devices (pre die-change) has tripled in recent weeks. We are stumped. > > Problems on DIE revision are more common that many realise.. > >1) You should check carefully that the algorithm has not changed - and >get >the confirmation from as reliable as source as possible. > The reflex reaction of most FAE's is 'no, nothing has changed' > >2) try as many different BRANDS of programmer as possible > I don't think that this is the way to go. For 70% of programmable devices, there are 4 or more die changes during the device's market life. For some devices (especially CPLDs) there can be as many as a dozen changes. Leading programmer vendors work very closely with the semiconductor vendors on this issue. That's why you can buy a programmer for thousands of dollars from Data I/O (and some other major vendors), yet there are dozens of vendors of $500 programmers that seem to have an OK spec. Despite much more expensive products, Data I/O has been the market leader for 25 years, and is many times bigger than any other programmer company. The answer to this apparent paradox is also the answer to the question being posed in this thread. It costs a lot of time and money to track the constant die changes, and cheap programmer vendors don't bother. However, most serious users of programmable devices (esp. in manufacturing) know that this is the biggest single issue in device programming, and that in this respect, you get what you pay for. [Direct Insight Ltd is Data I/O's UK VAR] -- David Pashley Direct Insight LtdArticle: 9046
Test....Article: 9047
Hi, Can someone tell me what are the FPGA Xilinx parts that could be programmed using a simple download cable (like lattice parts) ??? Thanks for your help. Francois. -- ------------------------------------------------------------- THIEBOLT Francois \ You think your computer run too slow ? UPS Toulouse III \ - Check nobody's asked for tea ! thiebolt@irit.fr \ "The Hitchikers Guide to the Galaxy" D.Adams -------------------------------------------------------------Article: 9048
PLEASE IF YOU KNOW WHERE I CAN GET ACROBAT READER FOR WINDOWS3.1 IN .ZIP AND NOT MORE THEN ONE DISKET PUT ME ADRESSArticle: 9049
I am getting dragged deeper into this than I wanted to, but let me clarify: No single delay in any modern CMOS circuit is longer than 50 ns, most likely not even longer than 20 ns. We just don't waste space on large resistors and large capacitors. So when something takes microseconds or milliseconds it is always a sequential event. ( Or it is thermal, or the result of a floating node ). The "funny bits" in the CPLD are stored in the regular EPROM (EEPROM, Flash) array and then read out into their latches, where they can directly control certain functions of the macrocell. I have always assumed that this read-out is sequential, somewhat like the configuration process in FPGAs. It is sad that there is nobody at Altera willing to stick his head out. Of course they are monitoring this newsgroup, but there's no guts on Orchard Parkway... It's fun to needle somebody who is too afraid to come out of hiding, and relies on being rescued, occasionally, from New Zealand... Peter Alfke, Xilinx Applications
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