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channing-wen@usa.net wrote: > > I'd like to designs a arbiter which process two, four and > more interrupt request cause the controller can acknowledg- > ing with no priority -- just "first come, first serve", > how to implement it with less cell ? > > Any help would be greatly appreciated. > > Regards, > > Channing Wen If you can guarantee that requests will not arrive at the same time that is fine (in that case, you really don't need an arbiter...there is nothing to arbitrate). The reason for arbitration is to deal with resolving who gets the resource when more than one subscriber wants to use it at given time. To resolve this you need some sort of priority scheme. The simplest is a fixed priority, but is subject to a higher priority user hogging the resource. More complex schemes are used to make a fairer priority scheme. You would be well advised to pick up one of the many books on this subject and look it over. -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randraka The Andraka Consulting Group is a digital hardware design firm specializing in high performance FPGA designs for digital signal processing, computing and control applications.Article: 10026
Because I need a lot of those subcircuits. I'm making a pipelined, iterative circuit with many stages. staylor@dspsystems.com wrote: > Vitit, > > Even the smallest FGPA has many CLBs. Why is it so important to use 10 instead > of 17 when you have hundreds or thousands?Article: 10027
leslie.yip@asmpt.com wrote: > In fact this idea raises when I answer the e-mail from the person below. As I > come to a new company doing ASIC & FPGA design. I would like to seek advice > from different people for the company to buy a new tool for synthesis, > simulation and implementation. > > Xilinx - ... Well, there is no "one" best architecture. I use Xilinx and Lucent. I like SRAM based FPGA's.That's my bias. Someone else may want greater granularity and pick an antifuse part. If you take 8 random designs and implement all of them on 4 different FPGA's, each FPGA will probably be superior to the others on at least one design. While Xilinx has had routability problems in the past, the new XC4000EX and XC4000XL parts are much better in this respect. I have a 4062XL which I regularly route in the mid 90 % full area. However, I am also certain that other vendors are improving their architectures as well. Know your application space and pick the technology/architecture which fits best. > Epson - Auklet. SLAx000 series. ... Sorry, never used it. > Exemplar Leonardo - Unless you need the ASIC synthesis capability in Leonardo, buy Galileo Extreme instead. It onlydoes FPGA's, so it's cheaper. As of 6 months ago, it also had a better GUI. > ModelSim (V-system) - Excellent simulator. Reasonably priced on the PC. Much faster the Viewlogic's SpeedWave onVITAL based full-timing simulations (I'm sorry to say). It's down sides are a VERY week scripting language (I guess they assume you can always write VHDL to do things other simulators let you do in a script!) and no hierarchical block diagram viewer. I use ViewDraw to capture the hierarchy of a design and plug VHDL modules into the schematic. When I'm simulating, I then have a broad view over the design flow since SpeedWave annotates back to the schematic. I find the Modelsim windows very cumbersome to traverse. In one Viewlogic schematic I can see what I need several Modelsim windows to view. This greatly speeds debugging. > Viewlogic - ViewLogic consists of ViewDraw,ViewSim and ViewTrace which Thank heavens Viewlogic is getting out of the synthesis business. ViewSynthesis was a joke and I don't know anyone using Aurora. ViewTrace is gone, replaced by ViewWave. ViewWave is both better and worse then ViewTrace. If you are going to have ViewSim, you really should also get SpeedWave. As long as you stay away from really big VITAL simulations (14 Meg VHDL netlists), SpeedWave will be just dandy for you. While Modelsim is a nifty simulator, the fact that SpeedWave is integrated to ViewDraw & ViewSim makes it THE simulator you should buy if you can only buy one. Just my two bits (inflation you know).Article: 10028
PAM-Blox version 1.0 are object-oriented netlist generator in C++ built on top of DIGITALs PamDC. Currently PAM-Blox are limited to Xilinx XC4000 and XC3000 series FPGAs. The PAM-Blox package has been tested under MS Visual C++ on a PC, and DIGITAL C++ on an Alpha workstation. PAM-Blox sources are distributed with a GNU General Public License. This means they are free for anyone to download, use and contribute. Serious contributions will be considered for the next release. more details at: http://umunhum.stanford.edu/PAM-Blox/ Oskar Mencer ------------------------------------------------------------- Computer Systems Laboratory Department of Electrical Engineering Stanford, CA 94305 email: oskar@umunhum.stanford.edu -------------------------------------------------------------Article: 10029
I would like to seek more advice on Exemplar leslie.yip@asmpt.com wrote: > In fact this idea raises when I answer the e-mail from the person below. As I > come to a new company doing ASIC & FPGA design. I would like to seek advice > from different people for the company to buy a new tool for synthesis, > simulation and implementation. > > Xilinx - ... Well, there is no "one" best architecture. I use Xilinx and Lucent. I like SRAM based FPGA's.That's my bias. Someone else may want greater granularity and pick an antifuse part. If you take 8 random designs and implement all of them on 4 different FPGA's, each FPGA will probably be superior to the others on at least one design. While Xilinx has had routability problems in the past, the new XC4000EX and XC4000XL parts are much better in this respect. I have a 4062XL which I regularly route in the mid 90 % full area. However, I am also certain that other vendors are improving their architectures as well. Know your application space and pick the technology/architecture which fits best. > Epson - Auklet. SLAx000 series. ... Sorry, never used it. > Exemplar Leonardo - Unless you need the ASIC synthesis capability in Leonardo, buy Galileo Extreme instead. It onlydoes FPGA's, so it's cheaper. As of 6 months ago, it also had a better GUI. > ModelSim (V-system) - Excellent simulator. Reasonably priced on the PC. Much faster the Viewlogic's SpeedWave onVITAL based full-timing simulations (I'm sorry to say). It's down sides are a VERY week scripting language (I guess they assume you can always write VHDL to do things other simulators let you do in a script!) and no hierarchical block diagram viewer. I use ViewDraw to capture the hierarchy of a design and plug VHDL modules into the schematic. When I'm simulating, I then have a broad view over the design flow since SpeedWave annotates back to the schematic. I find the Modelsim windows very cumbersome to traverse. In one Viewlogic schematic I can see what I need several Modelsim windows to view. This greatly speeds debugging. I would like to hear more about Exemplar Leonlardo > Viewlogic - ViewLogic consists of ViewDraw,ViewSim and ViewTrace which Thank heavens Viewlogic is getting out of the synthesis business. ViewSynthesis was a joke and I don't know anyone using Aurora. ViewTrace is gone, replaced by ViewWave. ViewWave is both better and worse then ViewTrace. If you are going to have ViewSim, you really should also get SpeedWave. As long as you stay away from really big VITAL simulations (14 Meg VHDL netlists), SpeedWave will be just dandy for you. While Modelsim is a nifty simulator, the fact that SpeedWave is integrated to ViewDraw & ViewSim makes it THE simulator you should buy if you can only buy one. Just my two bits (inflation you know). In article <6hl7s5$69r@sjx-ixn9.ix.netcom.com>, "Steven K. Knapp" <sknapp@optimagic.com> wrote: > > > leslie.yip@asmpt.com wrote in message <6hkboc$k6o$1@nnrp1.dejanews.com>... > [snip] > >Xilinx - very popular vendor. Good FPGA tool. Excellent for moderate design > >like joystick, Gun for playing TV games (PS, .....). But it seems quite > >difficult for trouble shooting on a large design about 30,000 gates on PC > >environment. I have used to design a video ASIC chip with DRAM & SDRAM > >controller. Another problem is the cost. It is quite expensive, probablity > >because its name is commonly known. > [snip] > > Various programmable logic vendors and related software vendors provide > their tools at little or no cost for evaluation purposes. The Programmable > Logic Jump Station maintains a list of available options at > http://www.optimagic.com/lowcost.html. > > Also, as most of the programmable logic vendors are using advanced > processing technology (0.35u, three-layer metal CMOS and beyond), FPGA > prices will be coming down dramatically. There will always be some > expensive FPGA, but at the upper end of performance or density. In some > ways, the FPGA market is like the PC market. You can buy a high-end PC > today, but the same machine will be much cheaper next year. Or, for the > same amount of money as today's high-end PC, you could buy an even > higher-performance machine next year. > > ----------------------------------------------------------- > Steven K. Knapp > OptiMagic, Inc. -- "Great Designs Happen 'OptiMagic'-ally" > E-mail: sknapp@optimagic.com > Web: http://www.optimagic.com > ----------------------------------------------------------- > > -----== Posted via Deja News, The Leader in Internet Discussion ==----- http://www.dejanews.com/ Now offering spam-free web-based newsreadingArticle: 10030
In article <6hl7s5$69r@sjx-ixn9.ix.netcom.com>, "Steven K. Knapp" <sknapp@optimagic.com> wrote: > > > leslie.yip@asmpt.com wrote in message <6hkboc$k6o$1@nnrp1.dejanews.com>... > [snip] > >environment. I have used to design a video ASIC chip with DRAM & SDRAM > >controller. Another problem is the cost. It is quite expensive, probablity > >because its name is commonly known. > [snip] Last I checked, the US$99 package from Xilinx could be used for their CPLDs and some FPGAs (up to 20k gates). No VHDL for that price, though. -----== Posted via Deja News, The Leader in Internet Discussion ==----- http://www.dejanews.com/ Now offering spam-free web-based newsreadingArticle: 10031
In article <353E73F3.62B5@ids.net>, Ray Andraka <no_spam_randraka@ids.net> wrote: > > If you can guarantee that requests will not arrive at the same time that > is fine (in that case, you really don't need an arbiter...there is > nothing to arbitrate). The reason for arbitration is to deal with > resolving who gets the resource when more than one subscriber wants to > use it at given time. To resolve this you need some sort of priority > scheme. The simplest is a fixed priority, but is subject to a higher > priority user hogging the resource. More complex schemes are used to > make a fairer priority scheme. You would be well advised to pick up one > of the many books on this subject and look it over. > -- > -Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email randraka@ids.net > http://users.ids.net/~randraka > > The Andraka Consulting Group is a digital hardware design firm > specializing in high performance FPGA designs for digital signal > processing, computing and control applications. > Thans for your answer. But there are two retrict in my project. First, I CAN'T guarantee that requests will not arrive at the same time; The Second, the requests are realy "First Come, First Served", I CAN'T set any other priority, for instance, there are four requests INT0, INT1, INT2 and INT3 will arrive at any time, when the controller processing the first request -- maybe is INT0, the INT3 is arrive, and the INT1 is arrive after a while but before the controller finish to process the INT0, in this case, the controller will acknowledge the INT3 but NOT INT1 when the last task is over. Regards, Channing Wen -----== Posted via Deja News, The Leader in Internet Discussion ==----- http://www.dejanews.com/ Now offering spam-free web-based newsreadingArticle: 10032
On 22 Apr 1998, Per Fremrot wrote: > FPGA-compiler libraries. I am trying to port a standard cell design to > FPGA (Xilinx) and have (not suprisingly) run into some performance > problems. > ............... > compile -map_effort high > ............... > imaginge that it is pretty difficult to do optimization on CLBs, but > the performance I get is not very impressive. Is this step skipped on Same case with me. When I start using FPGA compiler I don't know what it is doing inside. But after half year doing this I have some idea about that: 1. break down the whole design into hierarchy, until a module is less than 10 CLBs. Doing this need to understand the actual structure inside the CLBs. 2. write behavioral code is ok, but read the XSI guide on xilinx web. 3. port map the whole design, at the same time transfer to the mapper for further optimization. This is my case, when i start a design on FPGA. If you have already design using standard cell, I think a partial redesign is needed.. ------------------------------------------------------------------------------- | Best Regards, +--------+ | Email: eg_hsh@stu.ust.hk | | David Ho | ¦ó²Ðºµ | | cshosh@cs.ust.hk | | Ho Siu Hung +--------+ | | | University of Science and Technology | ICQ#: 798357 | | Computer Engineering Year 3 (CPEG) =======================================| -------------------------------------------------------------------------------Article: 10033
Hi all of you; I have design composed from blocks, each block has some components (e.g.: DFF, AND, XOR), and then one block composing those defined blocks. My question is when I am using synopsys simulation for any block it ask for configuration. How can I insert configuration? Should I write it in the top of each block? Any one could help! "I need this step to verify each block and the top level block" Thanks in advanceArticle: 10034
This paper possibly could help you: T. T. Do, H. Kropp, M. Schwiegershausen, P. Pirsch, "Implementation of Pipelined Multipliers on Xlinix FPGAs," Proceedings of the 7th International Workshop Field-Programmable Logic and Applications (FPL '97), W. Luk, P. Y. K. Cheung, M. Glesner, eds., Springer Verlag, September 1997, pp. 51-60. Best regards DirkArticle: 10035
Azeddien Sllame (Sllame@dcse.fee.vutbr.cz) wrote: : I have design composed from blocks, each block has some components : (e.g.: DFF, AND, XOR), and then one block composing those defined : blocks. : My question is when I am using synopsys simulation for any block it ask : for configuration. How can I insert configuration? : Should I write it in the top of each block? No, you need to write a top-level configuration declaration. Synopsys holds the somewhat unusual position that a top-level configuration is required. BTW, this configuration declaration must be the last design unit to be compiled. Hope this helps, Paul -- Paul Menchini | mench@mench.com | "Every damn thing is your Menchini & Associates | www.mench.com | own fault if you're any P.O. Box 71767 | 919-479-1670[v] | good." Durham, NC 27722-1767 | 919-479-1671[f] | -- Ernest HemingwayArticle: 10036
This may not answer your exact question but here is some advise from
someone who has been there.
Assumptions I'm making:
1. The original design is schematic and not HDL. (If it's HDL retargeting
is better than translation)
2. Your flow is something like this.
a. read edif (standard cell vendor libraries)
b. set libraries to translate to xilinx libraries
c. perform translation
d. optimizing design for speed. (try)
e. insert pads replace fpga etc.
Some things to beware of:
1. How many clock do you have? Relative to number of bufg that are
available in your target part.
2. Look for set/reset flops. Can't do them in a xilinx.
3. Look at your reset circuit can you adapted it to the GSR? This will
save routing resource.
As far as optimization goes there are a few things you can do.
1. Set a timing constraint for the translation. Letting synopsys know what
your trying to accomplish at this point is a generally a good think to do.
But it can slow this step down.
2. You can try optimizing after you translate. You can do this on a block
by block basis if needed. But before you spend a lot of time here you should
look at some of the worst paths and see how many CLB levels you have between
flops. If it's more than you can handle you can optimize for 100 years and
never make the goal. (The xilinx lititure has some good explanations of
this.)
3. What to do if you you have to many levels.
a. Look at the design for larger library elements. counter adders
etc. When you translate you get a gate level implementation of these. To
get a xilinx to run at any speed you need XBLOX (or logicblox)
implementations. You get them when you start with HDL. But not when you
translate (At least I haven't found a way to get them.) There is a very
easy fix. Take each library element and write a HDL replacement for it.
Making the entity name match the library name. Compile this into your
target technology (make sure you have XBLOX turned on) and save the db
file. Now right after translation you need to go find all of the instance
of that library element remove them from the design, read in your previously
compiled db file and relink the design. the flow continues from there.
This usually helps a lot and isn't that much work. You can do the same
thing for big blocks if you need to or to help translate library elements
that don't translate.
Best Regards
Carl Christensen
Per Fremrot wrote:
> I have just started to use Synopsys FPGA compiler and I am slightly
> confused regarding the difference in optimization between DC and
> FPGA-compiler libraries. I am trying to port a standard cell design to
> FPGA (Xilinx) and have (not suprisingly) run into some performance
> problems.
>
> If I use the design compiler libraries for Xilinx the compilation
> looks like when I'm using an ordinary standard cell library. If I
> instead use the libraries for the FPGA compiler the optimization looks
> like this:
>
> ===============================
>
> compile -map_effort high
>
> -cut-
>
> OPTIMIZATION DESIGN RULE
> TRIALS AREA DELTA DELAY COST COST
> -------- ------ ----------- ------ ------
> 0
> --------
> 0
>
>
> Optimization complete
> ---------------------
>
> ===============================
>
> No optimization at all here ! Is this the correct behavior ? I can
> imaginge that it is pretty difficult to do optimization on CLBs, but
> the performance I get is not very impressive. Is this step skipped on
> purpose or could this be Synopsys way of saying "it's no use trying, I
> give up..." ?
>
> /Per Fremrot
> Per.Fremrot@tde.lth.se
Article: 10037Carl Christensen <carl@philipsdvs.com> writes: Thanks the input. However the circumstances are slighly different. I am using the HDL-code so XBLOX etc is no big problem. My major concern if it is correct of Synopsys to skip the cost-driven optimization I can see when you normally compile, or if it aborts before starting because the design is too large or something. I'm used to see Synopsys optimize the "delta delay" from something to zero, and the fix the design rules in the second pass. I get "nothing" right now. I will look at the other things too (clocks, FFs, reset) but I don't think that it should be a big problem since I hace the RTL-code. I am not area limited (yet!). Best regards Per Fremrot > This may not answer your exact question but here is some advise from > someone who has been there. > > Assumptions I'm making: > > 1. The original design is schematic and not HDL. (If it's HDL retargeting > is better than translation) > 2. Your flow is something like this. > a. read edif (standard cell vendor libraries) > b. set libraries to translate to xilinx libraries > c. perform translation > d. optimizing design for speed. (try) > e. insert pads replace fpga etc. > > Some things to beware of: > 1. How many clock do you have? Relative to number of bufg that are > available in your target part. > 2. Look for set/reset flops. Can't do them in a xilinx. > 3. Look at your reset circuit can you adapted it to the GSR? This will > save routing resource. > > As far as optimization goes there are a few things you can do. > 1. Set a timing constraint for the translation. Letting synopsys know what > your trying to accomplish at this point is a generally a good think to do. > But it can slow this step down. > 2. You can try optimizing after you translate. You can do this on a block > by block basis if needed. But before you spend a lot of time here you should > look at some of the worst paths and see how many CLB levels you have between > flops. If it's more than you can handle you can optimize for 100 years and > never make the goal. (The xilinx lititure has some good explanations of > this.) > 3. What to do if you you have to many levels. > a. Look at the design for larger library elements. counter adders > etc. When you translate you get a gate level implementation of these. To > get a xilinx to run at any speed you need XBLOX (or logicblox) > implementations. You get them when you start with HDL. But not when you > translate (At least I haven't found a way to get them.) There is a very > easy fix. Take each library element and write a HDL replacement for it. > Making the entity name match the library name. Compile this into your > target technology (make sure you have XBLOX turned on) and save the db > file. Now right after translation you need to go find all of the instance > of that library element remove them from the design, read in your previously > compiled db file and relink the design. the flow continues from there. > This usually helps a lot and isn't that much work. You can do the same > thing for big blocks if you need to or to help translate library elements > that don't translate. > > Best Regards > Carl Christensen > > Per Fremrot wrote: > > > I have just started to use Synopsys FPGA compiler and I am slightly > > confused regarding the difference in optimization between DC and > > FPGA-compiler libraries. I am trying to port a standard cell design to > > FPGA (Xilinx) and have (not suprisingly) run into some performance > > problems. > > > > If I use the design compiler libraries for Xilinx the compilation > > looks like when I'm using an ordinary standard cell library. If I > > instead use the libraries for the FPGA compiler the optimization looks > > like this: > > > > =============================== > > > > compile -map_effort high > > > > -cut- > > > > OPTIMIZATION DESIGN RULE > > TRIALS AREA DELTA DELAY COST COST > > -------- ------ ----------- ------ ------ > > 0 > > -------- > > 0 > > > > > > Optimization complete > > --------------------- > > > > =============================== > > > > No optimization at all here ! Is this the correct behavior ? I can > > imaginge that it is pretty difficult to do optimization on CLBs, but > > the performance I get is not very impressive. Is this step skipped on > > purpose or could this be Synopsys way of saying "it's no use trying, I > > give up..." ? > > > > /Per Fremrot > > Per.Fremrot@tde.lth.seArticle: 10038
Garage startup needs help building prototype of new hardware product. Product is designed down to block diagrams and some schematics. But we need someone to do a simple FPGA and to complete schematic capute and to debug board. You must have your own facilities. I return for these services, you would receive equity, and defered compensation. While I cannot expain the nature of the product in this forum, it is a consumer product that will have major a major impact on the home computer and home entertainment markets. Please respond to hank777@aol.comArticle: 10039
Hiya, I'm having severe problems with ground bouncing while driving 32 bit data to the output. I'm using a XC4010XL-2. The design uses 4 clok inputs (two 53Mhz clocks and two 106Mhz clocks) Turning off the FAST attribute seemed to help a lot. But still the ground bouncing occurs. Sometimes more than 2V overshoot. Anyone having similar problems and know how to fix this ? With a XC4000E-2 (same design) I didn't have problems. Thanks in advance, KimArticle: 10040
Hi all:
I've use altera 10K20 (240 pin) in my design,
but when I use the BYTEBlaster to download the
sof file, I found the fpga didn't work, all I/O pins
are present high or Hi-Z, I'm sure the download
procedure was successful, the MaxPlus II tell me
it work fine, and I had see the all signal is work when
download(Status, DCLK, D0, Conf, CONF_DONE)
and CE, MSEL0, MSEL1 is connected with ground,
why the chip don't work, please someone help me
thanks
John Huang
Article: 10041Yes, Atmel. That was posted before I read your post. I hope that Atmel's software is easy to learn to be worth the time. Martin Mason wrote: > What about Atmel ???? > > Martin. >Article: 10042
If it is May 1, 1998 or later, please ignore this message. Thank you. Hi, My name is Richard, and this the most humiliating thing I've done in my life. I just don't know what else to do. My last resort. I'm a grad student in Instructional Technology at Chico State, but because of circumstances completely beyond my control, I have to--must-- raise $1560.00 by the end of this month (April). I lost my job because of a lay-off and I haven't been able to find other work (Chico, CA is a small community, with very little job oportunities).....Anyway, and this is the humiliating part: If you can help, please do. What I'm asking is for some of you who read this to please send me a $1 or two--or whatever you can--to the address below. This is a plea out of desperation. I just don't know where else to turn. The only thing I can promise you in return is: 1) a HEART-FELT THANKS, 2) A personal reply about how I'm doing, and 3) Repayment with interest (I will try to double your donation) ASAP. I will do my best to repay you within six months (sooner if possible). I will pay you the interest (double your money) ASAP--within the year I expect. I'm so ashamed of having to do this, and I know many, if not most of you will think this is a hoax. It isn't; I'm just desperate. Thank you from my heart if you can help, and if you help, you will be hearing from me--immediately. Please send whatever you can to the address below, and if you want to write me (I expect a lot of hate mail, and that's ok) you can e-mail me at "rico@ecst.csuchico.edu" or "rhowngtn@aol.com" (the aol account may not exist after April 30th)). THANK YOU! Also, if you're an employer in the Chico area, PLEASE contact me... I'm personable, reliable, honest, hard-working, and I'm familiar with several computer graphics applications (Photoshop, Director, Premiere, etc. I don't know Illustrator, but I'm learning Bryce 3D... and , if it matters, I can "get by" in German [I graduated from Biola University with a Major in ancient Greek (koine) and minors in German and Philosphy--Graduated summa cum laude with a 3.96 GPA.. Sincerely, Richard H. 236 W. East Ave. Apt. 163 Chico, CA 95926Article: 10043
Hi, I want to implement an LCD controller (1/4 VGA) on an ALTERA CPLD (FLEX 10K), if possible with several layers of overlapping characters and graphics. Does anybody know of some existing Macros/LPMs that I could use as a starting point? Thanks, Alex.Article: 10044
Most any programmer that claim to be able to program these parts have these set as 'options'. I know the late(r) Data I/O and BP MicroSystems do it this way. You might have to get late(r) software for your Data OH-NO! or what ever programmer you are using. I remember 6 years ago having to change some locations when using a Data OH-NO! UniSite. I think that is so lame on the programmer manufacturers to not make this easier...but I believe most do these days. Austin Franklin darkroom@ix.netcom.com Peter <z80@ds2.com> wrote in article <353f3d31.1059876611@news.netcomuk.co.uk>... > I had to do this manually too, on my Data I/O Chiplab programmer. > > One could develop a little awk program which would run, in e.g. a > batch file, and edit the .mcs file as required. > > >I am involved in a design using Xilinx FPGAs, using the Foundation 1.4 > >package. I am configuring the part from a Xilinx 17128D serial PROM. To > >make the PROM work, I must change the polarity of the RESET/OE pin by > >writing data to 4 locations in the part. For the life of me, I can't seem > >to find a way to automate this using the Foundation toolset. Currently I > >must edit the MCS file or manually edit the data on the programmer. Surely > >this has been addressed many times and an easy solution is available, or the > >solution is within the toolset and I'm just missing it. Any help in solving > >this problem will be greatly appreciated. > > > Peter. > > Return address is invalid to help stop junk mail. > E-mail replies to zX80@digiYserve.com but > remove the X and the Y. >Article: 10045
Kim Hofmans wrote: > > Hiya, > > I'm having severe problems with ground bouncing while driving 32 bit data > to the > output. I'm using a XC4010XL-2. > The design uses 4 clok inputs (two 53Mhz clocks and two 106Mhz clocks) > Turning off the FAST attribute seemed to help a lot. But still the ground > bouncing occurs. Sometimes more than 2V overshoot. > > Anyone having similar problems and know how to fix this ? > > With a XC4000E-2 (same design) I didn't have problems. > > Thanks in advance, > > Kim Good PCB design with very low impedance power/ground distribution and good bypassing at the power pins. Keep to dynamic loading on the FPGA outputs small too (especially watch capacitance). You may also need to control the impedance of signal lines. -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randraka The Andraka Consulting Group is a digital hardware design firm specializing in high performance FPGA designs for digital signal processing, computing and control applications.Article: 10046
Peter wrote: > > I had to do this manually too, on my Data I/O Chiplab programmer. > > One could develop a little awk program which would run, in e.g. a > batch file, and edit the .mcs file as required. > Looking at the BitGen & PromGen documentation there really doesn't seem to be any way top do this. You would probably be better off using the ATMEL reconfigurable serial EEPROMs which are programmed via the I2C i/f. You could do this from a PC parallel port with 3/4 wires connected to an 8-DIP socket.Its much easier to set the ATMEL's polarity bits than with the Xilinx SPROMs. BTW Why AWK ? I'd suggest discovering the wonders of PERL (esp. V5). -- _________________________________________________________________________ Dr. Richard Filipkiewicz phone: +44 171 700 3301 Algorithmics Ltd. fax: +44 171 700 3400 3 Drayton Park email: rick@algor.co.uk London N5 1NU EnglandArticle: 10047
In article <353E2CBF.E3221E3C@computer.org>, Vitit Kantabutra <vkantabu@computer.org> wrote: > > So why not have several "flavor" of CLB's? There are certainly enough > models of FPGA's out there to support that. > Because there is such a thing as lawsuits and intellectual property. Scott Taylor - DSP Fibre Channel Systems -----== Posted via Deja News, The Leader in Internet Discussion ==----- http://www.dejanews.com/ Now offering spam-free web-based newsreadingArticle: 10048
Actel: It seems to have good support and good for moderate design. Anyone know more ? In article <6hmb5v$ikn$1@nnrp1.dejanews.com>, leslie.yip@asmpt.com wrote: > > I would like to seek more advice on Exemplar > > leslie.yip@asmpt.com wrote: > > > In fact this idea raises when I answer the e-mail from the person below. As > I > > come to a new company doing ASIC & FPGA design. I would like to seek advice > > from different people for the company to buy a new tool for synthesis, > > simulation and implementation. > > > > Xilinx - ... > > Well, there is no "one" best architecture. I use Xilinx and Lucent. I like > SRAM based FPGA's.That's my bias. Someone else may want greater granularity > and pick an antifuse part. If you take 8 random designs and implement all of > them on 4 different FPGA's, each FPGA will probably be superior to the others > on at least one design. While Xilinx has had routability problems in the > past, the new XC4000EX and XC4000XL parts are much better in this respect. I > have a 4062XL which I regularly route in the mid 90 % full area. However, I > am also certain that other vendors are improving their architectures as well. > Know your application space and pick the technology/architecture which fits > best. > > > Epson - Auklet. SLAx000 series. ... > > Sorry, never used it. > > > Exemplar Leonardo - > > Unless you need the ASIC synthesis capability in Leonardo, buy Galileo Extreme > instead. It onlydoes FPGA's, so it's cheaper. As of 6 months ago, it also > had a > better GUI. > > > ModelSim (V-system) - > > Excellent simulator. Reasonably priced on the PC. Much faster the > Viewlogic's > SpeedWave onVITAL based full-timing simulations (I'm sorry to say). > > It's down sides are a VERY week scripting language (I guess they assume you > can > always write VHDL to do things other simulators let you do in a script!) and > no hierarchical > block diagram viewer. > > I use ViewDraw to capture the hierarchy of a design and plug VHDL modules into > the > schematic. When I'm simulating, I then have a broad view over the design flow > since SpeedWave > annotates back to the schematic. I find the Modelsim windows very cumbersome > to traverse. > In one Viewlogic schematic I can see what I need several Modelsim windows to > view. This > greatly speeds debugging. > > I would like to hear more about Exemplar Leonlardo > > Viewlogic - ViewLogic consists of ViewDraw,ViewSim and ViewTrace which > > Thank heavens Viewlogic is getting out of the synthesis business. > ViewSynthesis was a joke and I don't know anyone using Aurora. ViewTrace is > gone, replaced by ViewWave. > ViewWave is both better and worse then ViewTrace. > > If you are going to have ViewSim, you really should also get SpeedWave. As > long as you stay away from really big VITAL simulations (14 Meg VHDL > netlists), SpeedWave will be just dandy for you. While Modelsim is a nifty > simulator, the fact that SpeedWave is integrated to ViewDraw & ViewSim makes > it THE simulator you should buy if you can only buy one. > > Just my two bits (inflation you know). > > In article <6hl7s5$69r@sjx-ixn9.ix.netcom.com>, > "Steven K. Knapp" <sknapp@optimagic.com> wrote: > > > > > > leslie.yip@asmpt.com wrote in message <6hkboc$k6o$1@nnrp1.dejanews.com>... > > [snip] > > >Xilinx - very popular vendor. Good FPGA tool. Excellent for moderate design > > >like joystick, Gun for playing TV games (PS, .....). But it seems quite > > >difficult for trouble shooting on a large design about 30,000 gates on PC > > >environment. I have used to design a video ASIC chip with DRAM & SDRAM > > >controller. Another problem is the cost. It is quite expensive, probablity > > >because its name is commonly known. > > [snip] > > > > Various programmable logic vendors and related software vendors provide > > their tools at little or no cost for evaluation purposes. The Programmable > > Logic Jump Station maintains a list of available options at > > http://www.optimagic.com/lowcost.html. > > > > Also, as most of the programmable logic vendors are using advanced > > processing technology (0.35u, three-layer metal CMOS and beyond), FPGA > > prices will be coming down dramatically. There will always be some > > expensive FPGA, but at the upper end of performance or density. In some > > ways, the FPGA market is like the PC market. You can buy a high-end PC > > today, but the same machine will be much cheaper next year. Or, for the > > same amount of money as today's high-end PC, you could buy an even > > higher-performance machine next year. > > > > ----------------------------------------------------------- > > Steven K. Knapp > > OptiMagic, Inc. -- "Great Designs Happen 'OptiMagic'-ally" > > E-mail: sknapp@optimagic.com > > Web: http://www.optimagic.com > > ----------------------------------------------------------- > > > > > > -----== Posted via Deja News, The Leader in Internet Discussion ==----- > http://www.dejanews.com/ Now offering spam-free web-based newsreading > -----== Posted via Deja News, The Leader in Internet Discussion ==----- http://www.dejanews.com/ Now offering spam-free web-based newsreadingArticle: 10049
This is a multi-part message in MIME format. ------=_NextPart_000_000E_01BD6F78.03D08DC0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable John Huang wrote in message <353F9085.1156C0A4@tpts4.seed.net.tw>... >Hi all: > I've use altera 10K20 (240 pin) in my design, > but when I use the BYTEBlaster to download the >sof file, I found the fpga didn't work, all I/O pins >are present high or Hi-Z, I'm sure the download >procedure was successful, the MaxPlus II tell me >it work fine, and I had see the all signal is work when >download(Status, DCLK, D0, Conf, CONF_DONE) >and CE, MSEL0, MSEL1 is connected with ground, >why the chip don't work, please someone help me >thanks > > John Huang > Please, check Global Project Device Options=20 In this menu User-Supplied Start-Up Clock should be unchecked Same option also present in device option. After downloading ALTERA finished initialization procedure after = additional ~10 clocks. And BYTEBlaster provides this clocks. Good luck=20 Lev ------=_NextPart_000_000E_01BD6F78.03D08DC0 Content-Type: text/html; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable <!DOCTYPE HTML PUBLIC "-//W3C//DTD W3 HTML//EN"> <HTML> <HEAD> <META content=3Dtext/html;charset=3Diso-8859-1 = http-equiv=3DContent-Type> <META content=3D'"MSHTML 4.72.2106.6"' name=3DGENERATOR> </HEAD> <BODY> <DIV> </DIV> <DIV>John Huang<HUNGI@TPTS4.SEED.NET.TW> wrote in message <<A=20 href=3D"mailto:353F9085.1156C0A4@tpts4.seed.net.tw">353F9085.1156C0A4@tpt= s4.seed.net.tw</A>>...</DIV> <DIV>>Hi all:<BR>> I've use altera 10K20 (240 = pin) in my=20 design,<BR>> but when I use the BYTEBlaster to download = the<BR>>sof file,=20 I found the fpga didn't work, all I/O pins<BR>>are present high or = Hi-Z, I'm=20 sure the download<BR>>procedure was successful, the MaxPlus II tell=20 me<BR>>it work fine, and I had see the all signal is work=20 when<BR>>download(Status, DCLK, D0, Conf, CONF_DONE)<BR>>and CE, = MSEL0,=20 MSEL1 is connected with ground,<BR>>why the chip don't work, please = someone=20 help me<BR>>thanks<BR>><BR>> John = Huang<BR>></DIV> <DIV> </DIV> <DIV><FONT style=3D"BACKGROUND-COLOR: #ffffff">Please, check <FONT = color=3D#000000=20 face=3DArial size=3D3><STRONG>Global Project Device Options=20 </STRONG></FONT></FONT></DIV> <DIV><FONT color=3D#000000 face=3DArial size=3D3>In this menu = <STRONG>User-Supplied=20 Start-Up Clock</STRONG> should be unchecked</FONT></DIV> <DIV><FONT color=3D#000000 face=3DArial size=3D3>Same option also = present in device=20 option.</FONT></DIV> <DIV>After downloading ALTERA finished initialization procedure after=20 additional</DIV> <DIV>~10 clocks. And BYTEBlaster provides this clocks.</DIV> <DIV>Good luck </DIV> <DIV> Lev</DIV></BODY></HTML> ------=_NextPart_000_000E_01BD6F78.03D08DC0--
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