Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
>This is probably not the same thing as CE'ing the FFs. Did the clock >still get distributed through the clock tree or not? Yes, the clock did still get distributed. This cannot be stopped, unless you gate the global clocks before the ACLK/GCLK buffers. >So CE'ing does only avoid the fourth part, while gated local clocks >might skip on the second, depending on exactly how the routing works >and whether you need the global clock for something else. Sure. As I said, the effect of having a permanent global clock and using CE, versus gating all the clocks, can be a factor of several times. But most of this difference is probably due to interconnect capacitance. Does this matter? In an FPGA one cannot really avoid interconnects :) Peter. Return address is invalid to help stop junk mail. E-mail replies to zX80@digiYserve.com but remove the X and the Y.Article: 10326
"John Huang" <hungi@tpts4.seed.net.tw> wrote: >Hi: > I 've a problem with my design , could anyone can tell me that >3.3V and 5V chip has any differents? > My current design using altera 10K20-3, it's 5V I/O chip, but >its speed is too slow that does not suit my timing, I've contact the >sales of altera, he tell me the -3 is the fastest chip of 10K20, If >I want a faster chip, they have 10K70 for -1, but it is 3.3V, but >my board's I/Os are connect to 5V chip, I wonder if they can't >work fine, can I replace 10K20 for 5V to 10K70 for 3.3V directly? No. If the data book says its a 3.3V device, you must power it with 3.3V or you'll fry it. Speed improvements in VLSI devices has been obtained by shrinking the geometry to sub-micron levels. This has the side-effect of reducing the potential barrier between features within the device to levels that can be breached by just a few volts. Sometimes, however, you can connect the IO of 3.3V devices directly to the IO of 5V devices. Altera FLEX 10KA is an example of this. You need to know what you are doing, though - study the databooks carefully. Watch out for the max high level input voltage of 5.3V - if your signal lines are too long, you could overshoot this on low-to-high transitions due to inductive effects. -- Dave FarranceArticle: 10327
Simply inferring your 19 bit adder should cause Express to create a Logiblox element in the netlist. You should have a timing constraint on the counter as well. Check the logfile output to verify LogiBlox activity. Feel free to contact me if this doesn't seem to work for you. -- Ed McCauley Bottom Line Technologies Inc. Specializing Exclusively in Xilinx Design, Development and Training Voice: (500) 447-FPGA, (908) 996-0817 FAX: (908) 996-0817 Vo To wrote: > > Hi, > > One of the requirements of my FPGA design is to have a fast 19-bit > adder. > > How do I instantiate or infer a fast carry-logic adder in FPGA Express? > I read the XSI Design Guide, it said to use LogiBlox components. > However, inside FPGA Express, I can't use the Logiblox library. For > example: > > LIBRARY logiblox; > USE logiblox.mvlutil.ALL; > USE logiblox.mvlarith.ALL; > USE logiblox.logiblox.ALL; > > gives me errors that it's not recognizing the library. > > Thanks in advance.Article: 10328
Gilles: DEFINITELY get your post route timing report to your FAE. 135ns of routing delay is UNHEARD of. NOW: If that 135ns includes 11 layers of logic in a -4 part, well that's a different story. Figure 4ns per level and a matching amount of routing delay.... that's (4*11)*2=88ns. Add a convoluted circuit and yup, you can be running that slow. I'd first seek to understand your required functionality. Next I'd be looking for high fan out signals and address that potential problem. I'd also attempt to pipeline the process. Either way, it seems that an architectural solution is indicated. FWIW, Getting onto and off of an FPGA is the slowest thing you can do. We try to register everything on and off of our designs where possible. Best wishes. Let me know if I may be of further assistance. -- Ed McCauley Bottom Line Technologies Inc. Specializing Exclusively in Xilinx Design, Development and Training Voice: (500) 447-FPGA, (908) 996-0817 FAX: (908) 996-0817 Ries Gilles wrote: > > Hi ! > > I've just made a circuit with an Xilinx XC4044XL. > > I was amazed that 85% of the critical path delay was due to the routing > delay. Can it be considered correct, or did something go wrong in the > placement/routing ? > > In my case, I had 11 levels of logic, between a pad and a FF, and 20 ns > of logic, and 135 ns of Routing delay. I used the highest optimisation > effort possible with enough iteration. > > Thanks. > > Gilles.Article: 10329
Gilles: DEFINITELY get your post route timing report to your FAE. 135ns of routing delay is UNHEARD of. NOW: If that 135ns includes 11 layers of logic in a -4 part, well that's a different story. Figure 4ns per level and a matching amount of routing delay.... that's (4*11)*2=88ns. Add a convoluted circuit and yup, you can be running that slow. I'd first seek to understand your required functionality. Next I'd be looking for high fan out signals and address that potential problem. I'd also attempt to pipeline the process. Either way, it seems that an architectural solution is indicated. FWIW, Getting onto and off of an FPGA is the slowest thing you can do. We try to register everything on and off of our designs where possible. Best wishes. Let me know if I may be of further assistance. -- Ed McCauley Bottom Line Technologies Inc. Specializing Exclusively in Xilinx Design, Development and Training Voice: (500) 447-FPGA, (908) 996-0817 FAX: (908) 996-0817 Ries Gilles wrote: > > Hi ! > > I've just made a circuit with an Xilinx XC4044XL. > > I was amazed that 85% of the critical path delay was due to the routing > delay. Can it be considered correct, or did something go wrong in the > placement/routing ? > > In my case, I had 11 levels of logic, between a pad and a FF, and 20 ns > of logic, and 135 ns of Routing delay. I used the highest optimisation > effort possible with enough iteration. > > Thanks. > > Gilles.Article: 10330
If you wish to instantiate a LogiBlox component, create the component, and use the instantiation template to write the port map. Make sure the .ngo file from Logiblox is in the project directory, or tell M1 where to find it. ngdbuild will merge the netlists together. The libraries you found are in $XILINX/vhdl/src/logiblox are not synthesis libraries, but are Unisim behavioral simulation libraries. These are to be used for pre-M1 simulation. You do not need to make any special library callouts, just instantiate the component and make the netlist available to ngdbuild. Ed McCauley wrote: > > Simply inferring your 19 bit adder should cause Express to create a > Logiblox element in the netlist. You should have a timing constraint on > the counter as well. Check the logfile output to verify LogiBlox > activity. > > Feel free to contact me if this doesn't seem to work for you. > > -- > Ed McCauley > Bottom Line Technologies Inc. > Specializing Exclusively in Xilinx Design, Development and Training > Voice: (500) 447-FPGA, (908) 996-0817 > FAX: (908) 996-0817 > > Vo To wrote: > > > > Hi, > > > > One of the requirements of my FPGA design is to have a fast 19-bit > > adder. > > > > How do I instantiate or infer a fast carry-logic adder in FPGA Express? > > I read the XSI Design Guide, it said to use LogiBlox components. > > However, inside FPGA Express, I can't use the Logiblox library. For > > example: > > > > LIBRARY logiblox; > > USE logiblox.mvlutil.ALL; > > USE logiblox.mvlarith.ALL; > > USE logiblox.logiblox.ALL; > > > > gives me errors that it's not recognizing the library. > > > > Thanks in advance. -- ************************************************************ * Randy Robinson Field Applications Engineer * * Xilinx, Inc. Longmont, Colorado * * office (303) 774-1175 fax (303) 774-1198 * * mailto:randy.robinson@xilinx.com * * * * Technical hotline - (800) 255-7778 * * World Wide Web - http://www.xilinx.com * * Solutions - http://www.xilinx.com/support/searchtd.htm * ************************************************************Article: 10331
What I was able to do was power up the computer and let it boot without reconizing my PCI card. Then I downloaded the configuration with the Xilinx download cable. I would then do a reset without powering off the the PC and the boot sequence would then reconize my card. In production I was able to issue retries to the host until the FPGA was configured. (I was using a PCI bridge chip with an FPGA.) George Fang wrote: > Hi, > PCI and CardBus devices are detected at system boot-up. This is > going to be a problem when a FPGA is used as the PCI/CardBus controller > during development. > The FPGA configuration data downloading program can only be > available after the system is fully up, but without a configured FPGA > the device under development is not going to be detected. > Does anyone have a good solution for this? Is there a way to > re-invoke the device detecting process after the FPGA is configured? > Thanks in advance for any information in this regard. > > George. -- Arnie Buck Principal Hardware Engineer WaveMark Technologies, Inc. 70 Blanchard Rd. Burlington, MA 01803 phone: 781-270-7098 (Then, dial 1-234) fax: 781-270-0193Article: 10332
Hello! My name is Amy Bharucha and I am a recruiter at SUN. I apologize if this message is considered inappropriate by any members of the alias ... but I am staffing the CAD and other organizations at SUN and facing a few challenges! If you would be interested in opportunities at SUN, or have colleagues who may be interested please examine this posting. We have multiple openings within the SPARC organization in our microelectronics division. We are looking for: **Library Flow Engineer** Create and maintain CAD flow to provide seamless, automated verification of cells and datapath libraries. Requires 6+ years of experience in Shell, Perl programming, OPUS/EDGE and library flow. **CAD Support Engineer** Develop methodology for architectural, behavioural and gate-level design using Verilog, SYnopsys and/or Cadence/OPUS. **CAD Engineer** Using UNIX, C, C++ shell and perl within a small team for implementing and supporting various circuit analysis tools geared toward design verification of static and dynamic CMOS sircuits. **Software MTS** Design, port, develop debug and/or document system initialization, fcode drivers utilities and diagnostic program for high-performance SPARC based system board and its I/O subsystems. Write firmware programs for the HW functions including CPU, cache memory management etc. **Staff HW Engineer** 8+ years of experience in design of the high-speed computer systems. RISC architectures. PCI and/or Compact PCI highly desirable. Manage outside development of UltraSPARC IIi based CompactPCI board. **Program Manager** Cultivate support by 3rd party developers of PCI, PMC and Compact-PCI I/O cards for SUN products. **CAD Manager** Responsible for the Physical CAD tools and flows for high performance SPARC processor families. Work with design groups to tailor the EDA point tools as well as develop selected tools in the physical design space including place and route, timing, parasitic extraction, physical design verification and signal integrity analysis. **CAD Engineer** Develop and support a wide variety of CAD software tools, primarily for the "front-end" IC CAD. Net-listing, net-list related design modification/editions ERC. Broad CAD programming experience and familiarity with IC design methodologies. **Staff Engineer** DFT for the UltraSPARC. Scan testing, DFT, ATPG JTAG and BIST, verilog circuit and logic design required. VLSI test equipment, memory test, failure analysis RISC CPU design and script programming. Please respond to AMY BHARUCHA amy.bharucha@eng.sun.com 408 328 8852 phone 408 328 8812 fax Thank you for your time!!Article: 10333
Try AMD's tech support on the web. http://www.amd.com/support/support.html Vito Veneziani ( vitosim_at_tin.it ) wrote in message <3555f10e.5256808@news.tin.it>... >Is there anybody who can send me ( or tell me where to find ) the >programming algorithms for PALCE22v10 / GAL22v10 devices ? > >Thanks. >Vito VenezianiArticle: 10334
Steven K. Knapp (sknapp@optimagic.com) wrote: : Does anybody know where I might find an Ultra 2 SCSI core? I'm primarily : interested in Slave operations. Verilog is preferred but will take what I : can get. : ----------------------------------------------------------- : Steven K. Knapp : OptiMagic, Inc. -- "Great Designs Happen 'OptiMagic'-ally" : E-mail: sknapp@optimagic.com : Web: http://www.optimagic.com : ----------------------------------------------------------- Contact Symbios in Ft Collins, CO. I believe they have this core as part of their IP offerings. Of course you'll have to book the fabing with them. Chuck Shinn Hewelett Packard Boise, IdahoArticle: 10335
George Fang wrote: > > Hi, > PCI and CardBus devices are detected at system boot-up. This is > going to be a problem when a FPGA is used as the PCI/CardBus controller > during development. > The FPGA configuration data downloading program can only be > available after the system is fully up, but without a configured FPGA > the device under development is not going to be detected. > Does anyone have a good solution for this? Is there a way to > re-invoke the device detecting process after the FPGA is configured? > Thanks in advance for any information in this regard. > > George. George, If the only thing your interested in is development environment, and not the released product, and are using Windows 95 (Ver 1 or 2, but this doesn't work in 98) then you can try this. It works for us. 1) Open the Control Panel 2) Select "System" 3) Select Device Manager tab 4) With Computer hilighted (default) click Properties. 5) NOW, put in your Cardbus card, and it will be powered up, it will be visible in the PCI device list, but Windows will not yet examine its Configuration space. This will only happen when you Cancel out of viewing the Computer Properties screen (#4 above). You obviously cannot use this for bootup insertions, but it at least allows you time for the FPGA to power up. I suspect that the Configuration Manager is not in a state to update the machine while you're examining the properties, but is when you exit the Properties screen. Chris WielandArticle: 10336
In article <01bd7d82$cbde35c0$56cbaf8b@john>, "John Huang" <hungi@tpts4.seed.net.tw> writes... >Hi: > I 've a problem with my design , could anyone can tell me that >3.3V and 5V chip has any differents? > My current design using altera 10K20-3, it's 5V I/O chip, but >its speed is too slow that does not suit my timing, I've contact the >sales of altera, he tell me the -3 is the fastest chip of 10K20, If >I want a faster chip, they have 10K70 for -1, but it is 3.3V, but >my board's I/Os are connect to 5V chip, I wonder if they can't >work fine, can I replace 10K20 for 5V to 10K70 for 3.3V directly >? According to the Altera web site, the fastest version of the 10K70 is the -2 version and it is a 5V part. The larger device will have more interconnect delay so it may not be any faster than the 10K20-3. I would recommend looking at the 10K30A -1 or -2 parts (3.3V but 5V I/O compliant). Daniel Lang dbl@hydra0.caltech.eduArticle: 10337
In article <35580dff.85958704@news.dial.pipex.com>,
ems <ems@see_sig.com> wrote:
>there is, in principle, one possible workaround, which was discussed
>in comp.os.ms-windows.programmer.vxd a few months ago (look up "Help
>Allocating Physical Memory with PNP PCI Board" in dejanews). this
>involved adding some 'minimal' external circuitry which latches the
>address of configuration writes. this has a number of potential
>problems, and my own opinion was that you'd have to have a *very* good
>reason to try it.
Yeah, I'm the guy who tried it. The circuit is four chips: a 74ACT273
(8-bit D-FF), a 74ACT175 (4 bit D-FF with both inverted and true outputs), a
74F30 (8-input NAND) and a 74ACT378 (6 bit D-FF with clock enable). The
circuit is:
DIN = ( ENABLE ? AD2@CLK : DIN )@CLK ;
CCLK = ( ENABLE ? AD3@CLK : CCLK )@CLK ;
NPROG= ( ENABLE ? AD4@CLK : NPROG )@CLK ;
ENABLE= AD6@CLK & IDSEL@CLK & NBE0@CLK & NBE1@CLK & ~(NBE2@CLK) &
NBE3@CLK & ~(NFRAME@CLK) & NFRAME@CLK@CLK ;
'@' is a D-FF, as in: Q=D@CLK
'?:' is a 2:1 MUX, as in: F=S?A:B
a clock enable flip flop (I.E., the 74ACT378) then is: Q=(EN?D:Q)@CLK
With surface mount devices this is not too bad, but if you can think of some
way of making it smaller, let me know :-)
It decodes configuration writes such that the addresses 64-95 appear as
different patterns on DIN, CCLK, and NPROG. Note that the configuration
write cycle never completes (it times out), but the address does get
through.
When the device driver is run the first time after being installed, it has
to write the FPGA bitstream to all slots which don't appear to have a card
(try the local slots first, then bus extender slots; etc.). With a 4013E,
this process can take quite a long time. If the card's PCI configuration
registers appear in a slot after the bitstream has been written to it, the
card has been found. The software then has to save the slot number in a
.INI file or in the registry so that the next time the machine is rebooted,
the process doesn't take so long (unless the card doesn't appear because the
user moved it, in which case you have to try all the slots again).
The circuit has to be seperated from the PCI bus with 100-ohm series
resistors on each signal (placed close to where the PCI bus routes to the
FPGA), so as to try to not violate the load limit.
Once you have found the PCI card, you have to set its base registers. This
sounds dangerous but in practice it's easy to find empty address space above
the RAM and below the lowest-addressed PCI card. I think eventually that
the card services will get a reconfiguration system call, since
there already is a hot-insertion PCI standard.
This whole scheme works fine, but has the problem that if other people use
it with the same FPGA connected to the PCI bus in exactly the same way, you
run in to the possibility of recognizing the wrong card. I think we FPGA
PCI people should make up some sort of a standard to prevent this (perhaps
by having the above circuit only respond if you have loaded the correct PCI
vendor ID into a shift register or something), but everyone on both the FPGA
group and the VXD group thinks this is just a crazy hack. Which of course
it is :-)
The serial prom solution with FPGAs is not perfect either: the PCI standard
gives you only like 1ms after power up for the card to be ready to use.
This will be a problem on machines with no memory test.
--
/* jhallen@world.std.com (192.74.137.5) */ /* Joseph H. Allen */
int a[1817];main(z,p,q,r){for(p=80;q+p-80;p-=2*a[p])for(z=9;z--;)q=3&(r=time(0)
+r*57)/7,q=q?q-1?q-2?1-p%79?-1:0:p%79-77?1:0:p<1659?79:0:p>158?-79:0,q?!a[p+q*2
]?a[p+=a[p+=q]=q]=q:0:0;for(;q++-1817;)printf(q%79?"%c":"%c\n"," #"[!a[q-1]]);}
Article: 10338Hi, Looking for good info about the Texas Instruments TMS320C6x DSPs? Please check out my website: http://www.scs.ch/~andrew/c6x.html Here you'll find: - latest documentation and silicon availability info. - heaps of stuff about HW and SW design with these DSPs - application notes - comprehensive bug list - commercially available 'C6x processor boards and lots of other stuff ..... Have a look and please send me any comments. Don't forget to join my mailing list if you want to be notified when the site is updated ... Cheers, Andrew Phillips Supercomputing Systems AG Zurich, SwitzerlandArticle: 10339
Hi, I've tried the BUFGS component in my VHDL sourcecode and it worked very well. Thank you very much!!! M.Schmid APS wrote: > You have to be careful with this. The following example should work for > inserting GLOBAL buffers in the XILINX and other VHDL compilers. I remember > however that Exemplar had a problem with the buffers not actualling > instantiating (which they subsequently fixed) in XILINX parts. > > One problem you may have in the XVHDL metamor compiler is that it > automatically inserts global buffers where it feels they are needed.This can > be a nice feature unless you have already placed the pins. If the clock > driving those pins are not attached to the correct FPGA pins (primary or > secondary global clock FPGA pins) you get an error when you go to place and > route the part. The answer is to turn off the automatic insertion of the > global buffers and to insert them yourself. Turning off the automatic > insertion is done in an argument file in the XVHDL compiler. A detailed tech > note describing exactly how to do this is described in the X84 tech note > section of our website http://www.associatedpro.com in particular at > http://www.associatedpro.com/x84/support/x84_sup.html , > > If you are using the Accolade PeakFPGA version of the Metamor compiler you can > turn off the automatic insertion from the windows interface. > > The following code is an example using the APS-X84 board. A global buffer > component -BUFGS- (done once) is created and in this case is instantiated > three times to create three distinct buffers. This same procedure should work > for any VHDL compiler. > > If you have an X84 board there is C code available which will control the > board and exersize the VHDL code example provided. If you don't have one, get > one (-: , they are low cost, and are excellent for implementing and solving > problems just like this one (-: > The X84 boards come with labs and VHDL examples on CD which really save you > tons of time. It also comes with the Accolade PeakVHDL simulator and PeakFPGA > compiler in usable demo format. > (see http://www.associatedpro.com/x84/prod/x84_ds.html ) > > Also check out our VHDL free on line lab and our free newsletter which can be > subscribed to. They all provide tips and hints on using FPGAs and VHDL in > particular. > > The following code shows the use of a secondary Global buffer in VHDL > (among other things) > > -------------------------------------------------------------------------- > -------------------------------------------------------------------------- > -- Associated Professional Systems, Inc. > -- 3003 Latrobe Court, Abingdon, MD 21009 > -------------------------------------------------------------------------- > -- > -- Project: Example VHDL file for APS X-84 Board > -- 2 number SORT > -- Date: 23 November 97 > -- Author: Richard Schwarz > -- Title: APS-X84 READ WRITE sort > -- > -- Description: > -- > -- > -- > -- Contents: > --- > -- Generics: > -- > -- Version: 1.0 > -- > -- Revision History: > -------------------- > -- Rev: > -- Date: > -- Author: > -- Description: > -- > -- > -------------------------------------------------------------------------- > -------------------------------------------------------------------------- > > library IEEE; > use IEEE.std_logic_1164.all; > > library METAMOR; > use METAMOR.attributes.all; > > library SYNOPSYS; > use SYNOPSYS.std_logic_arith.all; > use SYNOPSYS.std_logic_unsigned.all; > > ENTITY X84RD_WR IS > > PORT > ( > WRin: IN std_logic; > RDin: IN std_logic; > LED: OUT std_logic; > CLKin: IN std_logic; > --eight bit IO bus > DataBus: INOUT std_logic_vector(7 downto 0) > ); > > attribute pinnum of DataBus : signal is "P10,P9,P8,P7,P6,P5,P4,P3"; > attribute pinnum of WRin : signal is "P17"; > attribute pinnum of RDin : signal is "P18"; > attribute pinnum of LED : signal is "P35"; > attribute pinnum of CLKin : signal is "P13"; > > END X84RD_WR; > ---------------------------------------------------------------- > ---------------------------------------------------------------- > ARCHITECTURE behave OF X84RD_WR IS > > -- Data Storage Registers > signal IOByte_0 : STD_LOGIC_VECTOR(7 downto 0); > signal IOByte_1 : STD_LOGIC_VECTOR(7 downto 0); > signal BigNum : STD_LOGIC_VECTOR(7 downto 0); > signal LitNum : STD_LOGIC_VECTOR(7 downto 0); > > signal TempDataBus : STD_LOGIC_VECTOR(7 downto 0); > signal cnt : INTEGER range 1 downto 0; > signal rd, wr, clk : STD_LOGIC; > > component BUFGS > port (I: in std_logic; > O: out std_logic); > end component; > > BEGIN > > WRBUF: BUFGS port map (I => WRin, O => WR); > RDBUF: BUFGS port map (I => RDin, O => RD); > CLKBUF: BUFGS port map (I=> CLKin, O=> CLK); > > LED <= '1' when IOByte_0 > IOByte_1 else '0'; --is last number larger > > DataBus <= TempDataBus when RD = '1' else "ZZZZZZZZ"; > > -- DO IO > WRITE: PROCESS(WR,RD) > BEGIN > > if (WR'EVENT AND WR = '1') then > IOByte_1 <= IOByte_0; > IOByte_0 <= DataBus; > Cnt <= 0; > end if; > > if (RD'EVENT AND RD = '1') then > if cnt = 0 then > > TempDataBus <= LitNum; > cnt <= cnt +1; > else > TempDataBus <= BigNum; > end if; > end if; > > END PROCESS; > > --Do computations with clock > > Compute: PROCESS(CLK) > BEGIN > if IOByte_0 > IOByte_1 then > BigNum <= IOByte_0; > LitNum <= IOByte_1; > else > BigNum <= IOByte_1; > LitNum <= IOByte_0; > end if; > END PROCESS; > > END behave; > > Rickman wrote: > > > Michael Schmid wrote: > > > Hi, > > > > > > I'm working with Xilinx XACT-M1.3. I wrote my design in VHDL. > > > Now I have the same problem with a XC4013XL chip. Because of not using > > > the global clock buffers I have enormous clock skew. > > > > > > So I've tried to use the BUFGS. I've clicked the "generic clock buffers" > > > button in the options-menu of XACT-M1. But after implementation the > > > buffers are not used. > > > > > > Now my question: > > > How can I use the BUFGS in VHDL ? > > > > -- > > I have never done an entirely VHDL design. I use schematics at the top > > level to link everything together. My suggestion would be to add a top > > level schematic where you can manually place a BUFGS on the clock input. > > > > If you don't want to use a schematic, why not try giving Xilinx a call > > at 800-624-4782? What are you using for the front end? Are you using > > Foundation, or are you using one of the third party vendors? If you > > don't have support, let me know and I will give them a call about this. > > > > Rick Collins > > > > rickman@XYwriteme.com > > > > remove the XY to email me. > > -- > __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ > > Richard Schwarz, President EDA & Engineering Tools > Associated Professional Systems (APS) http://www.associatedpro.com > 3003 Latrobe Court richard@associatedpro.com > Abingdon, Maryland 21009 > Phone: 410.569.5897 Fax:410.661.2760 > > __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ > > Michael Schmid wrote: > > > Rickman wrote: > > > > > > Vo To wrote: > > > > > > > > Hello, > > > > > > > > I'm using the Xilinx Foundation Series software to implement my FPGA > > > > design. One of the biggest problem with my design are frequent hold time > > > > errors (running at 25 Mhz, clock cycle = 40 ns) reported during timing > > > > simulation. > > > > > > > > If I reduce the clock to 12.5 Mhz, the hold time errors disappear and > > > > the signals are valid and my state machine works fine. > > > > > > > > Are the hold time errors caused from assigning too wide a signal bus? > > > > For example, in a clock cycle, I need to drive 32 internal signals to > > > > the external bidirection pins. Is it too much for the XC4025E to change > > > > 32 flip-flops in 40ns? > > > > > > > > To test this out, I reduced to using 8 lines of signal. At 25 Mhz, the > > > > simulation did not report hold time errors. If I increase to 16 lines, > > > > hold time errors occurs. > > > -- > > > I don't know the particulars of your circuit, but my guess is that you > > > are not using the global clock routing. If you don't use the global > > > clock routing, as you add more FFs, the data path does not slow down, > > > but your clock routing does. This will have the data from the previous > > > stage changing from the current clock edge, before the clock reaches the > > > next stage. > > > > > > To fix this, you need to bring the clock onto the chip through a BUFGS > > > rather than an IBUF. Change this buffer and your hold time violation > > > should go away. BTW, you should never get a hold time violation in any > > > FPGA. This is caused by your data delay being too SHORT, which is > > > something that should never happen. If your data path delay is too LONG, > > > you will get setup time violations. > > > > > > Rick Collins > > > > > > rickman@XYwriteme.com > > > > > > remove the XY to email me. > > -- > > > > Hi, > > > > I'm working with Xilinx XACT-M1.3. I wrote my design in VHDL. > > Now I have the same problem with a XC4013XL chip. Because of not using > > the global clock buffers I have enormous clock skew. > > > > So I've tried to use the BUFGS. I've clicked the "generic clock buffers" > > button in the options-menu of XACT-M1. But after implementation the > > buffers are not used. > > > > Now my question: > > How can I use the BUFGS in VHDL ? > > -- > __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ > > Richard Schwarz, President EDA & Engineering Tools > Associated Professional Systems (APS) http://www.associatedpro.com > 3003 Latrobe Court richard@associatedpro.com > Abingdon, Maryland 21009 > Phone: 410.569.5897 Fax:410.661.2760 > > __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/Article: 10340
Joseph H Allen wrote: > > > Yeah, I'm the guy who tried it. The circuit is four chips: a 74ACT273 > (8-bit D-FF), a 74ACT175 (4 bit D-FF with both inverted and true outputs), a > 74F30 (8-input NAND) and a 74ACT378 (6 bit D-FF with clock enable). The > circuit is: > > DIN = ( ENABLE ? AD2@CLK : DIN )@CLK ; > CCLK = ( ENABLE ? AD3@CLK : CCLK )@CLK ; > NPROG= ( ENABLE ? AD4@CLK : NPROG )@CLK ; > ENABLE= AD6@CLK & IDSEL@CLK & NBE0@CLK & NBE1@CLK & ~(NBE2@CLK) & > NBE3@CLK & ~(NFRAME@CLK) & NFRAME@CLK@CLK ; > > '@' is a D-FF, as in: Q=D@CLK > '?:' is a 2:1 MUX, as in: F=S?A:B > a clock enable flip flop (I.E., the 74ACT378) then is: Q=(EN?D:Q)@CLK > > With surface mount devices this is not too bad, but if you can think of some > way of making it smaller, let me know :-) > A flash memory based CPLD would certainly be smaller. It can also help with downloading the FPGA while the PC is booting up. -- Free VHDL/FPGA simulator: http://www.best.com/~rod1/vhdl EPL c/o WilsonBrianLee@yahoo.com (actually, the other way around)Article: 10341
William L. Bahn wrote: > >Since DONE must go High, I assume that the configuration process itself > >works properly. > > It certainly appears to complete the configuration process - although with > one PROM program it didn't and just kept running the CCLK forever. > > >Do you have a synchronous design, using global clock(s)? Asynchronous > >designs can be very nasty. > > It is synchronous after my clock generator circuit. This is how it works: I > take an external clock and clock a 4-bit counter with it and then use a 8:1 > mux to select the original clock, one of the four divided down clocks or one > of three other external clock sources. This becomes my "master clock" which > drives a quadrature clock generator that yields a set of four clocks at half > the master clock frequency that are quadrature related. The first two of > these are fed to the GCLK and ACLK buffers. At the present level of > implementation, I am only using the GCLK output to clock the rest of the > logic - but some of the un-implemented stuff will use the ACLK or have > inverted clock inputs using either the GCLK or the ACLK. Do you see any > problem with generating by GCLK and ACLK in this fashion. > > >You can analyze a specific item, e.g. the fourth counter bit not > >toggling, in XACT, the graphics editor. It shows every internal > >connection. > > I will look into this. Can it do it using the HEX file used to program the > SPROM? That would be best. > > Thanks. -- My guess is that your problem is in the routing of the initial "master clock". From your description, you are not routing this clock via the GCLK or ACLK buffers. If your routing of this clock is not even across the various FFs which are generating the quadrature clocks, you will get faulty outputs from the FFs. If you have a GCLK or ACLK left, try using it for the "master clock". Rick Collins rickman@XYwriteme.com remove the XY to email me.Article: 10342
Joseph H Allen wrote: > > In article <35580dff.85958704@news.dial.pipex.com>, > ems <ems@see_sig.com> wrote: > > >there is, in principle, one possible workaround, which was discussed > >in comp.os.ms-windows.programmer.vxd a few months ago (look up "Help > >Allocating Physical Memory with PNP PCI Board" in dejanews). this > >involved adding some 'minimal' external circuitry which latches the > >address of configuration writes. this has a number of potential > >problems, and my own opinion was that you'd have to have a *very* good > >reason to try it. > > Yeah, I'm the guy who tried it. The circuit is four chips: a 74ACT273 > (8-bit D-FF), a 74ACT175 (4 bit D-FF with both inverted and true outputs), a > 74F30 (8-input NAND) and a 74ACT378 (6 bit D-FF with clock enable). The > circuit is: ...snip... > The serial prom solution with FPGAs is not perfect either: the PCI standard > gives you only like 1ms after power up for the card to be ready to use. > This will be a problem on machines with no memory test. > > -- > /* jhallen@world.std.com (192.74.137.5) */ /* Joseph H. Allen */ -- I thought that the PCI spec intentionally gave enough time after reset to allow for booting of slow reconfigurable logic (like the Xilinx chips). My understanding (for what it is worth) is that a device has to be able to not clobber the bus after some short time, but doen't have to respond to a command for a much longer time, like many ms. This may be an addition in the 2.1 version of the spec. But I am sure I saw this discussed on the PCI-SIG mailing list. I don't know enough to post there, but I like to lurk. Rick Collins rickman@XYwriteme.com remove the XY to email me.Article: 10343
Hi, I've just installed Foundation Express and have a question: Is it possible to use the Synopsis VHDL compiler in place of the XVHDL compiler? I would like to use the Synopsis compiler in conjunction with top-level schematic entry, such that i could include VHDL source files in my hierarchy _without_ exporting/importing. (The imported macro becomes a primitive element in the schematic) In other words I would like to set the synthesis tool in the VHDL editor to Synopsis instead of XVHDL. mvh. -- Thor Arne Johansen Ibas Laboratories, Norway http://www.ibas.noArticle: 10344
> I thought that the PCI spec intentionally gave enough time after reset > to allow for booting of slow reconfigurable logic (like the Xilinx > chips). My understanding (for what it is worth) is that a device has to > be able to not clobber the bus after some short time, but doen't have to > respond to a command for a much longer time, like many ms. This may be > an addition in the 2.1 version of the spec. But I am sure I saw this > discussed on the PCI-SIG mailing list. I don't know enough to post > there, but I like to lurk. The PCI reset spec is: Reset Active Time After Power Stable' of 1ms MIN. So 1ms is all your guaranteed For any information on PCI reset timing, see section 4.3.2, page 139+ in the PCI 2.1 spec. and table 4-5 on p. 134, section 4.2.3.2. For a Xilinx, FAST configuration can be up to 12MHz per bit, so configuration time is 83ns/bit. 1ms/83ns = 12048 bit configuration. So, a 4010 barely makes this spec, and a 4103 doesn't. The spec in the data book is actually a range of 4MHz to 10MHz for FAST, and .5MHz to 1.25MHz for slow. Doesn't look too good for any Xilinx part to make the actual PCI spec's reset time. In truth, most systems hold reset for seconds, instead of 1ms, so you really are safe, just not within spec. Austin Franklin darkroom@ix.netcom.comArticle: 10345
> The FPGA configuration data downloading program can only be > available after the system is fully up, but without a configured FPGA > the device under development is not going to be detected. The only thing the BIOS detection does is program the configuration spaces on the card, and creates a table of what resources are used indexed by device IDs. This way a driver just looks through this table and finds out what the resources for its card are. > Does anyone have a good solution for this? > Is there a way to > re-invoke the device detecting process after the FPGA is configured? Yes. Sometimes when developing a PCI FPGA I download the bit stream via the serial download cable, after the system is booted (or during boot...), as I assume you are suggesting. Then I run a program (available with many PCI extender cards, or one that we developed) to write the configuration space on the card under test. There are calls in the OS to get the boot PCI configuration information, and yes, you can add to the configuration table. You just have to know what resources are available for you to use (obviously, you can't use one that is already allocated). There is another way though if you have a second computer...notebook may be. When the development system is booting, just hit the key (usually DEL) to get it to go to the Configure BIOS screen. Then the system is 'halted' from doing the PCI configuration. Download your bit stream (using another computer), and just exit out of the BIOS configuration screen (if you made no changes, it should just continue). Depending on the BIOS and system, providing you didn't tie the RESET (or INIT on 4k) of the FPGA to the RESET of the PCI bus, you should be fine. Hope this helps. Austin Franklin darkroom@ix.netcom.comArticle: 10346
Austin Franklin wrote: > The PCI reset spec is: Reset Active Time After Power Stable' of 1ms MIN. > So 1ms is all your guaranteed ...snip... > Austin Franklin > darkroom@ix.netcom.com -- You are quoting the time that the RESET signal must be asserted. I believe there is another spec that allows a board to take some additional time after the removal of RESET before it will respond to commands on the bus. I don't know where it is in the spec, but as I said, I saw this discussed on the PCI-SIG mailing list. Rick Collins rickman@XYwriteme.com remove the XY to email me.Article: 10347
Michael Schmid <mlschmid@iis.fhg.de> wrote in article
<355321D6.47D1@iis.fhg.de>...
> Hi,
>
> I'm working with Xilinx XACT-M1.3. I wrote my design in VHDL.
> Now I have the same problem with a XC4013XL chip. Because of not
using
> the global clock buffers I have enormous clock skew.
>
> So I've tried to use the BUFGS. I've clicked the "generic clock
buffers"
> button in the options-menu of XACT-M1. But after implementation the
> buffers are not used.
>
>
> Now my question:
> How can I use the BUFGS in VHDL ?
>
Michael,
I'm using M1.4 and the Metamor synth tool. Here's what I'm using -
and it works.
entity topentity is
port (
hsysclk : in STD_LOGIC;
lreset : in STD_LOGIC;
had : inout STD_LOGIC_VECTOR (7 downto 0) ;
-- other ports ...
);
attribute Xilinx_BUFG : boolean;
attribute Xilinx_BUFG of hsysclk: signal is true;
end topentity;
This will tell the synthesis tool that hsysclk needs a BUFG. If
you're using the Aldec VHDL editor tool, simply pull down the
Synthesis | Options menu item and make sure the compile is set to
"Chip." When it compiles, the proper IPADs, OPADs and buffers will
be inserted.
Good luck!
-Andy
Article: 10348Rickman <spamgoeshere1@yahoo.com> wrote in article <3559EFFD.4975C166@yahoo.com>... > Austin Franklin wrote: > > The PCI reset spec is: Reset Active Time After Power Stable' of 1ms MIN. > > So 1ms is all your guaranteed > ...snip... > > Austin Franklin > > darkroom@ix.netcom.com > > -- > You are quoting the time that the RESET signal must be asserted. I > believe there is another spec that allows a board to take some > additional time after the removal of RESET before it will respond to > commands on the bus. I don't know where it is in the spec, but as I > said, I saw this discussed on the PCI-SIG mailing list. Nope. That does not exist in the PCI 2.1 spec. that I have found. If you can find it, page or section, then I'll stand corrected. PCI signals can commence immediately after reset is released. AustinArticle: 10349
> The circuit has to be seperated from the PCI bus with 100-ohm series > resistors on each signal (placed close to where the PCI bus routes to the > FPGA), so as to try to not violate the load limit. I don't want to belabor this with you, but I believe that violates PCI spec. If this method were acceptable, then we would not need PCI to PCI bridge chips. Austin Franklin darkroom@ix.netcom.com
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z