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Messages from 103650

Article: 103650
Subject: Re: LVTTL, LVCMOS or 3.3V-PCI?
From: "John Smith" <someone@microsoft.com>
Date: Wed, 7 Jun 2006 17:54:37 +0200
Links: << >>  << T >>  << A >>

"kia rui" <krbyxtrm@gmail.com> wrote in message
news:1149693784.310825.244290@g10g2000cwb.googlegroups.com...
> what's the difference with LVTTL, LVCMOS and 3.3V-PCI for signalling a
> PCI fpga/cpld?
> And if 3.3V-PCI is not available, what should be used as the
> replacement(LVTTL or LVCMOS)?
>
I guess LVTTL is the low voltage version of the ordinary TTL,  low current
source (none !) but high current drain.  LVTTL  comes  in 3.3 Volts an
2.5Volts, and I guess the source-drain issue goes for them as wel.

LVCMOS are the low-voltage version of the normal cmos, it has equal drain
and source current, ant thats that.

3.3V PCI- i am not sure of, but I guess LVTTL at 3.3V should do the trick  I
use LVCMOS at 2.5V level to source diodes and stuff on my board, but i guess
PCI has somewhat legacy til TTL, so I guess this is the better choise for
this interface.



Article: 103651
Subject: Re: Problems with ISE logic optimization
From: "dmos" <daniel.mosconi@gmail.com>
Date: 7 Jun 2006 08:58:29 -0700
Links: << >>  << T >>  << A >>
I've resolved the problem using LUT1 and (R)LOC constraints for direct
routing!!
Thanks a lot for the suggestions!!!

Daniel


Article: 103652
Subject: Anyone with Xilinx SP305-board ?
From: "John Smith" <someone@microsoft.com>
Date: Wed, 7 Jun 2006 18:14:00 +0200
Links: << >>  << T >>  << A >>
Seemed like a good deal, but the board was only around for purchase a few
months, so I guess there aren't to many  around ? Thats a shame, really ! It
is as far as I can tell a good board, It has a good  an powerfull FPGA;
Spartan 3-1500 and enough power to fullfill the requirements of my masters
degree.  But the board are no longer available ? I was kind'a hoping
draining knowledge from other users of this board...



Article: 103653
Subject: Re: Anyone with Xilinx SP305-board ?
From: "radarman" <jshamlet@gmail.com>
Date: 7 Jun 2006 09:35:07 -0700
Links: << >>  << T >>  << A >>
John Smith wrote:
> Seemed like a good deal, but the board was only around for purchase a few
> months, so I guess there aren't to many  around ? Thats a shame, really ! It
> is as far as I can tell a good board, It has a good  an powerfull FPGA;
> Spartan 3-1500 and enough power to fullfill the requirements of my masters
> degree.  But the board are no longer available ? I was kind'a hoping
> draining knowledge from other users of this board...

Have you tried searching on the Xilinx website. I was able to find:

http://www.xilinx.com/products/boards/sp305/reference_designs.htm
http://www.xilinx.com/xlnx/xebiz/designResources/ip_product_details.jsp?key=HW-SP305-US&sGlobalNavPick=PRODUCTS&sSecondaryNavPick=BOARDS

Between the two, there are reference designs (with working UCF files),
schematics, and a user guide.

-Seth


Article: 103654
Subject: Re: FlipChip BGA Conformal Coating
From: fpga_toys@yahoo.com
Date: 7 Jun 2006 09:48:12 -0700
Links: << >>  << T >>  << A >>

se wrote:
> These types of packages are a serious issue in our mil systems that
> we've been working for sometime.  We have techniques that address the
> problem but keep looking for a real solution.
>
>                                                      Sam

Who is "our" and "we"?


Article: 103655
Subject: Xilinx SystemACE : Flash Memory
From: Henry <hhu@calpoly.edu>
Date: Wed, 7 Jun 2006 10:34:11 -0700
Links: << >>  << T >>  << A >>
Does the Flash memory unit connected to the SystemACE SC have to be from AMD? Or can another pin compatible device be used?

Does the SystemACE SC controller check the Flash Memory's ID code to make sure that the flash memory is from AMD?

Article: 103656
Subject: Incrmental Compilation in Quartus 5.1
From: "jjlindula@hotmail.com" <jjlindula@hotmail.com>
Date: 7 Jun 2006 10:53:37 -0700
Links: << >>  << T >>  << A >>
Hello, my co-worker has a very large Altera Quartus 5.1 design that
takes about 45 minutes to compile. The project has already had the pins
physically assigned and he is still adding things to the project such
as updated modules. I mentioned to him that trying Incremental
Compilation (IC) might decrease compilation time. He asked if you could
do IC after the I/O pin symbols have been physically assigned to pins?
I'm not an expert on IC so I hope someone can help.

Thanks,
joe


Article: 103657
Subject: Re: Anyone with Xilinx SP305-board ?
From: "John Adair" <g1@enterpoint.co.uk>
Date: 7 Jun 2006 12:29:29 -0700
Links: << >>  << T >>  << A >>
John

What are your requirements for a board? We can match the XC3S1500 on a
number of our products just a question of what else you want on board.
Have a look at our University Access program for discounts etc. Click
the big green square on top right of our root page for details or
directly at http://www.enterpoint.co.uk/uap/uap.html.

John Adair
Enterpoint Ltd.


John Smith wrote:
> Seemed like a good deal, but the board was only around for purchase a few
> months, so I guess there aren't to many  around ? Thats a shame, really ! It
> is as far as I can tell a good board, It has a good  an powerfull FPGA;
> Spartan 3-1500 and enough power to fullfill the requirements of my masters
> degree.  But the board are no longer available ? I was kind'a hoping
> draining knowledge from other users of this board...


Article: 103658
Subject: Re: Problems with ISE logic optimization
From: Kolja Sulimma <news@sulimma.de>
Date: Wed, 07 Jun 2006 21:31:26 +0200
Links: << >>  << T >>  << A >>
dmos wrote:
> Hello, I'm trying to implement a simple delay line for a 1MHz clock
> with an even number of inverter cells but the Synthetizer/Mapper
> doesn't work!! I think the logic optimizer is simplifying my even
> inverter cells in a short circuit...
> Wich kind of options can I use for the Xilinx tools?
> I'm using ISE7.1 and ISE8.1 with a Spartan3 device.
> How can I implement a simple delay line with about 500ps of delay in a
> FPGA?

This is exactly what the synthesizer is supposed to do.
You need to instantiate hard macros. You can generate the macros using the FPGA editor and
than instantiate them as black boxes in your HDL.
As most of the delay in an FPGA is in the routing you also need to manually place the macros.
Probably the least sensitive delay in an FPGA is the carry logic. It is a lot faster than
500ps but this allows you to calibrate your delay in approximate 50ps steps.
Just have a reference line that measures how far a signal can go in one clock cycle and based
on that measurement decide, where you want to tap your delay line.

See this paper for an example:
http://www-ppd.fnal.gov/EEDOffice-W/Projects/ckm/comadc/tdc1s.pdf

There is also a paper about people who calibrated an FPGA delay line by modulating the power supply
but I can not find it at the moment.

On the other hand: Why not buy a commercial TDC?
http://www.cronologic.de/products/time_measurement/hptdc/

Kolja Sulimma

Article: 103659
Subject: Can ILMB and DLMB of Microblaze be 24kByte?
From: "Dale" <dale.prather@gmail.com>
Date: 7 Jun 2006 12:34:13 -0700
Links: << >>  << T >>  << A >>
Hello,

I'm trying to get my ILMB and DLMB of my microblaze to be 24kBytes, but
I am only given an option of powers of two.  Is there any way around
this?

Thanks,
Dale


Article: 103660
Subject: Re: Easily add 4 Gb/s Ethernet link to FPGA systems for control & data transfer
From: weingart@cs.ualberta.ca (Tobias Weingartner)
Date: Wed, 7 Jun 2006 19:35:57 +0000 (UTC)
Links: << >>  << T >>  << A >>
In article <zEChg.112004$dW3.2334@newssvr21.news.prodigy.com>, James Ma wrote:
> 
> Add 4 Gb/s Ethernet links to FPGA systems easily & at low cost.

Your price-point is somewhat above the hobbiest range...

> High bandwidth, low latency  control & data transfers.
> Low gate count & low pin count.

It does look interesting.  :)


> Connection through standard switches or direct to PCs.
> Simple & easy. No driver programming.

These words always bring fear into my heart...  Thanks for pointing
out the 1GbE phy part for me though... been trying to find one for
some time.

-- 
 [100~Plax]sb16i0A2172656B63616820636420726568746F6E61207473754A[dZ1!=b]salax

Article: 103661
Subject: Re: Who's dying?
From: Jim Granville <no.spam@designtools.co.nz>
Date: Thu, 08 Jun 2006 07:47:23 +1200
Links: << >>  << T >>  << A >>
Austin Lesea wrote:
>>I was wondering why the Altera results differed in two areas, but
>>Xilinx's did not. Did the report not clarify that, or was it a typo ?
> 
> 
> Not sure what you are referring to.  One thing is that Hardcopy is
> including in those Altera numbers, and we don't see Hardcopy as anything
> but an ASIC, so it makes it hard to compare how the programmable logic
> sector is doing (is Altera falling more rapidly behind in FPGAs?).

#Looking at PLDs alone (no surprises here):
#Xilinx up 3.7% with 50.3%
#Altera up 7.6% with 33.1%
#Which makes these 5 with 96.8% of a $3.17 billion market
#So, what happens when you combine the Logic ASIC with the PLD markets,
#and look at them together?
#Xilinx up 3.7% with 10.5%
#Altera up 10.6% with 7.2%
#A combined 45.7% of the total market, which accounts for $7.13 billion.

In both blocks, Xilinx is +3.7%, but in one Altera is +7.6%, and the 
other +10.6%, so that was what caught my eye.

The 'second Altera' seems to be slightly larger, which may be tbe $45M
hardcopy you mentioned, included in that block, but not in the first ?

-jg




Article: 103662
Subject: Re: FPGA board for USB experiments?
From: langwadt@ieee.org
Date: 7 Jun 2006 13:18:42 -0700
Links: << >>  << T >>  << A >>

Rich Grise wrote:
> On Tue, 06 Jun 2006 14:02:18 -0700, langwadt wrote:
>
> >
> > Dave Farrance skrev:
> >
> >> Uwe Bonnes <bon@hertz.ikp.physik.tu-darmstadt.de> wrote:
> >>
> >> >In comp.arch.fpga Dave Farrance <DaveFarrance@omitthisyahooandthis.co.uk> wrote:
> >> >> I'll use another USB port for that, and I'll put together a transceiver
> >> >> board to handle the signal-levels so that I can route the raw data
> >> >> stream directly to the FPGA I/O. Such a USB interface would be
> >> >> speed-limited, but I'm not worried about that.
> >> >
> >> >The interface is not only speed limited, but also missing needed
> >> >functionality, at least for USB2. USB+ and USB- need to be evaluated in many
> >> >ways, not possible with a normal FPGA input. There are chips implementing the
> >> >physical access (UTMI).
> >>
> >> Thanks. I see. If I built an transceiver board myself, it'd have to be
> >> for USB 1.1 with a basic transceiver chip such as the MAX3346E which
> >> I'd run at low speed. I have managed to solder 14-pin TSSOP packages to
> >> prototype boards in the past, although I'd rather find a DIP chip if I
> >> could.
> >>
> >> --
> >> Dave Farrance
> >
> >
> > If it is a just for fun hack kinda thing you don't need a transciever.
> > I've implemented the
> > opencores usb core in an FPGA using just two normal IOs and a pullup
> > connected
> > to a usb connector and a little fpga logic to simultate the phy.
> > got as far as getting plugged and enumerated on windows, never used it
> > for anything though
> >
>
>
> Got VHDL?
>
> Thanks!
> Rich


Nope Verilog ;)

can't find it at the moment but was something like this at the top
level.

inout Dplus;   // pin connected to USB D+
inout Dminus;  // pin connected to USB D-

wire txdp; // Dplus  data (from usb_phy)
wire txdn; // Dminus data (from usb_phy)
wire txoe; // output enable for Dplus/Dminus  (from usb_phy)
wire rxd ; // data from differential receiver (to usb_phy)
wire rxdp; // data from Dplus  (to usb_phy)
wire rxdn; // data from Dminus (to usb_phy)

assign Dplus  = (txoe ? txdp : 1'bz);
assign Dminus = (txoe ? txdn : 1'bz);

assign rxdp = Dplus;
assign rxdn = Dminus;

assign rxd  = Dplus; // no differential receiver, so just use Dplus and
hope

-Lasse


Article: 103663
Subject: Re: Who's dying?
From: Austin Lesea <austin@xilinx.com>
Date: Wed, 07 Jun 2006 13:24:52 -0700
Links: << >>  << T >>  << A >>
Jim,

Could be (where is Hardcopy included/not?).  I used company reports for
the second posting, and an independent market firm's results for the
first posting.

I am pretty sure the marketing firm has all of Altera's revenues under
PLD (including Hardcopy).  The yearly report clearly states Hardcopy as
4% in 2005.

It is pretty picky of us to not include it (exclude from all
comparisons), but we do so to call attention to the volume of business
that they do, that detracts from their mindshare in FPGAs.  It is as if
they also make buggy whips.  Who cares how much money they make on buggy
whips.  They state in their yearly report, that Hardcopy could/might
become 10% or more of their business.  Given that LSI bailed, and had
$145 million, that might be too low an estimate.  If Altera gained all
LSI business, that would be almost $200 million for structured ASICs in
their basket.

No small number, but from our experience with Hardwire 1,2, 3 etc. that
business is a huge distraction, with poor to non-existent margins.

It does offer customers a path for cost reduction, and its primary value
is in the fact that most customers can't stop changing things, so they
must stick with FPGAs far longer than they wanted to.  Or, they can't
make the Hardcopy work, so they have to use the FPGA for much longer
than they wanted to.  Timing closure is still the number one problem
with any "hardened" approach.

However, when the hardened version doesn't work, the customer usually
demands a price concession on the FPGA until it does work.  Such
'difficult conversations' are conducted on an adversarial basis with
customers and generate negative "goodwill" and are never good for a
company.  I'd rather not be in a business where I have to get tough with
a customer to stay in business!  Once burned, they tend to go away, forever.

I'd rather not deal with a manufacturer that has tough guys used to very
angry yelling and screaming customers that I must negotiate with...

I am surprised that no one pointed out how good 2001 was and how bad
2002 was.  The dot-com bust really burst many bubbles.  Again, for
really good comparisons, you might want to go all the way back to 1985.

Austin

Article: 103664
Subject: Xilinx EDK: Connecting interrupt to MicroBlaze requires stdout?
From: "Garrick" <garrickk@gmail.com>
Date: 7 Jun 2006 13:38:08 -0700
Links: << >>  << T >>  << A >>
Hi, I'm beginning my development with Microblaze (EDK 8.1.02i).  I
don't currently had a debug module attached to my system and am
designing for a custom board currently.  I've run into one snag that I
can't find the origin of.

My system is setup as a simple sub module exported to ISE for
compilation with only one user designed peripheral which is working
well.  I've developed C code for it and have even setup simulation in
ModelSim.  Good start.  Since I have no debug module, my "stdout" and
"stdin" settings under "Software Platform Settings" are both currently
"none."  Clearly, I don't use printf.

Now, with my C code unchanged, I can compile my .elf file, import from
ISE the .bit file, update my bit stream, and everything is great.
However, if I simply connect a previously unconnected signal on my (or
any) peripheral to the INTERRUPT input to the microblaze_0 IP, I get
the following errors when compiling my software project:

/cygdrive/c/Installed/EDK/gnu/microblaze/nt/bin/../lib/gcc/microblaze/3.4.1/../../../../microblaze/bin/ld.real:
region ilmb_cntlr_dlmb_cntlr is full (TestApp/executable.elf section
bss_stack)
./microblaze_0/lib//libc.a(xil_printf.o): In function `outnum':
xil_printf.o(.text+0x19c): undefined reference to `outbyte'
xil_printf.o(.text+0x1c4): undefined reference to `outbyte'
xil_printf.o(.text+0x258): undefined reference to `outbyte'
./microblaze_0/lib//libc.a(xil_printf.o): In function `xil_printf':
...

Now, this appears to be a common error and I've found it in Xilinx's
Answer Solutions.  However, the "solution" is to either define your
stdout/in module (I have none to define), or remove any printf or
xil_printf statements from your code.  I have no printf statments!  My
code is as simple and short as possible at this point.

So, by simply connecting an interrupt signal in my System Assembly, I
have somehow linked in code containing a printf?  Perhaps some debug
feature of the interrupt IP?  I've searched and searched and can't find
where this happens.

I've also turned off "Generate Debug Symbols" in the compiler options
within the EDK for the software project and tried to compile.  Same
error.  I've setup the project in Studio SDK and tried to compile the
code for Release and Debug executables.  I still ge the same error.

Where are the printf's coming from?  What can I do to disable their
inclusion?  Thank you, and sorry for the lengthy post.

Garrick


Article: 103665
Subject: Re: IOBDELAY's delay value
From: "Eric Crabill" <eric.crabill@xilinx.com>
Date: Wed, 7 Jun 2006 13:40:43 -0700
Links: << >>  << T >>  << A >>
Hi,

In Virtex-II, the delay buffers are either ON or OFF. There is no other
adjustment. In order to know the delay that has been introduced, you should
run a timing report on your design. I say this because the magnitude of the
delay buffers is not the same in each part -- e.g. 2v500 and 2v6000 will
report different values.

The values are necessarily different because the purpose of these delay
buffers is to add delay to eliminate positive hold times for input
flip-flops when used with global clocks and no DCM. Larger parts have larger
delay on the clock distribution, requiring larger delays for the input delay
buffers.

Hope that helps,
Eric

> if I set IOBDELAY=BOTH in virtex-II. what's the delay value in the input
path?

> It seems there is no constraint for virtex-II to set the correct delay
value.



Article: 103666
Subject: Re: IOBDELAY's delay value
From: "Peter Alfke" <peter@xilinx.com>
Date: 7 Jun 2006 14:01:34 -0700
Links: << >>  << T >>  << A >>
Virtex-4 (different from the earlier families) has a programmable
IDELAY on every input, each programmable with 64 steps, each step about
78 ps. The delay is stabilized by a PLL using a 200 MHz oscillator
input. (That's where the 78 ps come from, 5 ns divided by 64).
The 200 MHz can be changed 25 MHz up or down, and is not
jitter-sensitive, contrary to earlier warnings.
Virtex-5 then adds an equally programmable ODELAY.( Each pin can have
either an IDELAY or an ODELAY, since they share the digital delay line
between them.)
Lots of flexibility, and very nice for source-synchronous interfaces.
Peter Alfke, Xilinx

================
Eric Crabill wrote:
> Hi,
>
> In Virtex-II, the delay buffers are either ON or OFF. There is no other
> adjustment. In order to know the delay that has been introduced, you should
> run a timing report on your design. I say this because the magnitude of the
> delay buffers is not the same in each part -- e.g. 2v500 and 2v6000 will
> report different values.
>
> The values are necessarily different because the purpose of these delay
> buffers is to add delay to eliminate positive hold times for input
> flip-flops when used with global clocks and no DCM. Larger parts have larger
> delay on the clock distribution, requiring larger delays for the input delay
> buffers.
>
> Hope that helps,
> Eric
>
> > if I set IOBDELAY=BOTH in virtex-II. what's the delay value in the input
> path?
>
> > It seems there is no constraint for virtex-II to set the correct delay
> value.


Article: 103667
Subject: STOP IT :)
From: burn.sir@gmail.com
Date: 7 Jun 2006 14:22:01 -0700
Links: << >>  << T >>  << A >>
I am in no way surprised that this thread turned into a FPGA vs ASIC
and then a Xilinx vs. Altera (or Xilinx vs. the world) war. What I
don't understand is how come Jim hasn't recommenced any Lattice devices
yet ;)


Jokes aside, please stop the madness


Article: 103668
Subject: Re: IOBDELAY's delay value
From: Uwe Bonnes <bon@hertz.ikp.physik.tu-darmstadt.de>
Date: Wed, 7 Jun 2006 21:52:03 +0000 (UTC)
Links: << >>  << T >>  << A >>
Peter Alfke <peter@xilinx.com> wrote:
> Virtex-4 (different from the earlier families) has a programmable
> IDELAY on every input, each programmable with 64 steps, each step about
> 78 ps. The delay is stabilized by a PLL using a 200 MHz oscillator
> input. (That's where the 78 ps come from, 5 ns divided by 64).
> The 200 MHz can be changed 25 MHz up or down, and is not
> jitter-sensitive, contrary to earlier warnings.
> Virtex-5 then adds an equally programmable ODELAY.( Each pin can have
> either an IDELAY or an ODELAY, since they share the digital delay line
> between them.)
> Lots of flexibility, and very nice for source-synchronous interfaces.
> Peter Alfke, Xilinx

Do I understand you right that V4 contains an internal 200 MHz oscillator?

Can this oscillator be used for other more general purposes?

-- 
Uwe Bonnes                bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

Article: 103669
Subject: Re: ise8.1 picking local instead of global clk routing?
From: "Gabor" <gabor@alacron.com>
Date: 7 Jun 2006 14:55:13 -0700
Links: << >>  << T >>  << A >>

langwadt@ieee.org wrote:
> Hi,
>
> I have an old asic prototype that was initially done using ise5.1 and a
> virtex2, I'm now
> moving to a virtex4 so I've moved to ise8.1i, initially targeting
> virtex2
>
> the design has five clks only one of them is really critical with a
> fanout  of about 6000,
> ise5.1 recognized all the clks and put them on global nets.
>
> ise8.1i warns that the clk signal has non-clk connections (it does the
> clk goes to an io for a debug interface) and it cannot fit it to a clk
> template or something along those lines and puts the critical clk on
> local routing and the design fails

I would check this again.  Usually although the clock has local routing
to
the non-clock connections, global routing is used for the remaining
routes.  The warning can usually be ignored as long as you don't need
low skew on those few non-clock nodes.  Also on either virtex 2 or 4
you can use DDR output flip-flops to drive an IOB with a 1x clock
signal
without using non-clock routing (i.e. clock only needs to go to the
clock
input of the IOB, not the data path).  So if "the design fails" it may
be
due to some other issue.  Also note that both Virtex 2 and Virtex 4
have clock regions, which can become a problem with a lot of clocks
and may require some floorplanning.  If you have FPGA editor, you can
see how the clock actually got routed.

>
> is there a trick to getting ise8.1i to recognize the clock net?
> 
> regards, 
> -Lasse


Article: 103670
Subject: Re: STOP IT :)
From: Jim Granville <no.spam@designtools.co.nz>
Date: Thu, 08 Jun 2006 09:59:13 +1200
Links: << >>  << T >>  << A >>
burn.sir@gmail.com wrote:

> I am in no way surprised that this thread turned into a FPGA vs ASIC
> and then a Xilinx vs. Altera (or Xilinx vs. the world) war. 

Hmm - I don't see much of a war here  ? - have I missed something ?

Austin put some numbers out, and I queried some details of that,
but I had no real issue with the numbers themselves.

It all seemed quite civil to me ?
None of Austin's replies offended me, and I don't think I offended him ?

> What I  don't understand is how come Jim hasn't recommenced any Lattice devices
> yet ;)

and how would that be relevent, to this thread, or why should I ?

> 
> Jokes aside, please stop the madness

madness ?  - I'm sure I missed something ...

-jg



Article: 103671
Subject: Re: STOP IT :)
From: Austin Lesea <austin@xilinx.com>
Date: Wed, 07 Jun 2006 14:59:55 -0700
Links: << >>  << T >>  << A >>
burn,

OK, I will no longer post to his topic, since you object.

Austin

burn.sir@gmail.com wrote:
> I am in no way surprised that this thread turned into a FPGA vs ASIC
> and then a Xilinx vs. Altera (or Xilinx vs. the world) war. What I
> don't understand is how come Jim hasn't recommenced any Lattice devices
> yet ;)
> 
> 
> Jokes aside, please stop the madness
> 

Article: 103672
Subject: Re: Xilinx EDK: Connecting interrupt to MicroBlaze requires stdout?
From: Siva Velusamy <siva.velusamy@xilinx.com>
Date: Wed, 07 Jun 2006 15:23:25 -0700
Links: << >>  << T >>  << A >>
<snip>
> /cygdrive/c/Installed/EDK/gnu/microblaze/nt/bin/../lib/gcc/microblaze/3.4.1/../../../../microblaze/bin/ld.real:
> region ilmb_cntlr_dlmb_cntlr is full (TestApp/executable.elf section
> bss_stack)
> ./microblaze_0/lib//libc.a(xil_printf.o): In function `outnum':
> xil_printf.o(.text+0x19c): undefined reference to `outbyte'
> xil_printf.o(.text+0x1c4): undefined reference to `outbyte'
> xil_printf.o(.text+0x258): undefined reference to `outbyte'
> ./microblaze_0/lib//libc.a(xil_printf.o): In function `xil_printf':
> ...
> 
<snip>
> Where are the printf's coming from?  What can I do to disable their
> inclusion?  Thank you, and sorry for the lengthy post.
> 

Garrick - If you add -Wl,-M option to the gcc commandline, you'll get a 
map file. The initial part of it would indicate why a particular library 
was brought in. It might be helpful in resolving which library or 
function caused xil_printf to be pulled in.

-Siva

Article: 103673
Subject: Re: STOP IT :)
From: "Peter Alfke" <peter@xilinx.com>
Date: 7 Jun 2006 15:41:20 -0700
Links: << >>  << T >>  << A >>
The most offensive posting here was by burn... ,
dressing down Ron as if he were a dumb schoolboy.
Otherwise it was the usual banter...
Peter Alfke


Article: 103674
Subject: Re: IOBDELAY's delay value
From: "Peter Alfke" <peter@xilinx.com>
Date: 7 Jun 2006 15:48:00 -0700
Links: << >>  << T >>  << A >>
Uwe, wishful thinking.
The frequency must be brought in from the outside.
I am very suspicious of any claims of self-contained internal precision
ocillators, although such claims have been made. (Precision defined as
1 or 2%)
Peter Alfke, Xilinx
==============================
Uwe Bonnes wrote:
> Peter Alfke <peter@xilinx.com> wrote:
> > Virtex-4 (different from the earlier families) has a programmable
> > IDELAY on every input, each programmable with 64 steps, each step about
> > 78 ps. The delay is stabilized by a PLL using a 200 MHz oscillator
> > input. (That's where the 78 ps come from, 5 ns divided by 64).
> > The 200 MHz can be changed 25 MHz up or down, and is not
> > jitter-sensitive, contrary to earlier warnings.
> > Virtex-5 then adds an equally programmable ODELAY.( Each pin can have
> > either an IDELAY or an ODELAY, since they share the digital delay line
> > between them.)
> > Lots of flexibility, and very nice for source-synchronous interfaces.
> > Peter Alfke, Xilinx
>
> Do I understand you right that V4 contains an internal 200 MHz oscillator?
>
> Can this oscillator be used for other more general purposes?
>
> --
> Uwe Bonnes                bon@elektron.ikp.physik.tu-darmstadt.de
>
> Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
> --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------




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