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Hi, I am using the virtx-4 mini module board from Avnet to implement some designs. Howeever I am not able to compile the reference design available along with the design on Xilinx EDK 7.1i. I had an error with the opb_ddr version. I found the answe on Xilinx site and corrected the version. Inspite of that, I have an error in the system.ucf file: Applying constraints in "system.ucf" to the design... ERROR:NgdBuild:756 - Line 27 in 'system.ucf': Could not find net(s) 'ddr_sdram_32mx16/ddr_sdram_32mx16/DDR_CTRL_I/ddr_dqs_rst<*>' in the design. To suppress this error specify the correct net name or remove the constraint. ERROR:NgdBuild:756 - Line 28 in 'system.ucf': Could not find net(s) 'ddr_sdram_32mx16/ddr_sdram_32mx16/DDR_CTRL_I/ddr_dqs_setrst<*>' in the design. To suppress this error specify the correct net name or remove the constraint. ERROR:Parsers:11 - Encountered unrecognized constraint while parsing. ERROR:NgdBuild:19 - Errors found while parsing constraint file "system.ucf". Has anyone else had a similar problem?? Does anyone have a solution?? Thanks, VivekArticle: 103851
Weng Have you tried GHDL? It's a great simulator for start-up and costs nothing. http://gna.org/projects/ghdl Good luck! RichardArticle: 103852
Roger, There's been a discussion touching this topic on the SI-LIST. Search for AC coupling at http://www.freelists.org/archives/si-list/ /Mikhail "Roger" <enquiries@rwconcepts.co.uk> wrote in message news:MVgjg.29636$C83.28979@newsfe4-win.ntli.net... > Does anyone know whether the type of capacitor is important or not when AC > coupling RIO signals to/from a VII-Pro please? I've heard that certain > dielectrics are better than others but is it really that important? > > TIA, > > Roger. > >Article: 103853
Nial Stewart wrote: >> Quartus FIXEDPC $2k license covers windows modelsim >> for vhdl or verilog. >> One year limit only applies to updates -- tools keep working. > > Are you sure about that Mike, I thought they changed the licencing > model a while ago so Modelsim only works for 18 months now. I'm not 100% sure of anything. But that is what the licensing data sheet says. Anybody from Altera got their ears on? -- Mike TreselerArticle: 103854
"Weng Tianxiang" <wtxwtx@gmail.com> wrote in message news:1150137811.189733.257690@y43g2000cwc.googlegroups.com... > Hi, > We want to buy a ModelSim license. > 1. Buy Xilinx-ModelSim version license from Xilinx website shop for > $1150 with dongle and 1 year expiration limit; > 2. Buy ModelSim PE version from one of agents we contact: $3K for > perpatual license. > Both versions will work and make no differences to our applications. > Does anyone knows a better way to buy a ModelSim license with lowest > price except the above two options? For a start-up, we prefer lowest > price, of course. If you're not tied to Modelsim it might be worth looking at VHDL Simili from SymphonyEDA... http://www.symphonyeda.com/ It's a fully compliant VHDL simulator. I've been evaluating it since it came out, it's always been a bit slower than Modelsim but I see that they've put some effort into speeding it up for the latest release (I haven't tried this so can't comment). Hard to beat for the price Nial.Article: 103855
Hi, Can anyone point me to the spec. for the maximum clock frequency for the CLKDIV pin of the IDELAY block in Virtex 4? I see the IDELAYCTRL blocks need a 200MHz REFCLK, +/- 10MHz, do I need to use this for the CLKDIV pin? Ta, Syms. Inviato da X-Privat.Org - Registrazione gratuita http://www.x-privat.org/join.phpArticle: 103856
Symon,
IDELAY doesn't have a CLKDIV pin, IDELAYCTRL has nothing to do with
CLKDIV (assuming you are talking about ISERDES , CLKDIV)
IDELAYCTRL is more like a "servo loop" which calibrates the tap delay
for the delay element close to 75ps (using the 200MHz as a ref) to
compensate for voltage temperature variation.
that's why if you are going to use IDELAY element you have to
instantiate the IDELAYCTRL in the same IO bank.
as a difference in virtex5 this REF_CLK which feeds the IDELAYCRTL it
can be from 180Mhz to 220Mhz, so the delay/tap will vary. (more
flexibility for the user)
however if you were reffering to ISERDES clkdiv, then this is the serial
clock divided by the number of stages in the deserializer (for SDR) , in
other words the frequency for the paralell de-serialized data, so it's a
function of serial frequency, stages into the de-serializer and SDR/DDR.
the clk div is "fabricated" by the means of BUFR (regional buffers)
where you can setup the div factor.
Aurash
Symon wrote:
>Hi,
>Can anyone point me to the spec. for the maximum clock frequency for the
>CLKDIV pin of the IDELAY block in Virtex 4? I see the IDELAYCTRL blocks need
>a 200MHz REFCLK, +/- 10MHz, do I need to use this for the CLKDIV pin?
>Ta, Syms.
>
>
>
>Inviato da X-Privat.Org - Registrazione gratuita http://www.x-privat.org/join.php
>
>
--
__
/ /\/\ Aurelian Lazarut
\ \ / System Verification Engineer
/ / \ Xilinx Ireland
\_\/\/
phone: 353 01 4032639
fax: 353 01 4640324
Article: 103857Let me just add that this wider range of the reference clock (180 to 220 MHz) also applies to Virtex-4. The original tight specification and any warnings about jitter on that clock were overly conservative. We have run extensive tests... Peter Alfke =================== Aurelian Lazarut wrote: > > > as a difference in virtex5 this REF_CLK which feeds the IDELAYCRTL it > can be from 180Mhz to 220Mhz, so the delay/tap will vary. (more > flexibility for the user) > >Article: 103858
Aurelian Lazarut wrote:
> just rename, or move these *.v files (behavioral models) from your way,
> and make sure the edifs are into the working directory, and should work.
> Aurash
> / /\/\ Aurelian Lazarut
> \ \ / System Verification Engineer
> / / \ Xilinx Ireland
> phone: 353 01 4032639
> fax: 353 01 4640324
I am still having trouble.
I have a working directory called "exhaust." In this directory I have
the following:
xyz.v
sine_dds.edn
File xyz.v contains the following:
module xyz(CLK,WE,SCLK,WE,A,SINE);
input CLK,WE,SCLK;
input [4:0] A;
output [20:0] SINE;
sine_dds sine_new(
.DATA(DATA),
.WE(WE),
.A(A),
.CLK(CLK),
.CE(CE),
.SCLR(SCLR),
.SINE(SINE));
endmodule
When I try to synthesize xyz.v, I get the following error message:
ERROR:HDLCompilers:87 - "xyz.v" line 10 Could not find module/primitive
'sine_dds'
line 10 is "sine_dds sine_new("
I am lost, and I do not know what I am doing wrong. By the way I am
using webpack 8.1
Art
Article: 103859Symon, The Ref Clock may be supplied from any +/- 10% 200 MHz source, including the DCM CLKFX output. For example, if there is a 66 MHz clock, a M=3, D=1 will provide you with a ~ 200 MHz output on CLKFX. There is no need to be concerned with the jitter from the CLKFX, as the analog locked loop which controls the delay is effectively a PLL which filters out the high frequency jitter components (jitter on Refclk is attenuated when transfered to the data lines). It is not our intent to require a separate oscillator for this function, one should be able to make good use of the clocks that are already part of your design. Initially we did not mention use of the DCM as a source of clock for the IDELAY, as it took some time to finish the characterization of the jitter attenuation of the analog loop used. Austin Symon wrote: > Hi, > Can anyone point me to the spec. for the maximum clock frequency for the > CLKDIV pin of the IDELAY block in Virtex 4? I see the IDELAYCTRL blocks need > a 200MHz REFCLK, +/- 10MHz, do I need to use this for the CLKDIV pin? > Ta, Syms. > > > > Inviato da X-Privat.Org - Registrazione gratuita http://www.x-privat.org/join.phpArticle: 103860
Hi Aurash, Thanks for your reply! I should perhaps refine my question! Looking at a freshly downloaded UG070, the V4 user guide, Figure 7-1: ILOGIC Block Diagram, I can see a pin called CLKDIV which connects via CLKDIVINV to the block IDELAY, pin CLK. Where is the specification for the maximum frequency of this clock? BTW, I'm not using ISERDES. Thanks again, Syms. "Aurelian Lazarut" <aurash@xilinx.com> wrote in message news:e6mp3t$6j21@cliff.xsj.xilinx.com... > Symon, > > IDELAY doesn't have a CLKDIV pin, IDELAYCTRL has nothing to do with CLKDIV > (assuming you are talking about ISERDES , CLKDIV) > IDELAYCTRL is more like a "servo loop" which calibrates the tap delay for > the delay element close to 75ps (using the 200MHz as a ref) to compensate > for voltage temperature variation. > that's why if you are going to use IDELAY element you have to instantiate > the IDELAYCTRL in the same IO bank. > > as a difference in virtex5 this REF_CLK which feeds the IDELAYCRTL it can > be from 180Mhz to 220Mhz, so the delay/tap will vary. (more flexibility > for the user) > > however if you were reffering to ISERDES clkdiv, then this is the serial > clock divided by the number of stages in the deserializer (for SDR) , in > other words the frequency for the paralell de-serialized data, so it's a > function of serial frequency, stages into the de-serializer and SDR/DDR. > the clk div is "fabricated" by the means of BUFR (regional buffers) where > you can setup the div factor. > > Aurash >Article: 103861
Hi Peter, Thanks for that, that gives me a little more flexibility. Best, Syms. "Peter Alfke" <peter@xilinx.com> wrote in message news:1150218602.914281.192260@g10g2000cwb.googlegroups.com... > Let me just add that this wider range of the reference clock (180 to > 220 MHz) also applies to Virtex-4. The original tight specification and > any warnings about jitter on that clock were overly conservative. We > have run extensive tests... > Peter Alfke > =================== > Aurelian Lazarut wrote: >> > >> as a difference in virtex5 this REF_CLK which feeds the IDELAYCRTL it >> can be from 180Mhz to 220Mhz, so the delay/tap will vary. (more >> flexibility for the user) >> >> > Inviato da X-Privat.Org - Registrazione gratuita http://www.x-privat.org/join.phpArticle: 103862
Hi Austin, Thanks for that, you've confirmed what I thought the datasheet told me! But part of my question remains. Where do I find the specification for the maximum clock frequency on the IDELAY block remains? In other words, if I want to use the IDELAY block (Figure 7-11: IDELAY Primitive in UG070) in Variable delay mode (IOBDELAY_TYPE = VARIABLE), how fast can I clock it? Regards, Syms. "Austin Lesea" <austin@xilinx.com> wrote in message news:e6ms5c$lji1@xco-news.xilinx.com... > Symon, > > The Ref Clock may be supplied from any +/- 10% 200 MHz source, including > the DCM CLKFX output. For example, if there is a 66 MHz clock, a M=3, > D=1 will provide you with a ~ 200 MHz output on CLKFX. There is no need > to be concerned with the jitter from the CLKFX, as the analog locked > loop which controls the delay is effectively a PLL which filters out the > high frequency jitter components (jitter on Refclk is attenuated when > transfered to the data lines). > > It is not our intent to require a separate oscillator for this function, > one should be able to make good use of the clocks that are already part > of your design. > > Initially we did not mention use of the DCM as a source of clock for the > IDELAY, as it took some time to finish the characterization of the > jitter attenuation of the analog loop used. > > Austin > > Symon wrote: >> Hi, >> Can anyone point me to the spec. for the maximum clock frequency for the >> CLKDIV pin of the IDELAY block in Virtex 4? I see the IDELAYCTRL blocks >> need >> a 200MHz REFCLK, +/- 10MHz, do I need to use this for the CLKDIV pin? >> Ta, Syms. >> >> >> >> Inviato da X-Privat.Org - Registrazione gratuita >> http://www.x-privat.org/join.php Inviato da X-Privat.Org - Registrazione gratuita http://www.x-privat.org/join.phpArticle: 103863
Symon, OK, I looked for it, and I can't find it. This clock is used for the control of the IDELAY block, and our usual goal is to have control stuff be able to run at the fabric speed (~400 MHz), but I will go find out what it actually is. Sometimes (rarely) these sorts of interfaces can not run at the full fabric speed. Austin Symon wrote: > Hi Austin, > Thanks for that, you've confirmed what I thought the datasheet told me! But > part of my question remains. > Where do I find the specification for the maximum clock frequency on the > IDELAY block remains? In other words, if I want to use the IDELAY block > (Figure 7-11: IDELAY Primitive in UG070) in Variable delay mode > (IOBDELAY_TYPE = VARIABLE), how fast can I clock it? > Regards, Syms. > > "Austin Lesea" <austin@xilinx.com> wrote in message > news:e6ms5c$lji1@xco-news.xilinx.com... >> Symon, >> >> The Ref Clock may be supplied from any +/- 10% 200 MHz source, including >> the DCM CLKFX output. For example, if there is a 66 MHz clock, a M=3, >> D=1 will provide you with a ~ 200 MHz output on CLKFX. There is no need >> to be concerned with the jitter from the CLKFX, as the analog locked >> loop which controls the delay is effectively a PLL which filters out the >> high frequency jitter components (jitter on Refclk is attenuated when >> transfered to the data lines). >> >> It is not our intent to require a separate oscillator for this function, >> one should be able to make good use of the clocks that are already part >> of your design. >> >> Initially we did not mention use of the DCM as a source of clock for the >> IDELAY, as it took some time to finish the characterization of the >> jitter attenuation of the analog loop used. >> >> Austin >> >> Symon wrote: >>> Hi, >>> Can anyone point me to the spec. for the maximum clock frequency for the >>> CLKDIV pin of the IDELAY block in Virtex 4? I see the IDELAYCTRL blocks >>> need >>> a 200MHz REFCLK, +/- 10MHz, do I need to use this for the CLKDIV pin? >>> Ta, Syms. >>> >>> >>> >>> Inviato da X-Privat.Org - Registrazione gratuita >>> http://www.x-privat.org/join.php > > > > Inviato da X-Privat.Org - Registrazione gratuita http://www.x-privat.org/join.phpArticle: 103864
Lattice is holding a webcast tomorrow, Wednesday, June 14, "Optimizing VHDL Coding for More Efficient FPGA Synthesis." The presenter will be Troy Scott, from our software marketing group. If you're interested, the event takes place live at 11am Pacific, 18:00 GMT. In addition, you will be able to view this webcast archive on-demand, at your convenience, starting a few hours after the live event takes place. You can register by clicking: http://www.latticesemi.com/corporate/webcasts/optimizingvhdlcodingformo/index.cfm Bart Borosky, LatticeArticle: 103865
The Xilinx webcast just ended. It was a nice intro to the board; I've got one on my desk so I learned nothing new about my "toy" but for those wondering whether to take the plunge, I'd recommend the board. What was "teased" in the webcast and not followed up was a new board on the horizon using the largest Spartan 3E: the XC3S1600E. Any info on the board as it develops would be appreciated. Some folks on the newsgroup were disappointed in the lack of stubless LVDS paths to get on/off the board and this lack did put a crimp on my prototyping a few 600 MB/s links (I implemented one very nicely as a proof of concept, though). There are lots of wants among the people who visit the newsgroup regularly. If there's anything to whet our appetite or any input before the schematic is final, we're here and some of us are even eager. But for $150, don't wait for the big board. - John_HArticle: 103866
backhus wrote:
> I just tried to minimize a simple statemachine with ISE8.1 and wondered
> that there is no effect, while the machine itself is an ideal target for
> state minimization. (It's a lecture example fur just that purpose)
If state encoding is set to AUTO
you are getting a one-hot encoding
which is not optimum in this case.
Might be a good subject for a lecture :)
Quartus says
13 flops and 17 luts for one-hot
4 flops and 13 luts for binary
What did you get?
-- Mike Treseler
Article: 103867Hi Weng, How large designs are we talking about? For small designs, you can always use free tools. Both open-source like IcarusVerilog and free versions of commercials products. For example, Altera Quartus II WebPack and Actel Libero Gold are both free and include simulators. In the case of Actel it is actually a version of ModelSim. The free versions may sometimes be a little limited, but we have paid hundreds of thousands of dollars for much worse tools in past. (Please note that I dont suggest you should switch to Altera/Actel). regards -Burns >Weng Tianxiang wrote: > Hi, > We want to buy a ModelSim license. > > 1. Buy Xilinx-ModelSim version license from Xilinx website shop for > $1150 with dongle and 1 year expiration limit; > > 2. Buy ModelSim PE version from one of agents we contact: $3K for > perpatual license. > > Both versions will work and make no differences to our applications. > > Does anyone knows a better way to buy a ModelSim license with lowest > price except the above two options? For a start-up, we prefer lowest > price, of course. > > Thank you. > > WengArticle: 103868
I turned over some stones: The stepping of the IDELAY taps can definitely be done at the IDELAY output clock rate, or at 250 MHz, and probably even faster. It's just a counter driving a decoder, so I could imagine that it is even much faster. But 250 MHz is no problem... Peter Alfke, Xilinx Applications ================= Austin Lesea wrote: > Symon, > > OK, I looked for it, and I can't find it. > > This clock is used for the control of the IDELAY block, and our usual > goal is to have control stuff be able to run at the fabric speed (~400 > MHz), but I will go find out what it actually is. Sometimes (rarely) > these sorts of interfaces can not run at the full fabric speed. > > Austin > >Article: 103869
xilinx_user skrev:
> Aurelian Lazarut wrote:
> > just rename, or move these *.v files (behavioral models) from your way,
> > and make sure the edifs are into the working directory, and should work.
> > Aurash
> > / /\/\ Aurelian Lazarut
> > \ \ / System Verification Engineer
> > / / \ Xilinx Ireland
> > phone: 353 01 4032639
> > fax: 353 01 4640324
>
> I am still having trouble.
>
> I have a working directory called "exhaust." In this directory I have
> the following:
>
> xyz.v
> sine_dds.edn
>
> File xyz.v contains the following:
>
> module xyz(CLK,WE,SCLK,WE,A,SINE);
> input CLK,WE,SCLK;
> input [4:0] A;
> output [20:0] SINE;
>
>
>
> sine_dds sine_new(
> .DATA(DATA),
> .WE(WE),
> .A(A),
> .CLK(CLK),
> .CE(CE),
> .SCLR(SCLR),
> .SINE(SINE));
> endmodule
>
> When I try to synthesize xyz.v, I get the following error message:
>
> ERROR:HDLCompilers:87 - "xyz.v" line 10 Could not find module/primitive
> 'sine_dds'
>
> line 10 is "sine_dds sine_new("
>
>
> I am lost, and I do not know what I am doing wrong. By the way I am
> using webpack 8.1
>
> Art
Coregen should also have generated a sine_dds.v file, add that to the
project
-Lasse
Article: 103870I have run across this board in scrap. There was no documentation for this board and I do not have a serial number with it... Does anyone have documentation for this board... I thank you all for any help you can give... -DanArticle: 103871
langwadt@ieee.org wrote:
> xilinx_user skrev:
>
> > Aurelian Lazarut wrote:
> > > just rename, or move these *.v files (behavioral models) from your way,
> > > and make sure the edifs are into the working directory, and should work.
> > > Aurash
> > > / /\/\ Aurelian Lazarut
> > > \ \ / System Verification Engineer
> > > / / \ Xilinx Ireland
> > > phone: 353 01 4032639
> > > fax: 353 01 4640324
> >
> > I am still having trouble.
> >
> > I have a working directory called "exhaust." In this directory I have
> > the following:
> >
> > xyz.v
> > sine_dds.edn
> >
> > File xyz.v contains the following:
> >
> > module xyz(CLK,WE,SCLK,WE,A,SINE);
> > input CLK,WE,SCLK;
> > input [4:0] A;
> > output [20:0] SINE;
> >
> >
> >
> > sine_dds sine_new(
> > .DATA(DATA),
> > .WE(WE),
> > .A(A),
> > .CLK(CLK),
> > .CE(CE),
> > .SCLR(SCLR),
> > .SINE(SINE));
> > endmodule
> >
> > When I try to synthesize xyz.v, I get the following error message:
> >
> > ERROR:HDLCompilers:87 - "xyz.v" line 10 Could not find module/primitive
> > 'sine_dds'
> >
> > line 10 is "sine_dds sine_new("
> >
> >
> > I am lost, and I do not know what I am doing wrong. By the way I am
> > using webpack 8.1
> >
> > Art
>
> Coregen should also have generated a sine_dds.v file, add that to the
> project
>
> -Lasse
sine_dds.v is the simulation file. From what I understand it cannot be
used for sythesis - only the edif file. Besides Aurelian Lazarut
already stated that I need to remove these from the working direcotyr.
It would appear something else is going on.
Article: 103872
xilinx_user skrev:
> langwadt@ieee.org wrote:
> > xilinx_user skrev:
> >
> > > Aurelian Lazarut wrote:
> > > > just rename, or move these *.v files (behavioral models) from your way,
> > > > and make sure the edifs are into the working directory, and should work.
> > > > Aurash
> > > > / /\/\ Aurelian Lazarut
> > > > \ \ / System Verification Engineer
> > > > / / \ Xilinx Ireland
> > > > phone: 353 01 4032639
> > > > fax: 353 01 4640324
> > >
> > > I am still having trouble.
> > >
> > > I have a working directory called "exhaust." In this directory I have
> > > the following:
> > >
> > > xyz.v
> > > sine_dds.edn
> > >
> > > File xyz.v contains the following:
> > >
> > > module xyz(CLK,WE,SCLK,WE,A,SINE);
> > > input CLK,WE,SCLK;
> > > input [4:0] A;
> > > output [20:0] SINE;
> > >
> > >
> > >
> > > sine_dds sine_new(
> > > .DATA(DATA),
> > > .WE(WE),
> > > .A(A),
> > > .CLK(CLK),
> > > .CE(CE),
> > > .SCLR(SCLR),
> > > .SINE(SINE));
> > > endmodule
> > >
> > > When I try to synthesize xyz.v, I get the following error message:
> > >
> > > ERROR:HDLCompilers:87 - "xyz.v" line 10 Could not find module/primitive
> > > 'sine_dds'
> > >
> > > line 10 is "sine_dds sine_new("
> > >
> > >
> > > I am lost, and I do not know what I am doing wrong. By the way I am
> > > using webpack 8.1
> > >
> > > Art
> >
> > Coregen should also have generated a sine_dds.v file, add that to the
> > project
> >
> > -Lasse
>
>
> sine_dds.v is the simulation file. From what I understand it cannot be
> used for sythesis - only the edif file. Besides Aurelian Lazarut
> already stated that I need to remove these from the working direcotyr.
> It would appear something else is going on.
sine_dds.v has the module definition for synthesis and enclosed in
translate_off/translate_on the stuff for simulation.
but if you don't want to listen ... ;)
-Lasse
Article: 103873Hi Everyone, Thank you for your responses. It is a start-up project for commercial use and I am not an academic researcher, instead of, an engineer who has a 2nd own project going on at home and hasn't got financial support from any investors. I have been using Xilinx free tools with ModelSim free software. Now ModelSim says that the size of project is beyond 50K statements that is beyond its limit of 10K statements. Whie beyond limit, ModelSim goes very slow. $3K price for ModelSim PE is acceptable to us, but finally it is found that ModelSim Design is for $3K and ModelSim PE for $5K. So we are wighting for other choice. Thank you. Weng burn.sir@gmail.com wrote: > Hi Weng, > > How large designs are we talking about? > > For small designs, you can always use free tools. Both open-source like > IcarusVerilog and free versions of commercials products. For example, > Altera Quartus II WebPack and Actel Libero Gold are both free and > include simulators. In the case of Actel it is actually a version of > ModelSim. > > > The free versions may sometimes be a little limited, but we have paid > hundreds of thousands of dollars for much worse tools in past. > > > (Please note that I dont suggest you should switch to Altera/Actel). > > regards > -Burns > > >Weng Tianxiang wrote: > > Hi, > > We want to buy a ModelSim license. > > > > 1. Buy Xilinx-ModelSim version license from Xilinx website shop for > > $1150 with dongle and 1 year expiration limit; > > > > 2. Buy ModelSim PE version from one of agents we contact: $3K for > > perpatual license. > > > > Both versions will work and make no differences to our applications. > > > > Does anyone knows a better way to buy a ModelSim license with lowest > > price except the above two options? For a start-up, we prefer lowest > > price, of course. > > > > Thank you. > > > > WengArticle: 103874
Weng, Have you looked at Aldec? Their simulator is as good as modelsim, and has an easier user interface. They also offer VHDL/verilog/edif/matlab co-simulation. The cadillac version competes favorably with modelsim PE for I think a similar price. The versions with fewer features are cheaper. You might contact Aldec and talk to them about your needs. One of the big advantages with Aldec is the customer support, I've always gotten personal attention from their support within hours. Model tech, on the other hand has not been all that responsive when issues come up.
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