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"rickman" <spamgoeshere4@yahoo.com> wrote in message
news:1151941283.587968.307520@v61g2000cwv.googlegroups.com...
> Does anyone know if a FF driven into metastability meets the criteria
> for chaos? Are there factors that prevent a FF output from being
> chaotic even in metastability?
I would imagine that metastable flip-flops might well be capable of chaotic
behaviour but, like you, I didn't find any published reference for this.
Like a "classical" chaotic system such as a double-pendulum, whether any
chaotic behaviour actually occurs will depend on the physical parameters and
initial conditions of the system. So even if the equations governing the
flip-flop's state permit chaotic behaviour, it might never appear under
"normal" circumstances.
I am not a semiconductor physicist (I'm not *any* kind of physicist) so I
can only speculate! :) Would also be interested to know the answer to this.
-Ben-
Article: 104651Vassili schrieb: > Hello All, > > Could anyone please tell me: * Whether I can use "VREF" pins for LVDS output? * What is HSWAPEN exactly for > > Thank you. Vassili Savinov 1 HSWAPEN enables(or disables) pullups when FPGA is *NOT* configred. 2 LVDS - the best thing todo is to actually create the design and see if the place and route complains or not. There are many restrictions on the IO Pin useage specially in Virtex-4 so it is VERY hard to figure out what is ok and what is not - as example in FX12 no IOPAD from the right half of the chip can reach any DCM input! Was a big surprise for me!! So read the manual, but better make the design assign pins and check it is routable! Antti http://antti-brain.comArticle: 104652
you can get away (sometimes) by not connecting all the VCCIO (for the
unused banks, if these paticular banks don't have configuration pins
belonging to them) but I'll strongly advise to connect all Vccint ans
Vccaux
Aurash
blisca wrote:
>for reading the device ID how should the PROGRAM pin be ?
>
>thank you all
>(i'm still spending hours and days trying to do it,no way....no activity on
>TDI or TDO)
>
>
>here ,once ,more the things that i did:
>
>i connected just one 1.8V supply to the VCCINT of the fpga(pin A9),it is not
>easy to test it (soldering wires on a bga as i do is even worse ...)but it
>looks
>that it should be enough for the core,correct???or i need to
>
>i connected in 7 points the 3.3VCCO(A2,B2,B12 , A13,G12,N1,M2) and the
>ground in 3
>points(A1,J1,N12)
>
>i connected the jtag signals,TCK,TDI,TMS,TDO(this one to the level
>amplifier)
>
>I connected PROGRAM fixed to 3.3V,then i tried to connect it with TMS,same
>result.....
>
>I left M0 and M2 open,and them are high,M1 tied to ground,this for choosing
>boundary scan mode
>
>using the debug chain utility i verified that the signals are working but i
>noticed that there is no movement on TMS,and of course on TDO
>
>there is something else missing?
>
>Thank you to everyone in the group that will help me or just will read this
>
>Diego
>
>
>
>
>
>
--
__
/ /\/\ Aurelian Lazarut
\ \ / System Verification Engineer
/ / \ Xilinx Ireland
\_\/\/
phone: 353 01 4032639
fax: 353 01 4640324
Article: 104653Peter Alfke wrote: > bjzhangwn wrote: > > I want to know how I can reset the logic in fpga and make the least > > metastable.I use 2 clock in fpga and if it is nessesary to make the > > reset input signal synchronize under the clock? > > If you use an asynchronous reset signal while the clock is running, > then you must be concerned about the trailing end of Reset. Reset will > not go away everywhere at the same time, which means that some parts of > the circuit end the reset before a certain clock edge, others after > that edge. This can have ugly consequences. > > The standard remedy is to augment (stretch) the asynchronous reset with > a local synchronous reset that lasts longer, but then of course ends > synchronously. > SRL16 shift registers are a popular and cheap way of doing that. > Peter Alfk, Xilinx Thanks for Peter's answer, but I have a problem is that why use SRL16? Why do not use a simple flip-flop? And if I use the LOCKED pin of a DCM, is it synchronous with the input clock of the DCM?Article: 104654
StanleyLee schrieb: > Peter Alfke wrote: > > bjzhangwn wrote: > > > I want to know how I can reset the logic in fpga and make the least > > > metastable.I use 2 clock in fpga and if it is nessesary to make the > > > reset input signal synchronize under the clock? > > > > If you use an asynchronous reset signal while the clock is running, > > then you must be concerned about the trailing end of Reset. Reset will > > not go away everywhere at the same time, which means that some parts of > > the circuit end the reset before a certain clock edge, others after > > that edge. This can have ugly consequences. > > > > The standard remedy is to augment (stretch) the asynchronous reset with > > a local synchronous reset that lasts longer, but then of course ends > > synchronously. > > SRL16 shift registers are a popular and cheap way of doing that. > > Peter Alfk, Xilinx > > Thanks for Peter's answer, but I have a problem is that why use SRL16? > Why do not use a simple flip-flop? And if I use the LOCKED pin of a > DCM, is it synchronous with the input clock of the DCM? interesting, I see no reason why the LOCKED signal should be synch to any of the DCM clocks, I bet it isnt. AnttiArticle: 104655
>Aurelian Lazarut schrieb: > > did you connect Vccaux? (2.5V) > Aurash > blisca wrote: > > >for reading the device ID how should the PROGRAM pin be ? > -- > __ > / /\/\ Aurelian Lazarut > \ \ / System Verification Engineer > / / \ Xilinx Ireland > \_\/\/ > > phone: 353 01 4032639 > fax: 353 01 4640324 Dear Xilinx System Verification Engineer! It stands "XCV200" in the subject from the OP, and that means: "Virtex Family" ! .. and Virtex Family has no VCCAUX !!! I belive that for Xilinx people the "Virtex" is really considered dead - how could be otherwise explainable that Xilinx has obsoleted SystemACE SC what means that an MCS (softcore) is obsoleted!! the only reason could be that Virtex silicon is no longer manufactured what also explains the availability an silly pricing of it. It was really surprising for me to see that ISE 8.1 has silently dropped systemACE SC support! Antti http://antti-brain.comArticle: 104656
for reading the device ID how should the PROGRAM pin be ? thank you all (i'm still spending hours and days trying to do it,no way....no activity on TDI or TDO) here ,once ,more the things that i did: i connected just one 1.8V supply to the VCCINT of the fpga(pin A9),it is not easy to test it (soldering wires on a bga as i do is even worse ...)but it looks that it should be enough for the core,correct???or i need to i connected in 7 points the 3.3VCCO(A2,B2,B12 , A13,G12,N1,M2) and the ground in 3 points(A1,J1,N12) i connected the jtag signals,TCK,TDI,TMS,TDO(this one to the level amplifier) I connected PROGRAM fixed to 3.3V,then i tried to connect it with TMS,same result..... I left M0 and M2 open,and them are high,M1 tied to ground,this for choosing boundary scan mode using the debug chain utility i verified that the signals are working but i noticed that there is no movement on TMS,and of course on TDO there is something else missing? Thank you to everyone in the group that will help me or just will read this DiegoArticle: 104657
Hi Annti,
I was mis leaded because of this statement from the original post:
"i connected just one 1.8V supply to the VCCINT of the fpga"
hence my assumption that a virtexE was in question.
Aurash
Antti wrote:
>>Aurelian Lazarut schrieb:
>>
>>did you connect Vccaux? (2.5V)
>>Aurash
>>blisca wrote:
>>
>>
>>
>>>for reading the device ID how should the PROGRAM pin be ?
>>>
>>>
>>--
>> __
>>/ /\/\ Aurelian Lazarut
>>\ \ / System Verification Engineer
>>/ / \ Xilinx Ireland
>>\_\/\/
>>
>>phone: 353 01 4032639
>>fax: 353 01 4640324
>>
>>
>
>Dear Xilinx System Verification Engineer!
>
>It stands "XCV200" in the subject from the OP, and that means:
>"Virtex Family" ! .. and Virtex Family has no VCCAUX !!!
>
>I belive that for Xilinx people the "Virtex" is really considered dead
>-
>how could be otherwise explainable that Xilinx has obsoleted SystemACE
>SC
>what means that an MCS (softcore) is obsoleted!! the only reason could
>be
>that Virtex silicon is no longer manufactured what also explains the
>availability
>an silly pricing of it.
>
>It was really surprising for me to see that ISE 8.1 has silently
>dropped
>systemACE SC support!
>
>Antti
>http://antti-brain.com
>
>
>
--
__
/ /\/\ Aurelian Lazarut
\ \ / System Verification Engineer
/ / \ Xilinx Ireland
\_\/\/
phone: 353 01 4032639
fax: 353 01 4640324
Article: 104658
Hi Guys,
I'm having trouble with the following problem:
I'm trying to create a 35x35 signed multiplier from DSP48s, inferring
pipelining in VHDL by adding registers after the multilplication
operation as seen below in the VHDL I'm using.
The problem is that when I synthesise, though I can see that the
synthesiser has noticed that it can shift registers about:
Synthesizing (advanced) Unit <signed_mult_TOP>.
Found pipelined multiplier on signal <mult_inst/_n0000>:
- 2 pipeline level(s) found in a register connected to the multiplier
macro output.
Pushing register(s) into the multiplier macro.
- 2 pipeline level(s) found in a register on signal <mult_inst/A2>.
Pushing register(s) into the multiplier macro.
- 2 pipeline level(s) found in a register on signal <mult_inst/B2>.
Pushing register(s) into the multiplier macro.
the clock rate achieved is still only a meagre 81.171MHz. I'll save my
half-baked hypotheses for now and see if anyone knows what's up here.
Any help you can give would be very much appreciated.
Robin
VHDL:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
ENTITY signed_mult_35x35 IS
generic (PIPE: natural);
port (
clk: IN std_logic;
a: IN signed(34 downto 0);
b: IN signed(34 downto 0);
o: OUT signed(69 downto 0));
END signed_mult_35x35;
ARCHITECTURE signed_mult_35x35_a OF signed_mult_35x35 IS
signal A2 : signed(34 downto 0);
signal B2 : signed(34 downto 0);
subtype mult_result is signed(69 downto 0);
type mult_result_array is array (0 to PIPE - 2) of mult_result;
signal pipeline_array : mult_result_array;
BEGIN
o <= pipeline_array(PIPE - 2);
reg: process(CLK) begin
if(rising_edge(CLK)) then
A2 <= a;
B2 <= b;
pipeline_array(0) <= A2 * B2;
for i in 1 to PIPE - 2 loop
pipeline_array(i) <= pipeline_array(i-1);
end loop;
-- Registering should be fused into DSP48-inferred multiply operation
end if;
end process;
END signed_mult_35x35_a;
Article: 104659blisca schrieb: > Thank you again to all that answered or only spent their time reading this > post. > Antti wrote > > prog_b needs to have an pullup to logic high level > > about pull-ups: > wich high level?1.8V or 3.3V? > (i forgot to say in the subject that i'm working,but i should better say > "crying",on a xcv200E ) uups! I yielled at Xilinx guy about him commenting about VCCAUX, well on Virtex-E it is also not available so it is no problem anyway. again - M0,M1,M2 - DONT CARE pullup of PROG_B - either 1.8 or 3.3V should be ok but even with PROG_B pulled down JTAG chain should be scannable can you see the IDCODE when you scan the chain? AnttiArticle: 104660
"rickman" <spamgoeshere4@yahoo.com> wrote: >I've been reading about chaos theory and it occurred to me that >metastability might be a chaotic process. It seems something as simple >as a damped, driven pendulum (a grandfather clock) can exhibit chaos. >The pendulum can swing stabily if given enough energy initially so that >it is driven and remains above a threshold point. But if released well >below the threshold it will decay to a static point. It will exhibit >chaotic behaviour when released near the threshold point, rising and >falling in ampitude and never achieving a stable period, but never >decaying to a static point either. > >Does anyone know if a FF driven into metastability meets the criteria >for chaos? Are there factors that prevent a FF output from being >chaotic even in metastability? Thanks for the interesting question. Metastablility is a whole lot of different things under one name, with the one thing in common being the output is expected to be digital and the process for getting there is analog. Some of the TTL FFs have behavior in metastable cases that might well be chaotic. TTL can do all sorts of weird things when metastable, including oscillating. To prove that one of those weird things was both metastable and chaotic could be done if someone could find a period*3 variation in the oscillation after a metastable event. Standard IC CMOS FFs on the other hand, I don't think so. The internal nodes and output do not oscillate, due to the design, as far as I understand it. No oscillation, no chaos. One could clearly design a FF in any technology that would have chaotic metastable behavior. Or a larger circuit with chaotic behavior that depended on the metastability characteristics of the FF. This brings up a different sort of questions: Would there ever be a reason to design a FF to have chaotic metastable behavior? I can't think of any, but perhaps I'm missing something. Are there any useful chaotic circuits that depend on the metastability characteristics of one or more FFs? A google search finds this: http://www.ee.surrey.ac.uk/Personal/D.Jefferies/reliability/reliability.html -- Phil Hays (Xilinx, but speaking for himself)Article: 104661
Aurelian Lazarut schrieb: > Hi Annti, > I was mis leaded because of this statement from the original post: > "i connected just one 1.8V supply to the VCCINT of the fpga" > hence my assumption that a virtexE was in question. > Aurash Well to MY knowledge Virtex-E has also no VCCAUX !? Antti PS To OP, I probably did not say strong enough: for reading of IDCODE over JTAG the prog_b is "DONT CARE" only issue is (or can be) that actualy configuration may fail without pullup.Article: 104662
"blisca" <blisca@tiscali.it> wrote in message news:44a93c14$0$3119$4fafbaef@reader1.news.tin.it... > for reading the device ID how should the PROGRAM pin be ? > > thank you all > (i'm still spending hours and days trying to do it,no way....no activity > on > TDI or TDO) > > [snip] TDI is the input and TDO is the output (at the FPGA). If you don't see activity (ever) on the FPGA's TDI pin then this is your problem. You may have the JTAG controller's TDI/TDO pins swapped. Are you using "flying leads" to connect the controller to your FPGA board? It's easy to get those wrong. I suggest you disconnect the controller from your board, and see which of the controller leads (TDI or TDO) wiggles when it attempts to communicate. The one that wiggles should be connected to the FPGA's TDI pin. BobArticle: 104663
Bob schrieb: > "blisca" <blisca@tiscali.it> wrote in message > news:44a93c14$0$3119$4fafbaef@reader1.news.tin.it... > > for reading the device ID how should the PROGRAM pin be ? > > > > thank you all > > (i'm still spending hours and days trying to do it,no way....no activity > > on > > TDI or TDO) > > > > > [snip] > > TDI is the input and TDO is the output (at the FPGA). If you don't see > activity (ever) on the FPGA's TDI pin then this is your problem. You may > have the JTAG controller's TDI/TDO pins swapped. Are you using "flying > leads" to connect the controller to your FPGA board? It's easy to get those > wrong. > > I suggest you disconnect the controller from your board, and see which of > the controller leads (TDI or TDO) wiggles when it attempts to communicate. > The one that wiggles should be connected to the FPGA's TDI pin. > > Bob good bob! I was wondering that too in the original post but assumed it a typo but assumptions are usually wrong. testing TDI-TDO loop is one of the first things todo of course AnttiArticle: 104664
Thank you again to all that answered or only spent their time reading this post. Antti wrote > prog_b needs to have an pullup to logic high level about pull-ups: wich high level?1.8V or 3.3V? (i forgot to say in the subject that i'm working,but i should better say "crying",on a xcv200E ) and what about the MODE?should i use pull-ups or not? this table is still not clear to me......does it means that if i dont use external pull-ups resistors(wich value?) should i use 1 0 1 with M1 connected to ground and M2 and M0 connected directly to.......VINT or VCCO?In few words,what is the correct mode for phisically implement the correct configuration? Configuration Mode M2 M1 M0 Pull-ups Master Serial 0 0 0 No Slave Serial 1 1 1 No SelectMAP 1 1 0 No Boundary Scan 1 0 1 No <---------- Master Serial (w/pull-ups) 1 0 0 Yes Slave Serial (w/pull-ups) 0 1 1 Yes SelectMAP (w/pull-ups) 0 1 0 Yes Boundary Scan (w/pull-ups) 0 0 1 Yes <---------- > > xilinx datasheet says it has internal pullup but on Virtex family JTAG > config > does not work without external pullup, that is the JTAG chain is > accessible > but configuratio fails. > > minimal connections are > > GND <--------done > VCCINT <--------done,it looks ohmically connected to every VCCINT pin > VCCIO in the bank that supply JTAG <--------done,connecteds to the 3 VCCIO of Banks 2 & 3 B12, G11, M13 > PROG_B pullup <--------not done,doing it soon > JTAG pins <--------done and verified > > thats all! > > if those connections are ok the FPGA should get configured over JTAG > > Antti > http://antti-brain.com >Article: 104665
"StanleyLee" <lizhongqi@hotmail.com> wrote: >Peter Alfke wrote: >> If you use an asynchronous reset signal while the clock is running, >> then you must be concerned about the trailing end of Reset. Reset will >> not go away everywhere at the same time, which means that some parts of >> the circuit end the reset before a certain clock edge, others after >> that edge. This can have ugly consequences. >> >> The standard remedy is to augment (stretch) the asynchronous reset with >> a local synchronous reset that lasts longer, but then of course ends >> synchronously. >> SRL16 shift registers are a popular and cheap way of doing that. >> Peter Alfk, Xilinx > >Thanks for Peter's answer, but I have a problem is that why use SRL16? >Why do not use a simple flip-flop? And if I use the LOCKED pin of a >DCM, is it synchronous with the input clock of the DCM? If reset goes away in less than a clock period, then a single FF will work, with enough care. Not a usual case anymore, unless the clock rate is fairly slow. If reset takes multiple clocks to go away, but less than 16, and the reset assertion time is longer than 16 clocks, then a SRL16 is a very cheap and very good solution. This is a common case. Short reset assertion time cases might require a shift register built out of FFs, or a counter, to stretch the synchronous reset. -- Phil Hays (Xilinx, but speaking for himself)Article: 104666
Oddly enough your answer is given in any of Altera's FPGA data sheets. Below is a sentence pulled from the Stratix data sheet. User I/O pins are tri-stated during configuration. Stratix and Stratix GX devices also have a weak pull-up resistors on I/O pins during configuration that are enabled by nIO_PULLUP. After initialization, the user I/O pins perform the function assigned in the user's design. "bjzhangwn" <bjzhangwn@126.com> wrote in message news:1151750377.065702.84730@d56g2000cwd.googlegroups.com... >I want to know the registers state after the configurations(altera) >Article: 104667
"gary" <rgarik@yahoo.com> wrote in message news:H4CdnVAPvfF8_jXZRVn_vA@giganews.com... > u want to see the instantiated file it is just a inverter ... No, I wanted to see your userip.vhd, in particular what you are doing with h and k, how they get assigned, etc. Does the implementation work with the original (wizard generated) userip.vhd? /MikhailArticle: 104668
blisca schrieb: > > but assumptions are usually wrong. > > > > testing TDI-TDO loop is one of the first things todo of course > > > > Antti > > > > can i do it with iMPACT?or only from line comands?thank you > > PS sorry again because i forget to type the "E", xcv200E sure you can use the impact "debug mode" connected your cable TDI-TDO and shoft some pattern and observer results, eg AnttiArticle: 104669
> but assumptions are usually wrong. > > testing TDI-TDO loop is one of the first things todo of course > > Antti > can i do it with iMPACT?or only from line comands?thank you PS sorry again because i forget to type the "E", xcv200EArticle: 104670
Bob <nimby1_NEEDSPAM@earthlink.net> wrote in message X4dqg.2323$ye3.71@newsread1.news.pas.earthlink.net... > > "blisca" <blisca@tiscali.it> wrote in message > news:44a93c14$0$3119$4fafbaef@reader1.news.tin.it... > > for reading the device ID how should the PROGRAM pin be ? > > > > thank you all > > (i'm still spending hours and days trying to do it,no way....no activity > > on > > TDI or TDO) > > > > > [snip] > > TDI is the input and TDO is the output (at the FPGA). If you don't see > activity (ever) on the FPGA's TDI pin then this is your problem. You may > have the JTAG controller's TDI/TDO pins swapped. Are you using "flying > leads" to connect the controller to your FPGA board? It's easy to get those > wrong. > > I suggest you disconnect the controller from your board, and see which of > the controller leads (TDI or TDO) wiggles when it attempts to communicate. > The one that wiggles should be connected to the FPGA's TDI pin. > > Bob > > Thank you Bob but no doubt about the wires of my jtag controller,they have different color,using the debug chain of iMPACT i can verify the toggling of the signals until the ball pin on the FPGA itselfArticle: 104671
Phil Hays wrote: > "rickman" <spamgoeshere4@yahoo.com> wrote: > > >>I've been reading about chaos theory and it occurred to me that >>metastability might be a chaotic process. It seems something as simple >>as a damped, driven pendulum (a grandfather clock) can exhibit chaos. >>The pendulum can swing stabily if given enough energy initially so that >>it is driven and remains above a threshold point. But if released well >>below the threshold it will decay to a static point. It will exhibit >>chaotic behaviour when released near the threshold point, rising and >>falling in ampitude and never achieving a stable period, but never >>decaying to a static point either. >> >>Does anyone know if a FF driven into metastability meets the criteria >>for chaos? Are there factors that prevent a FF output from being >>chaotic even in metastability? Sounds like an ideal target for experimentation :) ie build a significant number of cells that you make deliberately metastable, and store the results. I'd do this one-at-a-time, to avoid cell coupling effects. ( ie, if you have 512 cells, use 512 edges to get the results ) Of course, actually hitting the very narrow metastable zone is going to be non trivial. It would need a 'deliberate seeking' circuit design. > Thanks for the interesting question. > > > Metastablility is a whole lot of different things under one name, with > the one thing in common being the output is expected to be digital and > the process for getting there is analog. > > Some of the TTL FFs have behavior in metastable cases that might well > be chaotic. TTL can do all sorts of weird things when metastable, > including oscillating. To prove that one of those weird things was > both metastable and chaotic could be done if someone could find a > period*3 variation in the oscillation after a metastable event. > > Standard IC CMOS FFs on the other hand, I don't think so. The > internal nodes and output do not oscillate, due to the design, as far > as I understand it. No oscillation, no chaos. Yes and no. They are regenerative, and they are also analog, and there has to be threshold noise in there as well... So there is chaos in the settling time/final value. > > One could clearly design a FF in any technology that would have > chaotic metastable behavior. Or a larger circuit with chaotic > behavior that depended on the metastability characteristics of the FF. > > > This brings up a different sort of questions: > > Would there ever be a reason to design a FF to have chaotic metastable > behavior? I can't think of any, but perhaps I'm missing something. If you mean never settle, that would be very hard. But there is a wide area of usage for seeding random number generators. Some devices use local oscillators for this, but they are power hungry, and less than ideally random. -jgArticle: 104672
I am starting a new design using V4FX parts. I have only one JTAG connection so far. Is it possible to simultaneously run the debugger and a chipscope session so I can debug problems between the micro and the fpga fabric? If not, do I need a second JTAG and how do I wire it? Thanks, ClarkArticle: 104673
>"gary" <rgarik@yahoo.com> wrote in message
>news:H4CdnVAPvfF8_jXZRVn_vA@giganews.com...
>> u want to see the instantiated file it is just a inverter ...
>
>No, I wanted to see your userip.vhd, in particular what you are doing
with h
>and k, how they get assigned, etc.
>
>Does the implementation work with the original (wizard generated)
>userip.vhd?
>
>/Mikhail
>
>hi,
Iam giving the h,k values to the regesters (slv_reg0,slv_reg1), so
that i can throw the input value from the 'C' code to the inverter & see
the output of the inverter value on the hyper terminal.
Following is my user_ip.vhd file..
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v2_00_a;
use proc_common_v2_00_a.proc_common_pkg.all;
-- DO NOT EDIT ABOVE THIS LINE --------------------
--USER libraries added here
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_DWIDTH -- User logic data bus width
-- C_NUM_CE -- User logic chip enable bus width
--
-- Definition of Ports:
-- Bus2IP_Clk -- Bus to IP clock
-- Bus2IP_Reset -- Bus to IP reset
-- Bus2IP_Data -- Bus to IP data bus for user logic
-- Bus2IP_BE -- Bus to IP byte enables for user
logic
-- Bus2IP_RdCE -- Bus to IP read chip enable for user
logic
-- Bus2IP_WrCE -- Bus to IP write chip enable for user
logic
-- IP2Bus_Data -- IP to Bus data bus for user logic
-- IP2Bus_Ack -- IP to Bus acknowledgement
-- IP2Bus_Retry -- IP to Bus retry response
-- IP2Bus_Error -- IP to Bus error response
-- IP2Bus_ToutSup -- IP to Bus timeout suppress
------------------------------------------------------------------------------
entity user_logic is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_DWIDTH : integer := 32;
C_NUM_CE : integer := 3
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
--USER ports added here
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
Bus2IP_Clk : in std_logic;
Bus2IP_Reset : in std_logic;
Bus2IP_Data : in std_logic_vector(0 to
C_DWIDTH-1);
Bus2IP_BE : in std_logic_vector(0 to
C_DWIDTH/8-1);
Bus2IP_RdCE : in std_logic_vector(0 to
C_NUM_CE-1);
Bus2IP_WrCE : in std_logic_vector(0 to
C_NUM_CE-1);
IP2Bus_Data : out std_logic_vector(0 to
C_DWIDTH-1);
IP2Bus_Ack : out std_logic;
IP2Bus_Retry : out std_logic;
IP2Bus_Error : out std_logic;
IP2Bus_ToutSup : out std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
end entity user_logic;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of user_logic is
--USER signal declarations added here, as needed for user logic
------------------------------------------
-- Signals for user logic slave model s/w accessible register example
------------------------------------------
signal slv_reg0 : std_logic_vector(0 to
C_DWIDTH-1);
signal slv_reg1 : std_logic_vector(0 to
C_DWIDTH-1);
signal slv_reg2 : std_logic_vector(0 to
C_DWIDTH-1);
signal slv_reg_write_select : std_logic_vector(0 to 2);
signal slv_reg_read_select : std_logic_vector(0 to 2);
signal slv_ip2bus_data : std_logic_vector(0 to
C_DWIDTH-1);
signal slv_read_ack : std_logic;
signal slv_write_ack : std_logic;
signal h : std_logic_vector(0 to 31);
signal k : std_logic_vector(0 to 31);
component inverter
port( s : in std_logic_vector(0 to 31);
t : out std_logic_vector(0 to 31));
end component;
begin
we: inverter
port map(h,k);
--USER logic implementation added here
------------------------------------------
-- Example code to read/write user logic slave model s/w accessible
registers
--
-- Note:
-- The example code presented here is to show you one way of
reading/writing
-- software accessible registers implemented in the user logic slave
model.
-- Each bit of the Bus2IP_WrCE/Bus2IP_RdCE signals is configured to
correspond
-- to one software accessible register by the top level template. For
example,
-- if you have four 32 bit software accessible registers in the user
logic, you
-- are basically operating on the following memory mapped registers:
--
-- Bus2IP_WrCE or Memory Mapped
-- Bus2IP_RdCE Register
-- "1000" C_BASEADDR + 0x0
-- "0100" C_BASEADDR + 0x4
-- "0010" C_BASEADDR + 0x8
-- "0001" C_BASEADDR + 0xC
--
------------------------------------------
slv_reg_write_select <= Bus2IP_WrCE(0 to 2);
slv_reg_read_select <= Bus2IP_RdCE(0 to 2);
slv_write_ack <= Bus2IP_WrCE(0) or Bus2IP_WrCE(1) or
Bus2IP_WrCE(2);
slv_read_ack <= Bus2IP_RdCE(0) or Bus2IP_RdCE(1) or
Bus2IP_RdCE(2);
-- implement slave model register(s)
SLAVE_REG_WRITE_PROC : process( Bus2IP_Clk ) is
begin
if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
if Bus2IP_Reset = '1' then
slv_reg0 <= (others => '0');
slv_reg1 <= (others => '0');
slv_reg2 <= (others => '0');
else
case slv_reg_write_select is
when "100" =>
for byte_index in 0 to (C_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg0(byte_index*8 to byte_index*8+7) <=
Bus2IP_Data(byte_index*8 to byte_index*8+7);
end if;
end loop;
when "010" =>
for byte_index in 0 to (C_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg1(byte_index*8 to byte_index*8+7) <=
Bus2IP_Data(byte_index*8 to byte_index*8+7);
end if;
end loop;
when "001" =>
for byte_index in 0 to (C_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg2(byte_index*8 to byte_index*8+7) <=
Bus2IP_Data(byte_index*8 to byte_index*8+7);
end if;
end loop;
when others => null;
end case;
end if;
end if;
end process SLAVE_REG_WRITE_PROC;
-- implement slave model register read mux
SLAVE_REG_READ_PROC : process( slv_reg_read_select, slv_reg0,
slv_reg1,h,k,slv_reg2 ) is
begin
case slv_reg_read_select is
when "100" => slv_ip2bus_data <= h;
when "010" => slv_ip2bus_data <= k;
when "001" => slv_ip2bus_data <= slv_reg2;
when others => slv_ip2bus_data <= (others => '0');
end case;
end process SLAVE_REG_READ_PROC;
------------------------------------------
-- Example code to drive IP to Bus signals
------------------------------------------
IP2Bus_Data <= slv_ip2bus_data;
IP2Bus_Ack <= slv_write_ack or slv_read_ack;
IP2Bus_Error <= '0';
IP2Bus_Retry <= '0';
IP2Bus_ToutSup <= '0';
end IMP;
//regards
//gary
Article: 104674Jim Granville wrote: > Phil Hays wrote: > > "rickman" <spamgoeshere4@yahoo.com> wrote: > > > > > >>I've been reading about chaos theory and it occurred to me that > >>metastability might be a chaotic process. It seems something as simple > >>as a damped, driven pendulum (a grandfather clock) can exhibit chaos. > >>The pendulum can swing stabily if given enough energy initially so that > >>it is driven and remains above a threshold point. But if released well > >>below the threshold it will decay to a static point. It will exhibit > >>chaotic behaviour when released near the threshold point, rising and > >>falling in ampitude and never achieving a stable period, but never > >>decaying to a static point either. > >> > >>Does anyone know if a FF driven into metastability meets the criteria > >>for chaos? Are there factors that prevent a FF output from being > >>chaotic even in metastability? > > Sounds like an ideal target for experimentation :) > > ie build a significant number of cells that you make deliberately > metastable, and store the results. > I'd do this one-at-a-time, to avoid cell coupling effects. > ( ie, if you have 512 cells, use 512 edges to get the results ) > > Of course, actually hitting the very narrow metastable zone > is going to be non trivial. It would need a 'deliberate seeking' > circuit design. > > > > Thanks for the interesting question. > > > > > > Metastablility is a whole lot of different things under one name, with > > the one thing in common being the output is expected to be digital and > > the process for getting there is analog. > > > > Some of the TTL FFs have behavior in metastable cases that might well > > be chaotic. TTL can do all sorts of weird things when metastable, > > including oscillating. To prove that one of those weird things was > > both metastable and chaotic could be done if someone could find a > > period*3 variation in the oscillation after a metastable event. > > > > Standard IC CMOS FFs on the other hand, I don't think so. The > > internal nodes and output do not oscillate, due to the design, as far > > as I understand it. No oscillation, no chaos. > > Yes and no. They are regenerative, and they are also analog, > and there has to be threshold noise in there as well... > So there is chaos in the settling time/final value. > > > > > One could clearly design a FF in any technology that would have > > chaotic metastable behavior. Or a larger circuit with chaotic > > behavior that depended on the metastability characteristics of the FF. > > > > > > This brings up a different sort of questions: > > > > Would there ever be a reason to design a FF to have chaotic metastable > > behavior? I can't think of any, but perhaps I'm missing something. > > If you mean never settle, that would be very hard. > > But there is a wide area of usage for seeding random number generators. > Some devices use local oscillators for this, but they are power hungry, > and less than ideally random. > > -jg When I was so much younger, an elder colleague now retired explained a little experiment he used to do for the new lads that weren't quite sure about metastability, must have been early 70s. Using classic 4000 series RCA cmos devices, he would set up a flop to go meta stable and keep it there by watching it come out. It needed a servo loop that would put a voltage onto Din with a D/A converter and restore the flop back to the middle state if it came out adjusting the servo to maximize the period. Can't recall how long though. You could probably repeat that today if you could find real 18v style cosmac parts. John Jakson
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