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Messages from 106650

Article: 106650
Subject: Re: Crystal input for FPGA
From: "Symon" <symon_brewer@hotmail.com>
Date: 16 Aug 2006 22:52:12 +0200
Links: << >>  << T >>  << A >>

"Antti" <Antti.Lukats@xilant.com> wrote in message
news:1155663532.687608.302340@75g2000cwc.googlegroups.com...
>
> for s3,s3e,v4 it is also possible to use the DCM in as on-chip free
> running oscillators by enabling factory test mode.
>
Hi Antti,
Is that feature documented anywhere? Or is this a task for my FAE?
Thanks, Syms.



Article: 106651
Subject: S3 starter kit, command-line
From: burn.sir@gmail.com
Date: 16 Aug 2006 13:56:07 -0700
Links: << >>  << T >>  << A >>


Any idea why flash programming would fail on the old starter kit (S3,
not S3E)? I cant even load the Digilent demo bitfile without getting a
verification error. The jumper is on default and the board works just
fine otherwise. Flash blanking  and readback works just fine.


Anyone out there with a simple ISE project that generates
bitstream/prom and programs the board without using the UI?


[the ironic thing is that the project I am trying to get to work is a
programmer for Atmel flash]

regards
 - Burns


Article: 106652
Subject: Re: Crystal input for FPGA
From: "Antti" <Antti.Lukats@xilant.com>
Date: 16 Aug 2006 14:10:06 -0700
Links: << >>  << T >>  << A >>
Symon schrieb:

> "Antti" <Antti.Lukats@xilant.com> wrote in message
> news:1155663532.687608.302340@75g2000cwc.googlegroups.com...
> >
> > for s3,s3e,v4 it is also possible to use the DCM in as on-chip free
> > running oscillators by enabling factory test mode.
> >
> Hi Antti,
> Is that feature documented anywhere? Or is this a task for my FAE?
> Thanks, Syms.

I dont think your FAE does know it. unless his name is Ken Chapman!

there is some documentation in Spartan3e reference designs docs.
the useage for Virtex-4 is a little bit different and only in
http://antti-brain.com
it was possible to wild guess the Virtex-4 dcm_test thing also

Antti


Article: 106653
Subject: Re: Crystal input for FPGA
From: "Antti" <Antti.Lukats@xilant.com>
Date: 16 Aug 2006 14:30:47 -0700
Links: << >>  << T >>  << A >>
Symon schrieb:

> "Antti" <Antti.Lukats@xilant.com> wrote in message
> news:1155663532.687608.302340@75g2000cwc.googlegroups.com...
> >
> > for s3,s3e,v4 it is also possible to use the DCM in as on-chip free
> > running oscillators by enabling factory test mode.
> >
> Hi Antti,
> Is that feature documented anywhere? Or is this a task for my FAE?
> Thanks, Syms.

http://xilant.com/index.php?option=com_content&task=view&id=26&Itemid=32

now the V4 is also docu :)
Antti


Article: 106654
Subject: Re: Quartus and source control (continued)
From: "mswlogo" <geomills@gmail.com>
Date: 16 Aug 2006 14:39:28 -0700
Links: << >>  << T >>  << A >>
I'm starting a new thread on this since Google locked me out from
replying.

Regarding conflicts using CVS, use SVN and tag certain files as
requiring checkout. (I forget the procedure but it uses the property
name you attach. You need to run a script on a regular basis that does
this because it's done on a pre file basis.

Regarding which source control system. Any one should work (but I hate
CVS). SVN is pretty nice.

Regarding which files should be archived (as source). I would not sweat
it too much (e.g. files that get copied from library etc.) It's not the
end of the world if they get versioned.

Ragarding binary: Just check them in as binary. SVN handles binary much
better than svn and the database is amazingly small.

I'm still working myself on what makes sense for users. I have the CAD
folks that use solid works working very nicely on SVN. If also saved
their butts in short order.

I'm trying to understand where FPGA pin mappings are stored as the
users claim they are in the db directory and other folks on the
previous thread said never to version the db directory.


Article: 106655
Subject: Re: Large Spartan3 vs. Small V5
From: "John Adair" <g1@enterpoint.co.uk>
Date: 16 Aug 2006 14:42:44 -0700
Links: << >>  << T >>  << A >>
Brannon

On current technology you would be very lucky to make $40/chip mark for
something the size of a 2V6000 unless you have a very high volume. Even
then I'm dubious.

However it is worth examining your design to see if it can be crushed
to allow smaller cheaper parts to be used. I have seen designs reduced
by 40-50% in some cases by a good designer. Playing with tool settings
can give you something but the best I have seen is in the order of
10-15% reduction by this approach.

Another thing to consider is sharing of resources to reduce size e.g. a
multiplier servicing 2 data streams in a time muxed fashion.

Also for the brew is the fact that the biggest devices come at a
premium and several smaller devices of the equivalent logic size may be
cheaper.

It is also worth looking at the ram to logic ration of the chip you
use. RAM is a relatively expensive resource in a FPGA so using a FPGA
that is less memory rich may bring benefits. Typically the lower end
families have a lower ram/logic ratio. Even within families you will
find variations in the ration so choosing an appropraite size may help
cost too.

John Adair
Enterpoint Ltd.


Brannon wrote:
> So is Xilinx working on another budget-line FPGA? Or are they intending
> that small V5 chips replace the Spartan line altogether? What's their
> next budget chip with the new LUT structure and when can I look for it?
>
> According to Xilinx's website, the Spartan-3E line is for gate-centric
> uses and goes up to 1.2M gates. Yeah. Huge.
>
> I just finished a project that uses 4.5M gates (so says the MRP) on
> each of eight 2v6000 chips. It's only using 1/3 the block RAM and none
> of the MUL blocks on any chip. It only accesses DRAM from one chip. I
> want that project on cheap hardware. What chips would you recommend for
> this? By cheap I mean $40/chip, not $2000/chip.


Article: 106656
Subject: Re: Alternatives to 2v6000
From: "rickman" <gnuarm@gmail.com>
Date: 16 Aug 2006 15:20:17 -0700
Links: << >>  << T >>  << A >>
Brannon wrote:
> > Altera's Cyclone II family is fully supported by free tools and the
> > largest (EP2C70) is about 68k LUT, much more than the 3S5000.
> >
> > I don't know how the pricing compare though.
>
> I think you may have proposed a great plan. Their prices range from
> $125 to $300 for their 672 pin chips (according to their website).
> That's still three times what I had been hoping for, but maybe I could
> make that work. And it is 25% cheaper than Xilinx. Can I get these
> Cyclone II chips for less than that through some other dealer?

I was talking to a rep the other day and he pointed out that "there is
no minimum pricing for FPGAs".  Now we know that is not really true,
but the point is that if you speak with the disti or the manufacturers
account manager, they will be willing to "bid" on your business much
more so than other semi manufacturers.  There seems to be a very high
markup on FPGAs and if you buy in any volume they will give you some
good pricing.  I have seen this first hand where I was given 50,000
piece pricing for 1,000 piece quantities in order to get the design
win.

So don't worry about web pricing, it is typically not very good.  Get
the disti involved and you can get some much better pricing.


Article: 106657
Subject: Re: Large Spartan3 vs. Small V5
From: "Daniel S." <digitalmastrmind_no_spam@hotmail.com>
Date: Wed, 16 Aug 2006 18:43:12 -0400
Links: << >>  << T >>  << A >>
Thomas Womack wrote:
>> I just finished a project that uses 4.5M gates (so says the MRP) on
>> each of eight 2v6000 chips. It's only using 1/3 the block RAM and none
>> of the MUL blocks on any chip. It only accesses DRAM from one chip. I
>> want that project on cheap hardware.
> 
> Is it impossible to make the project use 1.25M gates on each of
> thirty-two 3S1500 chips?  
> 
> http://www.hyperelliptic.org/tanja/SHARCS/talks06/copa_sharcs.pdf
> 
> is the sort of hardware that I imagine targetting when contemplating
> cheap FPGA approaches to problems.

The more chips you have, the more IOs you need to stitch them together 
unless the data dependencies are highly linear, clean and somewhat 
minimalist. Otherwise peak attainable performance quickly becomes IO-bound.

In the case of code-breaking applications, as long as you pick FPGAs 
large enough to contain at least one instance of the code-breaking unit, 
you will not need to worry about interconnects. The rest is simply a 
matter of setting performance targets, selecting an FPGA family then 
cost-optimize the device count, size (number of code-breaking units per 
FPGA vs device cost) and speed grade - code-breaking is generally so 
parallelizable that there is very little to no performance gain between 
a single large-scale system and N N-times as slow smaller-scale ones.

Article: 106658
Subject: Re: Quartus and source control (continued)
From: ghelbig@lycos.com
Date: 16 Aug 2006 16:55:55 -0700
Links: << >>  << T >>  << A >>
mswlogo wrote:
>
> I'm trying to understand where FPGA pin mappings are stored as the
> users claim they are in the db directory and other folks on the
> previous thread said never to version the db directory.

I put pin mappings in the RTL source file.  You can assign I/O type
there as well.

I like to keep all technology/implimentation dependant stuff in one
spot.  The very top level usually works well.


Article: 106659
Subject: Re: Quartus and source control (continued)
From: "Subroto Datta" <sdatta@altera.com>
Date: 16 Aug 2006 17:11:18 -0700
Links: << >>  << T >>  << A >>
The pin mappings are stored in the *.qsf file. Each revision for the
project has its own qsf file. You should not be storing anything from
the db directory in the source code control system.

Hope this helps,
Subroto Datta
Altera Corp.

mswlogo wrote:
> I'm starting a new thread on this since Google locked me out from
> replying.
>
> Regarding conflicts using CVS, use SVN and tag certain files as
> requiring checkout. (I forget the procedure but it uses the property
> name you attach. You need to run a script on a regular basis that does
> this because it's done on a pre file basis.
>
> Regarding which source control system. Any one should work (but I hate
> CVS). SVN is pretty nice.
>
> Regarding which files should be archived (as source). I would not sweat
> it too much (e.g. files that get copied from library etc.) It's not the
> end of the world if they get versioned.
>
> Ragarding binary: Just check them in as binary. SVN handles binary much
> better than svn and the database is amazingly small.
>
> I'm still working myself on what makes sense for users. I have the CAD
> folks that use solid works working very nicely on SVN. If also saved
> their butts in short order.
>
> I'm trying to understand where FPGA pin mappings are stored as the
> users claim they are in the db directory and other folks on the
> previous thread said never to version the db directory.


Article: 106660
Subject: xilinx or altera?
From: "jetq88" <jetq5188@gmail.com>
Date: 16 Aug 2006 18:14:45 -0700
Links: << >>  << T >>  << A >>
which one should I go in term of easy to learn and use, has more
support tool and low cost.
they both have web version of development software, is it enough to do
general work?

thanks


Article: 106661
Subject: Re: Simple state machine in CUPAL
From: "logjam" <grant@cmosxray.com>
Date: 16 Aug 2006 18:40:31 -0700
Links: << >>  << T >>  << A >>
How do I learn the pinnode numbers of the burried flip flops in the
ATF750?  I can't find anything useful in the data sheet.

Grant

Jim Granville wrote:
> logjam wrote:
> > I'm working on a Power-On-Jump GAL/SPLD for an 8080 machine.  I'm
> > trying to figure out how to write it using Sequence/Present/Next
> > syntax.  I'm not sure if a standard 22v10 GAL can handle what I need.
> > I can also use a 750 from Atmel that is basically two 22v10s (I guess
> > this means it has internal pinnodes?)
>
> yes.
>
> > Here is the required flow.  The state machine will have to wait for an
> > input condition and then respond with an output action.
> >
> > Inputs:
> > RESET
> > PDBIN
> >
> > Outputs:
> > DI7...0
> > CCDSB
> >
> > I: RESET LOW
> > O: DI7...0 output enable
> > O: CCDSB LOW
> > I: RESET HIGH (do not necessarily need to wait for)
> > I: PDBIN HIGH
> > 0: DI7...0 = C3
> > I: PDBIN LOW
> > I: PDBIN HIGH
> > O: DI7...0 = 00
> > I: PDBIN LOW
> > I: PDBIN HIGH
> > O: DI7...0 = FF
> > I: PDBIN LOW
> > O: DI7...0 output disable
> > O: CCDSB HIGH
> >
> > Then I would like for the state machine to start waiting for another
> > reset.
> >
> > I tried writing a Sequence/Present routine but the way I wrote it there
> > were duplicated states.  Does anyone have any pointers or suggestions
> > on how I should attack this problem?
>
> if it complains about duplicated states, you need to add some dummy
> state-bits, to make each state unique.
> - above you seem to have 5 output choices, so you need 5 states, which
> is 3 state bits, at a minumum.
>   DI7..0 seem to have no restrictions on value, so cannot be used for
> state variable saving, but CCDSB can be part of the state engine.
>   So that means >= 2 more bits, and unless you can prune DI7..DI0 to
> DI6..DI0, you will need to use the ATF750CL, to get enough macrocells.
>
> >
> > I have 8 other inputs that I did not mention.  JMP15...8.  Once I get
> > the basic logic down I want to make the last byte sent reflect jumper
> > settings (DI7...0 = JMP15...8)
> 
> That needs to be added to your state sequence.
> 
> -jg


Article: 106662
Subject: Re: xilinx or altera?
From: "Tommy Thorn" <tommy.thorn@gmail.com>
Date: 16 Aug 2006 18:45:17 -0700
Links: << >>  << T >>  << A >>
jetq88 wrote:
> which one should I go in term of easy to learn and use, has more
> support tool and low cost.
> they both have web version of development software, is it enough to do
> general work?

Xilnix and Altera (and Atmel, Lattice, Actel, etc) are all _companies_
with _families_ of FPGA products.

X and A are the top dogs and both provide very capable tools that are
"free" for a subset of their FPGA products. It's not clear what your
asking and it's naive to imagine that there would be a simple correct
answer (as both companies are in business and doing quite well).

Both Quartus II (Altera) and ISE WebPACK (Xilinx) are way beyond
"enough for general work"; you could make a living using nothing but
these tolos. If you're familiar with one, it will take little effort to
learn the other. Most likely what will drive your decision is the
availability of development kits.

IMO: I much prefer Quartus II, but the Spartan-3E Starter Kit offers by
far the best value (at $149).

Now, go design :-)

Tommy


Article: 106663
Subject: Re: Quartus and source control (continued)
From: Mark McDougall <markm@vl.com.au>
Date: Thu, 17 Aug 2006 11:51:45 +1000
Links: << >>  << T >>  << A >>
mswlogo wrote:

> I'm trying to understand where FPGA pin mappings are stored as the
> users claim they are in the db directory and other folks on the
> previous thread said never to version the db directory.

The *nice* thing about Quartus is that you only need to store *2* text
files for the project, aside from your source - namely the .QPF and .QSF
files.

Everything else is generated output from Quartus!

Works really well with SVN.

Nice
Regards,

-- 
Mark McDougall, Engineer
Virtual Logic Pty Ltd, <http://www.vl.com.au>
21-25 King St, Rockdale, 2216
Ph: +612-9599-3255 Fax: +612-9599-3266

Article: 106664
Subject: Re: xilinx or altera?
From: Mark McDougall <markm@vl.com.au>
Date: Thu, 17 Aug 2006 11:53:02 +1000
Links: << >>  << T >>  << A >>
jetq88 wrote:

> which one should I go in term of easy to learn and use, has more
> support tool and low cost.
> they both have web version of development software, is it enough to do
> general work?

You may as well ask whether to go with Christianity or Islamic faith! ;)

Regards,

-- 
Mark McDougall, Engineer
Virtual Logic Pty Ltd, <http://www.vl.com.au>
21-25 King St, Rockdale, 2216
Ph: +612-9599-3255 Fax: +612-9599-3266

Article: 106665
Subject: Re: xilinx or altera?
From: Mark McDougall <markm@vl.com.au>
Date: Thu, 17 Aug 2006 11:58:22 +1000
Links: << >>  << T >>  << A >>
Mark McDougall wrote:

> You may as well ask whether to go with Christianity or Islamic faith! ;)

The only meaningful responses you're likely to get are from people that
have reasonable *practical* experience with *both*!

Actually I'd be interested to know the preferences of people in this
category. I've done a few years work with Altera and have recently
cracked open ISE to play with a Spartan-3. I'm finding it an unpleasant
experience but I'm sure that I went through similar over the years when
getting my head around Quartus too?!? So I admit I'm biased atm...

Regards,

-- 
Mark McDougall, Engineer
Virtual Logic Pty Ltd, <http://www.vl.com.au>
21-25 King St, Rockdale, 2216
Ph: +612-9599-3255 Fax: +612-9599-3266

Article: 106666
Subject: Re: xilinx or altera?
From: "Tommy Thorn" <tommy.thorn@gmail.com>
Date: 16 Aug 2006 19:11:56 -0700
Links: << >>  << T >>  << A >>
Mark McDougall wrote:
> Actually I'd be interested to know the preferences of people in this
> category. I've done a few years work with Altera and have recently
> cracked open ISE to play with a Spartan-3. I'm finding it an unpleasant
> experience but I'm sure that I went through similar over the years when
> getting my head around Quartus too?!? So I admit I'm biased atm...

I first _started_ with ISE long ago, but IMO Quartus II has always been
far more logical and user friendly. ISE is much better these days, but
its notion of "work flow" is just a PITA. Not to mention that ISE
appears to get buggier with every release, while I've hardly ever had
issues with Quartus II.

And thus the jihad began...

Tommy


Article: 106667
Subject: Re: xilinx or altera?
From: "TeddyM" <themarenas@comcast.net>
Date: 16 Aug 2006 19:26:57 -0700
Links: << >>  << T >>  << A >>
I think you should choose Switzerland.  That is Lattice's fpga
offerings.  Their fpga families are broad and their web software
includes Synplify synthesis.  The interface is close to ISE and the sw
is very solid.


Tommy Thorn wrote:
> Mark McDougall wrote:
> > Actually I'd be interested to know the preferences of people in this
> > category. I've done a few years work with Altera and have recently
> > cracked open ISE to play with a Spartan-3. I'm finding it an unpleasant
> > experience but I'm sure that I went through similar over the years when
> > getting my head around Quartus too?!? So I admit I'm biased atm...
>
> I first _started_ with ISE long ago, but IMO Quartus II has always been
> far more logical and user friendly. ISE is much better these days, but
> its notion of "work flow" is just a PITA. Not to mention that ISE
> appears to get buggier with every release, while I've hardly ever had
> issues with Quartus II.
> 
> And thus the jihad began...
> 
> Tommy


Article: 106668
Subject: Re: xilinx or altera?
From: "Daniel S." <digitalmastrmind_no_spam@hotmail.com>
Date: Wed, 16 Aug 2006 22:44:43 -0400
Links: << >>  << T >>  << A >>
jetq88 wrote:
> which one should I go in term of easy to learn and use, has more
> support tool and low cost.
> they both have web version of development software, is it enough to do
> general work?
> 
> thanks
> 

It depends on what you want to do, how you want to do it and, to no 
negligeable extent, your personnal preferences.

Altera has had PLLs in its FPGAs for a long time and they are fully 
supported by Altera's Quartus Web Edition. Xilinx introduced PLLs in the 
V5 family but these are not supported by ISE Webpack yet. If you curse 
DCMs (grainy clock adjustments) and swear by PLLs, Altera is the only 
"free" game in town.

Since you say this is for learning, I suggest you download both Quartus 
Web and ISE Webpack, try them for a while and THEN decide which side you 
prefer.

That said, I have yet to touch an Altera device. I have recently started 
using Quartus since I have an upcoming IP validation/integration job 
coming up and the initial tests will be done on a Cyclone-2.

As far as development software goes, ISE has more eye-candy, leaks 
memory and crashes much more often than I would like it to. For Quartus, 
the interface has a somewhat rougher feel to it and I have not played 
with it long enough to see how sturdy it is. On the ease-of-use side, I 
think both are about equally easy to use but ISE has become somewhat 
less intuitive over the last few versions.

Whichever side you pick, the rest is all about getting intimate with 
your chosen FPGA familyies' architecture and your synthesis tools to get 
the most out of the pair... or anything at all when you run into corner 
cases, synthesis bugs, tool crashes, etc. (Are these less common with 
Quartus?)

-- 
Daniel Sauvageau
Matrox Graphics Inc.
1155 St-Regis, Dorval, Qc, Canada
514-822-6000

Article: 106669
Subject: Re: Simple state machine in CUPAL
From: Jim Granville <no.spam@designtools.maps.co.nz>
Date: Thu, 17 Aug 2006 14:54:48 +1200
Links: << >>  << T >>  << A >>
logjam wrote:
> How do I learn the pinnode numbers of the burried flip flops in the
> ATF750?  I can't find anything useful in the data sheet.

[sound of some very dusty archives being dug into...]

et voila :  Snipped from an ATF750 CUPL file :

PIN     1       =
PIN     2       =
PIN     3       =
PIN     4       =
PIN     5       =
PIN     6       =
PIN     7       =
PIN     8       =
PIN     9       =
PIN     10      =
PIN     11      =
PIN     13      =

/*  Output Pin and No
PIN     14      =
PIN     15      =
PIN     16      =
PIN     17      =
PIN     18      =
PIN     19      =
PIN     20      =
PIN     21      =
PIN     22      =
PIN     23      =

PINNODE 25  =
PINNODE 26  =
PINNODE 27  =
PINNODE 28  =
PINNODE 29  =
PINNODE 30  =
PINNODE 31  =
PINNODE 32  =
PINNODE 33  =
PINNODE 34  =


Article: 106670
Subject: Problems about the synthesis(XST)
From: "agou" <agou.win@gmail.com>
Date: 16 Aug 2006 20:13:10 -0700
Links: << >>  << T >>  << A >>
Hi, there

We are using a XUP board to implement an algorithm on FPGA right now.
Our design is pretty big on the chip. The device utilization summary is
listed as follows:

Logic Utilization:
  Number of Slice Flip Flops:      15,413 out of  27,392   56%
  Number of 4 input LUTs:          15,218 out of  27,392   55%
Logic Distribution:
  Number of occupied Slices:       12,892 out of  13,696   94%
  Number of Slices containing only related logic:  12,892 out of
12,892  100%
  Number of Slices containing unrelated logic:          0 out of
12,892    0%
        *See NOTES below for an explanation of the effects of unrelated
logic

Ever since our design grew big, some weird results appeared. And if we
tried different Placer cost table in the fast_runtime.opt, we got
different results. Sometimes good ones. If we optimized the design, and
then shrinked it a little bit, then we could get good result without
trying difference cost tables. We defined the "good result" by seeing
when the maximum frequency reached 100MHz which is what we are running
at.

But now, the frequency reached 101.843 MHz, the weird result still
appeared. Every time I run the code, we got different result. THe
simulation is just fine.

I don't really know what to do next now. I thought we shrinked the
design as much as possible.

So anyone has any idea? Is it possible to use Synplify which is said to
be better? Will it improve a lot?

Thanks a lot.
Zhaoyi


Article: 106671
Subject: Re: Simple state machine in CUPAL
From: "logjam" <grant@cmosxray.com>
Date: 16 Aug 2006 23:51:18 -0700
Links: << >>  << T >>  << A >>
Thanks for the help!  Here is what I came up with.  It seems to work
good (in the simulator!!!).  I hope there are no glitches in the 8080
status signals...

Do you see anything I could have done to make the design better?  I've
included my .PLD and .SIM files.

.PLD file:

Name     PowerOnJump ;
PartNo   00 ;
Date     8/15/2006 ;
Revision 01 ;
Designer Engineer ;
Company  Stockly Electronics ;
Assembly None ;
Location  ;
Device   v750c ;

/*** INPUT PINS ********************** DESCRIPTION
****************************/
PIN   1 = CLK16M                  ; /* 16MHz Clock
      */
PIN   2 = pRESET                  ; /* 8080 Reset Signal, Active Low
      */
PIN   3 = pDBIN                   ; /* 8080 Data bus In Signal, Active
High   */
PIN   4 = na1                     ; /*
      */
PIN   5 = JMPA15                  ; /*
      */
PIN   6 = JMPA14                  ; /*
      */
PIN   7 = JMPA13                  ; /*
      */
PIN   8 = JMPA12                  ; /*
      */
PIN   9 = JMPA11                  ; /*
      */
PIN  10 = JMPA10                  ; /*
      */
PIN  11 = JMPA9                   ; /*
      */
PIN  13 = JMPA8                   ; /*
      */

/*** OUTPUT PINS ********************* DESCRIPTION
****************************/
PIN  14 = CCDSB                   ; /* Command/Control Disable, Active
Low    */
PIN  15 = na2                     ; /*  CCDSB prevents memory from
responding */
PIN  16 = DI0                     ; /*
      */
PIN  17 = DI1                     ; /*
      */
PIN  18 = DI2                     ; /*
      */
PIN  19 = DI3                     ; /*
      */
PIN  20 = DI4                     ; /*
      */
PIN  21 = DI5                     ; /*
      */
PIN  22 = DI6                     ; /*
      */
PIN  23 = DI7                     ; /*
      */

/****** PIN NODES ******************** DESCRIPTION
****************************/
PINNODE 25  = Q0                  ; /*
      */
PINNODE 26  = Q1                  ; /*
      */
PINNODE 27  = Q2                  ; /*
      */
PINNODE 28  = na3                 ; /*
      */
PINNODE 29  = na4                 ; /*
      */
PINNODE 30  = na5                 ; /*
      */
PINNODE 31  = na6                 ; /*
      */
PINNODE 32  = na7                 ; /*
      */
PINNODE 33  = na8                 ; /*
      */
PINNODE 34  = na9                 ; /*
      */

field jmpadr = [JMPA15,JMPA14,JMPA13,JMPA12,JMPA11,JMPA10,JMPA9,JMPA8];
field data = [DI7,DI6,DI5,DI4,DI3,DI2,DI1,DI0];
field count = [Q2, Q1, Q0];

$define S0 'b'000
$define S1 'b'001
$define S2 'b'010
$define S3 'b'011
$define S4 'b'100
$define S5 'b'101
$define S6 'b'110
$define S7 'b'111

!CCDSB = Q2 # Q1;		/* Disable Command/Control outputs if count is > 1
*/
data.oe = !CCDSB & pDBIN;	/* Enable data bus if count is > 1 and the
data bus is IN */

data = 'h'C3 & count:S3 #
	'h'00 & count:S5 #
	jmpadr & count:S7;

count.ck = CLK16M;
count.sp = 'b'000;

SEQUENCE count {
/* If count='d'0 - data.oe='b'0 CCDSB='b'1 */
PRESENT S0	if !pRESET	next S1;	/* If pRESET is low, continue */
		if pRESET	next S0;	/* If pRESET is high, loop */

/* Wait for reset to go high */
PRESENT S1	if pRESET	next S2;	/* If pRESET is high, continue */
		if !pRESET	next S1;

/* If count > 'd'1 then data.oe='b'1,CCDSB='b'0 */

/* Wait for pDBIN to go high */
PRESENT S2	if pDBIN	next S3;	/* If pDBIN is high, continue */
		if !pRESET	next S0;
		if !pDBIN	next S2;

/* If count=S3 data='h'C3 */
PRESENT S3	if !pDBIN	next S4;	/* If pDBIN is low, continue */
		if !pRESET	next S0;
		if pDBIN	next S3;

PRESENT S4	if pDBIN	next S5;	/* If pDBIN is high, continue */
		if !pRESET	next S0;
		if !pDBIN	next S4;

/* If count=S5 data='h'00 */
PRESENT S5	if !pDBIN	next S6;	/* If pDBIN is low, continue */
		if !pRESET	next S0;
		if pDBIN	next S5;

PRESENT S6	if pDBIN	next S7;	/* If pDBIN is high, continue */
		if !pRESET	next S0;
		if !pDBIN	next S6;

/* If count=S7 data=JMPADR */
PRESENT S7    if !pDBIN	next S0;	/* If pDBIN is low, go to the
beginning */
		if !pRESET	next S0;
		if pDBIN	next S7;
}



.SIM file:

Name     PowerOnJump;
PartNo   00;
Date     8/15/2006;
Revision 01;
Designer Engineer;
Company  Stockly Electronics;
Assembly None;
Location ;
Device   v750c;


ORDER: CLK16M, pDBIN, pRESET, jmpadr, CCDSB, count, data;


VECTORS:
C01 'AA' ************
C01 'AA' ************
C00 'AA' ************
C00 'AA' ************
C01 'AA' ************
C01 'AA' ************
C11 'AA' ************
C11 'AA' ************
C01 'AA' ************
C01 'AA' ************
C11 'AA' ************
C11 'AA' ************
C01 'AA' ************
C01 'AA' ************
C11 'AA' ************
C11 'AA' ************
C01 'AA' ************
C01 'AA' ************
C11 'AA' ************
C11 'AA' ************
C01 'AA' ************
C00 'AA' ************
C01 'AA' ************
C01 'AA' ************
C01 'AA' ************
C01 'AA' ************
C11 'AA' ************
C11 'AA' ************
C01 'AA' ************
C01 'AA' ************
C11 'AA' ************
C11 'AA' ************
C01 'AA' ************
C01 'AA' ************
C11 'AA' ************
C11 'AA' ************
C01 'AA' ************
C01 'AA' ************
C11 'AA' ************
C11 'AA' ************
C01 'AA' ************
C01 'AA' ************
C11 'AA' ************
C11 'AA' ************
C01 'AA' ************
C01 'AA' ************


Article: 106672
Subject: Re: Quartus and source control (continued)
From: "Martin Schoeberl" <mschoebe@mail.tuwien.ac.at>
Date: Thu, 17 Aug 2006 09:08:57 +0200
Links: << >>  << T >>  << A >>
>> I'm trying to understand where FPGA pin mappings are stored as the
>> users claim they are in the db directory and other folks on the
>> previous thread said never to version the db directory.
>
> The *nice* thing about Quartus is that you only need to store *2* text
> files for the project, aside from your source - namely the .QPF and .QSF
> files.

If you have more than one device in the JTAG chain also
store the .cdf. And for the SOPC builder all information
is in the .ptf. So you end up with a maximum of 4 files
and they are all plain text. Very convenient.

Martin 



Article: 106673
Subject: Re: FPGA Memory Power
From: "Xesium" <amirhossein.gholamipour@gmail.com>
Date: 17 Aug 2006 00:12:21 -0700
Links: << >>  << T >>  << A >>
I'm wondering if you have your elf file on the off-chip memory how you
want to measure the power consumption of the system?

daniel.larkin@gmail.com wrote:
> Thanks for clearing that up Peter,
>
> For others, I found the following link quite useful:
> https://intranet.insa-toulouse.fr/view/422/content/64bit_ram.html
>
> Peter Alfke wrote:
> > quickwayne@gmail.com wrote:
> > > Probably it is because that on-chip memory are dual port memory, at
> > > least for Xilinx FPGA, and much more power consuming compared to single
> > > port memory.
> > >
> > There is no reason to assume that a dual-port memory uses any more
> > power than a single-port memory (as long as the second port is not
> > being exercised).
> > Dynamic power is almost exclusively in the address decoding structure.
> > Static power consumption is in all transistor cells.
> >
> > I do not think that nebulous speculations belong in this newsgroup.
> > Peter Alfke, Xilinx


Article: 106674
Subject: Re: Is necessary to use Modsim on DDR Memory development?
From: heinerlitz@gmx.de
Date: 17 Aug 2006 00:12:42 -0700
Links: << >>  << T >>  << A >>
I have another question regarding this topic?

Is it possible to use cadence NCSIM? I tried and it runs, no crypted
library problems or anything still I get loads of bit error out of
bounds faults and the DDR model does not work. I can write data but
cannot read it back.
Any ideas?




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