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Mark McDougall <markm@vl.com.au> writes: > The *nice* thing about Quartus is that you only need to store *2* > text files for the project, aside from your source - namely the .QPF > and .QSF files. I only store ONE file for Quartus, a tcl script to compile the design. It includes all the pin assignments, global assignments to generate SVF files etc. A typical build from a fresh checkout will look like: cvs co designname cd designname/impl/ep1c6t144c8 quartus_sh -t compile.tcl Petter -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail?Article: 106676
Martin Schoeberl wrote: > And for the SOPC builder all information > is in the .ptf. Ah yes, indeed! However, we'll strategically overlook mentioning NIOS IDE projects and the !@#*@&^#%$% workspace... ;) Regards, -- Mark McDougall, Engineer Virtual Logic Pty Ltd, <http://www.vl.com.au> 21-25 King St, Rockdale, 2216 Ph: +612-9599-3255 Fax: +612-9599-3266Article: 106677
Petter Gustad wrote: > A typical build from a fresh checkout will look like: > cvs co designname > cd designname/impl/ep1c6t144c8 > quartus_sh -t compile.tcl Now there's someone who doesn't like documenting build instructions! ;) Regards, -- Mark McDougall, Engineer Virtual Logic Pty Ltd, <http://www.vl.com.au> 21-25 King St, Rockdale, 2216 Ph: +612-9599-3255 Fax: +612-9599-3266Article: 106678
I used to use Cygwin, but when I installed Quartus II and Nios, my local installation stopped working; it couldn't find cygwin1.dll. Rather than fight that, I remove my local installation of it, uninstalled Quartus II and Nios II and reinstalled everything. To no avail the binaries under C:\altera\kits\nios2_60\bin\nios2-gnutools\H-i686-pc-cygwin\bin doesn't run. Incidently, the Nios II Dev Board, reference manual seems out of sync. In "Appendix B: Restoring Factory Configuration, step 1" the directions to launch the SDK Shell doesn't match the menus -- in fact, there aren't any SDK Shell under the Altera menu. I'd be much obliged for any help here. Thanks, TommyArticle: 106679
dear Zhaoyi PAR tools are statistical tools and never generate the same results on each run. Especially the case when the device utilization is high , You will find some nets that will not be meeting timings. You fix them by adding pipeline and next time after PAR some other nets will not be meeting timings. To solve this problem use efficient floor planning tools like planAhead or make many runs of PAR and see results. regards MHArticle: 106680
Hello, I am using the Xilinx XUPV2P board and connect to it using the USB cable. My idea is to upload some data to the board, have the FPGA do some processing and then downloading the result from the board. To transfer the data I use the XMD utility and connect GDB to it. In GDB I use the "restore" and "dump memory" commands to access the DDR memory on the board and the "load" and "c" commands to load my program and execute it. The nice thing is that all of this is easy to set up, can be scripted, and requires only the usb cable to connect to the board. The bad thing is that dumping the memory takes a long time. Downloading the data set to the board using the "restore" command has a reasonable speed (for my purposes), about 60K/sec. Uploading the memory from the board back to the PC with the "dump memory" command, however, has a speed of approx. 2K/sec. This was measured running the USB cable at 12 Mhz, and after the program had finished so no other peripherals were using the bus. The system consisted of a powerPC core, a serial interface and a 256 MB DDR module, and everything the BSB adds to make them work together. Can anybody tell me what causes this difference in speed? Any hints on how to increase the speed would also be very welcome. Currently I am considering using the serial port to transfer data back to the PC, since it would get a higher throughput. The ethernet port would also be an option, but since I have no license for the Ethernet core from Xilinx it is kinda hard to get it working. Thanks, MartijnArticle: 106681
logjam wrote: > Thanks for the help! Here is what I came up with. It seems to work > good (in the simulator!!!). I hope there are no glitches in the 8080 > status signals... From here, you are on your own.... I will add that CUPL can append the Sim vectors to the JED file, so you can (on a good programmer) run a full HW vector test, after device PGM. That can be usefull, when you have a green design, and are not sure if the PCB is valid. -jgArticle: 106682
Antti schrieb: > 1) JDrive does not support XCF ASFAIK We use it on our time to digital converters to programm XCF02S. Kolja SulimmaArticle: 106683
Kolja Sulimma schrieb: > Antti schrieb: > > 1) JDrive does not support XCF ASFAIK > > We use it on our time to digital converters to programm XCF02S. > > Kolja Sulimma then I was misinformed AnttiArticle: 106684
Tommy Thorn kirjoitti: > I used to use Cygwin, but when I installed Quartus II and Nios, my local > installation stopped working; it couldn't find cygwin1.dll. Rather than > fight that, I remove my local installation of it, uninstalled Quartus II > and Nios II and reinstalled everything. To no avail the binaries under > C:\altera\kits\nios2_60\bin\nios2-gnutools\H-i686-pc-cygwin\bin doesn't run. > > I'd be much obliged for any help here. > > Thanks, > Tommy Gygwin and Quartus should work nicely together. Are you sure you try to start 'real cygwin' from Cygwin installation directory not from Quartus installation. My cygwin.bat says: @echo off C: chdir C:\cygwin\bin bash --login -i I have cygwin1.dll under C:\cygwin\bin. AnttiArticle: 106685
Kolja Sulimma schrieb: > Antti schrieb: > > 1) JDrive does not support XCF ASFAIK > > We use it on our time to digital converters to programm XCF02S. > > Kolja Sulimma Kolja you are just lucky (more than I was) 1) at the time I needed to program the XCFxxP devices even the BSDL files for the XCFxxP were not available (and as JDrive depends on them it couldnt possible be used at time). 2) Secondly there is an errata on some XCFxxP parts saying that programming only succeeds with JTAG clock above 3MHz, and JDrive bitbang IO doesnt guarantee that clock rate. Ok it is possible to desing high speed jtag interface and make JDrive to support it. 3) I still wonder how are you able to burn an XCF device from .BIT (or binary) file using only the open-source code from JDrive? There is no open-source tools to create ISC files for XCFxxS or XCFxxP or I am misinformed again? XGEN1532 isnt even available any more (and I think it wasnt fully opensource anyway)? so I think it still stands that the XCF programming algorithm is not public neither there is full source code (from xilinx) that implements the algorithm. JDrive can playback ISC files but no opensource tool can generate them, so Xilinx prop. tools are needed anyway AnttiArticle: 106686
Austin Lesea wrote: > There is no sequence sensitivity that I am aware of. Fantastic. Thank you. > Perhaps there is something introduced as the device configures, and > starts or tries to calibrate MGTs before all the supplies are present? > > Since the device requires one Vcco (for the config bank), Vccaux, and > Vccint to be above their power on reset thresholds, the device could > configure and start before the MGT supplies are present or even while > they are still changing (depending on how fast they power on in relation > to the other three supplies I mentioned). > > That might be the source of your problem? No problem *yet*, I'm still at design stage, just want to aim for the golden egg of right first time :) The V4 specs require a soft-start for Vcco, Vccaux and Vccint which I'm giving them. The MGTs require separate LDO supplies which will come up pretty instantaneously at power on, certainly way before the three main supplies. I was just wondering whether this was a known no-no and if I needed to spec some kind of soft-start for these supplies too. I have a V2 dev board which works fine with an LDO which comes up before the main supplies, I just wanted to make that the situation was the same with the V4. -- Peter > > Austin > > Peter Mendham wrote: >> Does anyone know if it's a problem if the LDO supplies to V4 MGTs come >> up before supplies to the rest of the chip (i.e. before VCCINT)? >> >> Thanks, >> >> -- PeterArticle: 106687
> Can anybody tell me what causes this difference in speed? > Any hints on how to increase the speed would also be very welcome. > > Currently I am considering using the serial port to transfer data back > to the PC, since it would get a higher throughput. > The ethernet port would also be an option, but since I have no license > for the Ethernet core from Xilinx it is kinda hard to get it working. > I'd suggest you try using a download TCL script from within XMD. Basically write a TCL script which reads N bytes from X location, source it within XMD and then execute it. This will avoid the socket communication and remote protocol overhead between XMD and GDB. However, I *think* you are mainly limited by the speed of the jtag protocol between the powerpc and XMD. In which case using Ethernet or RS232 might be the better option. /SivaArticle: 106688
topweaver@hotmail.com wrote: > Hi, > Mentor's HDL Designer has many functions. But I really do not see any > requirement to use a tool to generate a state machine (I have tested > the tools from mentor and Xilinx ISE). Directly writing the code in a > single always block is already very clear and easy. By using such tools > usually cost more time. > Many other functions in the HDL Designer are very useful. As a large > company, Mentor's products indeed cover a very wide area, but at least > in some cases, the free tools from Topweaver family are much more > powerful. > 1, Comparing TME with HDL Designer's Tabular IO, TME shows better > performance in parameter/generic, dynamical adjustment of HDL code > format, secure code synchronization, complex HDL code template and > launch speed. > 2, Like ISE, QUARTUS, ActiveHDL and other tools, HDL Designer's module > integration function is based on traditional schematic method, which is > hardly used in large projects. You can see these tools' demo all using > only a few modules and wires. Topweaver can easily deal with hundreds > of ports. A quick demo from http://www.topweaver.com/demo.htm can show > how to fulfill the integration work within a few minutes. If you can > use any other tool to get the same performance, please let me know. > Now the new version of Topweaver is in the final test. > www.topweaver.com I agree - which is why I only produce state machines in HDL Designer that need to be documented, or are designed by someone else. The tool does a nice job producing pretty graphics, and reasonable HDL. The documentation facility alone makes it worthwhile for those "committee" jobs. While you could use Visio, or some other graphics package, HDL Designer allows you to produce exactly what you drew - so the documentation is immediately linked with the actual design - eliminating documentation errors. However, for the vast majority of my state machines, I just write them out without any tools (other than UltraEdit).Article: 106689
Hi there. I am thinking about to use a Xilinx FPGA to take FFT on some data. Xilinx provide a free FFT core that I most likely can use. I need a windowing function (Like hamming) for that/a FFT function. I have at the moment no idea of how to handle floatingpoints numbers in an FPGA, further I have no ideas for any workarounds. Does anyone have some Ideas/Solutions to that? RaymondArticle: 106690
I think his problem has more to do with some paths being unconstrained since the reported frequency itself meets the constraint. Another possible reason for weird behaviour is an inadequate power supply. /Mikhail "mh" <moazzamhussain@gmail.com> wrote in message news:1155802372.094594.62070@74g2000cwt.googlegroups.com... > dear Zhaoyi > PAR tools are statistical tools and never generate the same results on > each run. Especially the case when the device utilization is high , You > will find some nets that will not be meeting timings. You fix them by > adding pipeline and next time after PAR some other nets will not be > meeting timings. > > To solve this problem use efficient floor planning tools like planAhead > or make many runs of PAR and see results. > > regards > MH >Article: 106691
Let's take a step back here... do you really need floating point?Article: 106692
"Raymond" <raybakk@yahoo.no> wrote in message news:1155820374.552982.238560@i3g2000cwc.googlegroups.com... > > Does anyone have some Ideas/Solutions to that? Use fixed point. The core you mentioned is probably fixed point anyway. /MikhailArticle: 106693
Antti, The readme_xc18v00_xcf00s.txt file included in the downloadables for XAPP058 highlights at least some of the differences between programming algorithms for XC18xx and XCF18xx parts. Don't know if it's of any use though... /MikhailArticle: 106694
Peter, Sounds just fine. we are still characterizing switching power supplies for the MGTs, and I wish I could recommend one, but we haven't finished all our work. Right now, it is best to treat the MGTs like the multi-GHz blocks they really are. If you have any questions, feel free to email me directly, AustinArticle: 106695
In a design:
case 1)
using a clock (divided whith a "vhdl process" 25Mhz
from 50Mhz) so that the remaining of the desing use the divided clock
and a minor part use the original clock...
...then the XST report show:
Device utilization summary:
---------------------------
Selected Device : 3s200ft256-4
Number of Slices: 1798 out of 1920 93%
Number of Slice Flip Flops: 630 out of 3840 16%
Number of 4 input LUTs: 3500 out of 3840 91%
Number used as logic: 3244
Number used as RAMs: 256
Number of IOs: 143
Number of bonded IOBs: 143 out of 173 82%
IOB Flip Flops: 32
Number of BRAMs: 6 out of 12 50%
Number of GCLKs: 2 out of 8 25%
Timing Summary:
---------------
Speed Grade: -4
Minimum period: 26.113ns (Maximum Frequency: 38.295MHz)
Minimum input arrival time before clock: 13.848ns
Maximum output required time after clock: 12.917ns
Maximum combinational path delay: No path found
_._._._._._._._._._._._._._._._._._._._._._._._._._._._._._.
In the same desing but:
case 2)
using a dcm to syntetize a frequency (35Mhz from 50Mhz) so that
the remaining of the design use the dcm output as clock and a minor
part use the original clock...
...then the XST report show:
Device utilization summary:
---------------------------
Selected Device : 3s200ft256-4
Number of Slices: 1610 out of 1920 83%
Number of Slice Flip Flops: 657 out of 3840 17%
Number of 4 input LUTs: 3137 out of 3840 81%
Number used as logic: 2881
Number used as RAMs: 256
Number of IOs: 143
Number of bonded IOBs: 143 out of 173 82%
Number of BRAMs: 6 out of 12 50%
Number of GCLKs: 1 out of 8 12%
Number of DCMs: 1 out of 4 25%
Timing Summary:
---------------
Speed Grade: -4
Minimum period: 63.448ns (Maximum Frequency: 15.761MHz)
Minimum input arrival time before clock: 14.704ns
Maximum output required time after clock: 12.091ns
Maximum combinational path delay: No path found
============================================================
Anyone knows if it can be a normal behaviour (I'm pointing
in particular the Maximum Frequency 15.761MHz using the DCM vs
38.295MHz not using it)...
...or better ;-) I done some mistake somewhere?
thaks in advance
Sandro
Article: 106696>Hi there. > >I am thinking about to use a Xilinx FPGA to take FFT on some data. > >Xilinx provide a free FFT core that I most likely can use. > >I need a windowing function (Like hamming) for that/a FFT function. >I have at the moment no idea of how to handle floatingpoints numbers in >an FPGA, further I have no ideas for any workarounds. > >Does anyone have some Ideas/Solutions to that? > >Raymond > > I suspect that the Xilinx core is fixed-point, and handles the data growth that happens during a FFT in some manner described in its documentation. If it doesn't, then don't use it. You could use a number representation such as Q1.15 that handles numbers in the range -1.0 to +1.0, and do scaling at each pass of the FFT. True floating-point on a FPGA is difficult. Cheers!Article: 106697
How do your two clock domains, 35 MHz and 50 MHz communicate with each other? I hope you are aware of their asynchronous relationship, and the many problems that poses... Peter Alfke, Xilinx ============================ Sandro wrote: > In a design: > case 1) > using a clock (divided whith a "vhdl process" 25Mhz > from 50Mhz) so that the remaining of the desing use the divided clock > and a minor part use the original clock... > ...then the XST report show: > > Device utilization summary: > --------------------------- > Selected Device : 3s200ft256-4 > Number of Slices: 1798 out of 1920 93% > Number of Slice Flip Flops: 630 out of 3840 16% > Number of 4 input LUTs: 3500 out of 3840 91% > Number used as logic: 3244 > Number used as RAMs: 256 > Number of IOs: 143 > Number of bonded IOBs: 143 out of 173 82% > IOB Flip Flops: 32 > Number of BRAMs: 6 out of 12 50% > Number of GCLKs: 2 out of 8 25% > > Timing Summary: > --------------- > Speed Grade: -4 > Minimum period: 26.113ns (Maximum Frequency: 38.295MHz) > Minimum input arrival time before clock: 13.848ns > Maximum output required time after clock: 12.917ns > Maximum combinational path delay: No path found > > _._._._._._._._._._._._._._._._._._._._._._._._._._._._._._. > > In the same desing but: > case 2) > using a dcm to syntetize a frequency (35Mhz from 50Mhz) so that > the remaining of the design use the dcm output as clock and a minor > part use the original clock... > ...then the XST report show: > > Device utilization summary: > --------------------------- > Selected Device : 3s200ft256-4 > Number of Slices: 1610 out of 1920 83% > Number of Slice Flip Flops: 657 out of 3840 17% > Number of 4 input LUTs: 3137 out of 3840 81% > Number used as logic: 2881 > Number used as RAMs: 256 > Number of IOs: 143 > Number of bonded IOBs: 143 out of 173 82% > Number of BRAMs: 6 out of 12 50% > Number of GCLKs: 1 out of 8 12% > Number of DCMs: 1 out of 4 25% > > Timing Summary: > --------------- > Speed Grade: -4 > Minimum period: 63.448ns (Maximum Frequency: 15.761MHz) > Minimum input arrival time before clock: 14.704ns > Maximum output required time after clock: 12.091ns > Maximum combinational path delay: No path found > > ============================================================ > > Anyone knows if it can be a normal behaviour (I'm pointing > in particular the Maximum Frequency 15.761MHz using the DCM vs > 38.295MHz not using it)... > ...or better ;-) I done some mistake somewhere? > > thaks in advance > SandroArticle: 106698
Raymond wrote: > Hi there. > > I am thinking about to use a Xilinx FPGA to take FFT on some data. > > Xilinx provide a free FFT core that I most likely can use. > > I need a windowing function (Like hamming) for that/a FFT function. > I have at the moment no idea of how to handle floatingpoints numbers in > an FPGA, further I have no ideas for any workarounds. > > Does anyone have some Ideas/Solutions to that? > > Raymond > The first thing you need to address is whether or not you really need floating point. Floating point requires quite a bit more complexity for dynamically managing the scaling. Unless your data has a very wide dynamic range, you may find that a fixed point implementation is suitable. If you really need floating point, there is floating point FFT IP out there, but not for free as far as I know. I've got, for example, a floating point FFT core for Virtex 4 that does IEEE single precision FFT sizes from 32 to 4096 points at 400MS/sec continuous. Three engines fit in a V4SX55 for a composite throughput of over 1GS/sec.Article: 106699
Hi everybody, Isi it possible to connect directly FPGA ouptuts to USB line like this : http://osainto.free.fr/USBHOST/usbDirect.pdf (Pull downs are necessary to be able to act as USB Host.) And then to use a dedicated IP for USB host role (some on opencores ) Thanks
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