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"rickman" <gnuarm@gmail.com> wrote in message news:1157060830.197096.216820@p79g2000cwp.googlegroups.com... > Symon wrote: > > It is getting a bit pointless to continue to discuss > this as the only thing that is important is how it works. We can get > info on how we expect it to work by doing simulations and analysis, but > measurement is the only way to be sure. But I don't think we even > agree on what constitutes the requirement in terms of impedance. > Rick, I totally agree. Both your designs and mine work, and we've had a robust but civil and highly enjoyable discussion of the issues. I've certainly learned some things from this conversation, thanks for your time and thoughts! I still disagree with the other points in your post, but I've already detailed why in my previous posts, so I'll just have to live with that. Thanks again, and best regards, Syms.Article: 107751
"zcsizmadia@gmail.com" <zcsizmadia@gmail.com> writes: > I've reversed engineer the CableServer communication with Impact and > written from scratch a brand new CableServer. Currently only Parallel > III cable is implemented, but new cables can be added very easily. I > will post the project on sourceforge.net next week. Awesome news, thanks!!!!! I'm really looking forward to trying it! EricArticle: 107752
Hello Martin, >> >>>Know what? What really bad typos indicate? Pretty clear, if someone >>>affords his or her resume that little attention to detail I assume it'll >>>be the same for a design. Can't use that. >> >>Or the person is dyslexic with a foriegn native tounge, language >>impaired, but with experience and genuis in design that can easily be >>offset by using good clerical assistant to help the designer with >>writing, editing, and other written language issues. > > hehe, I walked into the local language school, here in spain, having > problems translating my CV. The average tranlator cannot comprehend > technical terms like "Video Post Production facility engineer" > That's a common misconception even among professional translators. They think that you don't need to be an engineer to translate technical stuff. The result is often close to the manuals that come with some Asian consumer products, between funny and largely incomprehensible. Ask one of your engineer friends to do it. Afterwards you could still have it polished to top-notch Castellano but chances are they put some mistakes back in. Happened to me when I did my own translation into Dutch (many moons ago when I could properly speak it). The boss corrected some of the not so well worded parts. Then the company gave it to an in-house pro who is Dutch. Whoops, nearly all my not so well worded parts were back in :-) -- Regards, Joerg http://www.analogconsultants.comArticle: 107753
On Wed, 30 Aug 2006 20:40:26 GMT, Vladimir Vassilevsky <antispam_bogus@hotmail.com> wrote: > > >Luhan wrote: > > >> >> Glowing perfomance reviews and stock options are what companies give >> valued employees instead of raises. > >Good point, Luhan. In the big company, there is a salary schedule: how >much is getting paid to a person in this position. There is actually no >way for them to give any raise. > >Also this is how the loafers from HR are making themselves look very useful. > >VLV Hi Vladimir, No just wait a dog-gone second here!!! Are you implying that HR people are not hard-working, conscientious, skilled, caring employees? Ha ha ha ha ha. I worked for 15 years in the aerospace industry. My experience is that 80% of HR people should fired as soon as possible. (Those folks were actually detrimental to the welfare of a company.) In my experience, HR people were like Govt employees (I worked for the Fed Govt for 15 years). One person out of five does the useful work, and 4 people out of 5 screw around for 6 hours a day playing on the computer and gossiping on the phone to their sister. What I've learned in recent years is that HR people are often in charge of "Company Training". Because they have no concept whatsoever of what training is needed by their company's employees (particularly engineers) they focus their training expenditures on things like "How To Handle A Difficult Employee", "How To Conduct An Effective Meeting", or "How To Empower Your Employees (that's one of my favorites) ---generally useless training in the competitive world of engineering companies. [-Rick-]Article: 107754
Group, Can somebody check my understanding on the V2PRO30? I currently have some LVTTL single ended signals that are currently sharing a bank with some LVDS inputs. The way I understand the data sheet is that I can run my bank voltage at 3.3V as long as I don't need the on-chip terminating resistors. Is this correct? What happens if I turn on the on-chip terminating resistors with a bank voltage of 3.3V? I'm assuming that the resistance value will then be in question. Thank you, RobArticle: 107755
Jerry Avins wrote: > Engineering is the art of making what you want from things you can get. While Jerry's sig line was ment to imply products/designs, it also includes the organizations we live/work in. Bitching about HR, and doing something about it is the difference between acting like those in HR that sit on the phone and chat with their sisters, and being engineers making or society a better place.Article: 107756
Rick Lyons wrote: > In my experience, HR people were like > Govt employees (I worked for the Fed > Govt for 15 years). One person out of five > does the useful work, and 4 people out of 5 > screw around for 6 hours a day playing on the > computer and gossiping on the phone to their > sister. HR *definitely* belong on the B Arc! Regards, -- Mark McDougall, Engineer Virtual Logic Pty Ltd, <http://www.vl.com.au> 21-25 King St, Rockdale, 2216 Ph: +612-9599-3255 Fax: +612-9599-3266Article: 107757
Joerg wrote: > Hello Martin, > >>> >>>> Know what? What really bad typos indicate? Pretty clear, if someone >>>> affords his or her resume that little attention to detail I assume >>>> it'll >>>> be the same for a design. Can't use that. >>> >>> >>> Or the person is dyslexic with a foriegn native tounge, language >>> impaired, but with experience and genuis in design that can easily be >>> offset by using good clerical assistant to help the designer with >>> writing, editing, and other written language issues. >> >> >> hehe, I walked into the local language school, here in spain, having >> problems translating my CV. The average tranlator cannot comprehend >> technical terms like "Video Post Production facility engineer" >> > > That's a common misconception even among professional translators. They > think that you don't need to be an engineer to translate technical > stuff. The result is often close to the manuals that come with some > Asian consumer products, between funny and largely incomprehensible. > > Ask one of your engineer friends to do it. Afterwards you could still > have it polished to top-notch Castellano but chances are they put some > mistakes back in. Happened to me when I did my own translation into > Dutch (many moons ago when I could properly speak it). The boss > corrected some of the not so well worded parts. Then the company gave it > to an in-house pro who is Dutch. Whoops, nearly all my not so well > worded parts were back in :-) > Of course, this works both ways. Much of the technical literature for components which is available in Chinese has been translated from English by someone in China with an English degree. Some of the Chinese is just as funny as the Asian consumer product manuals you refer to. SteveArticle: 107758
"Rob" <robnstef@frontiernet.net> wrote in message news:yoLJg.205$Ka1.158@news01.roc.ny... > Group, > > Can somebody check my understanding on the V2PRO30? I currently have some > LVTTL single ended signals that are currently sharing a bank with some LVDS > inputs. The way I understand the data sheet is that I can run my bank > voltage at 3.3V as long as I don't need the on-chip terminating resistors. > Is this correct? > Yes. > >What happens if I turn on the on-chip terminating > resistors with a bank voltage of 3.3V? I'm assuming that the resistance > value will then be in question. > I think the software will stop you doing this. From previous discussions with Austin, I believe this is because the termination will be out of spec. Dunno why, it seems daft to me. I would've thought that bit would be powered by Vccaux, but I guess not. Cheers, Syms.Article: 107759
Frank Buss wrote: > jacko wrote: > > > > > http://indi.joox.net link to quartus II files > > This looks like a net list or something like this. I have only ISE WebPack > installed and I don't know how to display it. Do you have a picture of it? i think ahdl custom to altera. there tool is web downloaded. could notget the xilinx tool to download after 5 attempts. website more specific. the zip file is current project design files in quartus II version 6, but still have to design instruction sequencing unit. thought of using an 8 cycle simple instruction execution, for a very compact IP core. also decided that modular forth in instancable blocks would be most flexible. it is going to evolve as a 16n design, as all carry can happen along multiple instances to make any 16*n word size, but i have to decide how the program word width may or may not expand to the word size. i hope to get wishbone and avalon bus interfaces too, but this is not my immediate priority. i intend a serial bus standard to allow connected multicore designs, each core having 128KB memory. does anyone know how to export a quartus project as VHDL? cheesr jackoArticle: 107760
rickman wrote: <snip> > If a chip can produce a rise time of 0.5 nS > then clearly the power plane is providing enough current at very high > frequencies to drive the transmission line. I don't see how the chip > could possibly provide enough coulombs to drive the line without the > power coming from the power plane. > > Is it possible that HJ was referring to the packages with higher lead > inductance (any type of leaded package such as SSOP, TSSOP or QFP) > compared to BGA and CSP? It was a BGA package with on-package decoupling and - for highest frequencies - capacitance in the silicon. If you ask yourself how many coulombs are associated with a single switching event and compare it to the energy stored in an 0402 capacitor you might be surprised. These things look nearly like AC shorts at their SRFs, after all.Article: 107761
Hi all, Recently I bought a Spartan 3E starter kit board and met some configuration problems. As indicated in the user guide for the board, it can be programmed by the USB cable shipped with the kit, (see user guide page 28). However, it seems the programming via the USB does not work and the driver software on the PC side is not properly installed, although the user guide says the "windows OS should recognized and install the associated driver software". Well, Xilinx trust too much on Windows! I already checked with the Xilinx website and no answer was found for this problem. I do find similar questions posted on other bbs but nobody answered. Can anybody help? Thank you in advance. SteveArticle: 107762
On 27 Aug 2006 20:39:49 -0700, "rickman" <gnuarm@gmail.com> wrote: >Austin Lesea wrote: >> To the subject at hand: placing additional caps across existing caps >> does not reduce the noise (unless the dominant cause is lack of adequate >> capacitance). >> >> The reason why the noise is bad is that the L (as in Ldi/dt) is most >> likely the largest, and most dominant factor, in the form of the via and >> traces to the bypass capacitor. >> >> Many times people have placed additional caps on top of the the existing >> caps and wondered why the noise is not reduced: well, you did not >> change the L in the equation, did you. So why did you expect V to change? >> >> You may have moved the resonant frequency (more often not), but often >> people make the mistake of assuming that a 0.1uF requires a 0.01uF and a >> 0.001uF in parallel. You can see that if the series L is dominant, you >> haven't even moved the frequency by more than a few percent by the small >> amount of additional capacitance. > >What do you think about the idea that if the caps are connected >directly to good low impedance power planes that the location of the >caps are not critical at all. I have been discussing this in >comp.arch.embedded and have not gotten much negative feedback except >some claim that more is always better and that multiple values are not >needed. > I sometimes add a few SMA connector footprints to multilayer boards so I can TDR the planes. As near as I can measure with my Tek 20 GHz TDR, on a bare VME-sized (6U) board, good parallel planes look like an ideal capacitor, with no evidence of edge reflections or anything like that. And as you load ceramic bypass caps *anywhere* on the board, the value of the ideal cap increases. So it doesn't much matter where you put bypass caps. The planes are a better cap than any discrete parts. Keep the powerplane to ground dielectric thin, 5 mils or less, to keep the plane capacitance high. JohnArticle: 107763
I have a 4 layer, development board in prototype stage. The board has an
XCR3128XL CPLD and a Spartan 3 XC3S400 FPGA both running at 3.3 volts. I
started out trying to program the CPLD with a simple clocked counter
process in VHDL. I am using a parallel 3 download cable. The code
simulates correctly, synthesises and fits, etc and, according the impact
software, programs correctly. I can erase the part, verify that it is
erased, program the part, verify that it's programmed, but I get no
response from any of the pins. I have checked the UCF file, pin reports,
power supply and ground pins on the device and everything looks fine but
still no output. I finally went down to even a simpler pin assignment:
outpin1 <= '1';
outpin2 <= '0';
Still no output. I did all of this on two assembled boards with the same
results. So, I finally figured I must have two fried CPLDs (one on each
board.)
I then turned my attention to the Spartin 3 device, set up a ucf, vhdl
file, ran it through the xilinx software, created an programming file
and again tried to program this part with the parallel 3 cable (JTAG
mode without a serial ROM). Again, the impact software says all is ok,
part erases, programs, verifies, but still no output. (also again on
both boards.)
Now, I'm not quite believing I have four bad parts that erase, program
and verify, (and get valid part descriptors)
Is it possible to program and verify a part that is foo bared?, or do I
have a screwed up programming cable? Anybody else been through this?
Mike
Article: 107764On 29 Aug 2006 12:34:50 -0700, "rickman" <gnuarm@gmail.com> wrote: >John_H wrote: >> "rickman" <gnuarm@gmail.com> wrote in message >> Won't any higher inductance result in the same above-SRF slope? That is, >> given the total inductance, it won't matter what the capacitance is once >> above an ohm in the impedance vs freq plot. > >I'm not sure what you are asking. A different capacitance will not >change the inductive part of the impedance curve and a different >inductance will not change the capacitive part of the curve. What >changes in both cases is the SRF. So you put a few 0.1 uF caps on the >board and a number more of 0.01 uF caps and even more of the 0.001 uF >caps. Each capacitance value needs to have sufficient quantity to >bring the impedance near the SRF low enough to be effective. Then the >capacitive effect of the smaller caps keep the overall impedance low in >spite of the larger caps being inductive. There's nothing wrong with a cap being inductive as long as the inductance is low. If somebody made a 10 farad 0603 cap, its SRF might be a kilohertz or something, but having more C, and operating above srf, doesn't make it any worse a high-frequency bypass. I figure the more C, the better for any given size. PCB planes are a big, lossy, many-nF capacitors (or, if you prefer, big, lossy, super-low Z transmission lines), and adding lots of, say, 0.33 uF 0603 caps just makes it better. All this stuff about Spicing staggered srf nulls is silly, given that the caps aren't out in space, they're soldered to the huge low-z lossy power planes. JohnArticle: 107765
Ayon kay John_H: > "yy" <yy7d6@yahoo.com.ph> wrote in message > news:1157037993.495350.96860@b28g2000cwb.googlegroups.com... > > Hi i am designing a PCI-X 64-bit 66 Mhz Device in FPGA, connected with > > a SBC (without backplane), the Spec says that IDSEL for the first slot > > be routed to AD32, IDSEL for the 2nd slot is AD31 and so on, does this > > mean that i don't need to have an I/O assigned for IDSEL in my FPGA? > > and refer to AD32 for IDSEL during configuration transaction? > > > > BTW, i use Xilinx Spartan 3 fpga. > > Thanks. > > > I don't believe AD32 is a specific requirement, just a suggestion. If your > FPGA is embedded on the PCI bus and not interfaces to a slot that has a slot > IDSEL assigned, then yes, you can hard-wire the IDSEL of your PCI core to > the selected AD line either inside your device or through a resister > external to the device. It won't matter to your embedded system which > approach you use. The Single Board Computer (SBC) to which the PCI Device is to connect does not have IDSEL on its Edge fingers, also it has CLKA,CLKB,CLKC, and CLKD to pair with REQ0#-GNT0# to REQ3#-GNT3#. So i will have to either try both.Article: 107766
Ju, Jian wrote: > Hi all, > > Recently I bought a Spartan 3E starter kit board and met some configuration > problems. As indicated in the user guide for the board, it can be programmed > by the USB cable shipped with the kit, (see user guide page 28). However, it > seems the programming via the USB does not work and the driver software on > the PC side is not properly installed, although the user guide says the > "windows OS should recognized and install the associated driver software". > Well, Xilinx trust too much on Windows! > > I already checked with the Xilinx website and no answer was found for this > problem. I do find similar questions posted on other bbs but nobody > answered. > > Can anybody help? Thank you in advance. > > Steve I successfully used the USB cable to program my board, no troubles. Are you running with an old Windows version? Have you successfully used the USB for other things? Do you have Webpack installed on your machine? Wasn't there a checkbox to load USB drivers with Webpack or not?Article: 107767
John Larkin wrote: > On 27 Aug 2006 20:39:49 -0700, "rickman" <gnuarm@gmail.com> wrote: > >> Austin Lesea wrote: >>> To the subject at hand: placing additional caps across existing caps >>> does not reduce the noise (unless the dominant cause is lack of adequate >>> capacitance). >>> >>> The reason why the noise is bad is that the L (as in Ldi/dt) is most >>> likely the largest, and most dominant factor, in the form of the via and >>> traces to the bypass capacitor. >>> >>> Many times people have placed additional caps on top of the the existing >>> caps and wondered why the noise is not reduced: well, you did not >>> change the L in the equation, did you. So why did you expect V to change? >>> >>> You may have moved the resonant frequency (more often not), but often >>> people make the mistake of assuming that a 0.1uF requires a 0.01uF and a >>> 0.001uF in parallel. You can see that if the series L is dominant, you >>> haven't even moved the frequency by more than a few percent by the small >>> amount of additional capacitance. >> What do you think about the idea that if the caps are connected >> directly to good low impedance power planes that the location of the >> caps are not critical at all. I have been discussing this in >> comp.arch.embedded and have not gotten much negative feedback except >> some claim that more is always better and that multiple values are not >> needed. >> > > I sometimes add a few SMA connector footprints to multilayer boards so > I can TDR the planes. As near as I can measure with my Tek 20 GHz TDR, > on a bare VME-sized (6U) board, good parallel planes look like an > ideal capacitor, with no evidence of edge reflections or anything like > that. And as you load ceramic bypass caps *anywhere* on the board, the > value of the ideal cap increases. So it doesn't much matter where you > put bypass caps. > > The planes are a better cap than any discrete parts. Keep the > powerplane to ground dielectric thin, 5 mils or less, to keep the > plane capacitance high. > > John Have you verified that you can use a 50 ohm TDR to effectively measure impedance around 1 ohm and less? Measurements have been made by others that suggest your readings aren't telling you the whole story. It's possible the others are wrong and you're correct but it seems there are several sources suggesting that a 6U board will NOT look like an ideal capacitor without inductive or transmission line effects.Article: 107768
"John_H" <newsgroup@johnhandwork.com> ??????:_KOJg.13869$pX3.2025@trnddc07... > Ju, Jian wrote: >> Hi all, >> >> Recently I bought a Spartan 3E starter kit board and met some >> configuration problems. As indicated in the user guide for the board, it >> can be programmed by the USB cable shipped with the kit, (see user guide >> page 28). However, it seems the programming via the USB does not work and >> the driver software on the PC side is not properly installed, although >> the user guide says the "windows OS should recognized and install the >> associated driver software". Well, Xilinx trust too much on Windows! >> >> I already checked with the Xilinx website and no answer was found for >> this problem. I do find similar questions posted on other bbs but nobody >> answered. >> >> Can anybody help? Thank you in advance. >> >> Steve > > I successfully used the USB cable to program my board, no troubles. > Are you running with an old Windows version? --- I tried on both Windows XP SP2 and Windows 2000 SP4 > Have you successfully used the USB for other things? --- The PC can detect the plug-in of the USB device but it indicates the driver is not installed. So I think the USB cable should be ok. > Do you have Webpack installed on your machine? --- The webpack is successfully installed on my PC and I updated it to 8.1.03i by installing the ISE service pack (8_1_03i_win.exe) on the Xilinx download center. > Wasn't there a checkbox to load USB drivers with Webpack or not? --- No checkbox appear when I plug in the USB cable.Article: 107769
In article <1157079057.922443@nsserver1.polyu.edu.hk>, Ju, Jian <eejju@polyu.edu.hk> wrote: > Hi all, > > Recently I bought a Spartan 3E starter kit board and met some configuration > problems. As indicated in the user guide for the board, it can be programmed > by the USB cable shipped with the kit, (see user guide page 28). However, it > seems the programming via the USB does not work and the driver software on > the PC side is not properly installed, although the user guide says the > "windows OS should recognized and install the associated driver software". > Well, Xilinx trust too much on Windows! When I first started using the same board, it went through a lot of iterations of installing first one USB driver (that it found on the internet somewhere), then another, then back to the first.... Eventually it settled down. Now it works pretty well, except that about once a day the ISE trashes the .ise file and I have to recover from a copy. -- David M. Palmer dmpalmer@email.com (formerly @clark.net, @ematic.com)Article: 107770
I just tried using another USB cable, it works. Although it's weird, I can work on the project now. Thanks for all your help. "John_H" <newsgroup@johnhandwork.com> ??????:_KOJg.13869$pX3.2025@trnddc07... > Ju, Jian wrote: >> Hi all, >> >> Recently I bought a Spartan 3E starter kit board and met some >> configuration problems. As indicated in the user guide for the board, it >> can be programmed by the USB cable shipped with the kit, (see user guide >> page 28). However, it seems the programming via the USB does not work and >> the driver software on the PC side is not properly installed, although >> the user guide says the "windows OS should recognized and install the >> associated driver software". Well, Xilinx trust too much on Windows! >> >> I already checked with the Xilinx website and no answer was found for >> this problem. I do find similar questions posted on other bbs but nobody >> answered. >> >> Can anybody help? Thank you in advance. >> >> Steve > > I successfully used the USB cable to program my board, no troubles. > Are you running with an old Windows version? > Have you successfully used the USB for other things? > Do you have Webpack installed on your machine? > Wasn't there a checkbox to load USB drivers with Webpack or not?Article: 107771
Symon wrote: >> What happens if I turn on the on-chip terminating >> resistors with a bank voltage of 3.3V? I'm assuming that the resistance >> value will then be in question. >> > I think the software will stop you doing this. No, it will not. You will not even get a warning message, at least not unless you turn on (even) more verbose reports. But Jim Wu's excellent "ADEPT"-Tool (see http://home.comcast.net/~jimwu88/tools/) will at least tell you you shouldn't be doing this. And yes, the termination value will be in question. Noone at Xilinx can tell you what that value might be; they haven't charcterized it, since they don't recommend using it in this way. cu, SeanArticle: 107772
In message <D4LJg.5081$yO7.4612@newssvr14.news.prodigy.com>, dated Fri, 1 Sep 2006, Joerg <notthisjoergsch@removethispacbell.net> writes >That's a common misconception even among professional translators. They >think that you don't need to be an engineer to translate technical >stuff. REALLY professional translators ask for help on the translators' newsgroup. Most of its traffic is about queries on technical terms. -- OOO - Own Opinions Only. Try www.jmwa.demon.co.uk and www.isce.org.uk 2006 is YMMVI- Your mileage may vary immensely. John Woodgate, J M Woodgate and Associates, Rayleigh, Essex UKArticle: 107773
Hi, Can I use Block RAM for data storage in a system involving micro-controller which writes into Block RAM as a buffer? I am bothered about the timing as 8051 does not have data clock combination as is required by block RAM. Or Block RAM is just for local FPGA starage?Article: 107774
from XILINX: - Switching regulators can be used up to 3.12 with extensive passive filtering, for higher frequencies linears should be used. - Unused MGT do need power supply but no filtering, actually they can be powered from the FPGA core supply. - I still have no answer on how much current unused MGTs need heiner
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