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Peter Alfke wrote: > See the data sheet on the Xilinx website. Why can't we get the errata as simple as the datasheet ?. Seems crucial for ES devices. Karl.Article: 108901
Hello.
I am currently implementing a Microblaze system with 2 external
interrupts. Let us call them bus_reset_INTR and opb_intc_0_Intr_pin .
Now earlier I had written some code to include only opb_intc_0_Intr_pin
and it worked perfectly fine. The code is given below:
XIntc_Initialize(&InterruptController, XPAR_OPB_INTC_0_DEVICE_ID);
microblaze_enable_interrupts();
XIntc_Connect(&InterruptController,
DEVICE_INTERRUPT_ID,(XInterruptHandler)PacketParser,(void *)0);
XIntc_Start(&InterruptController, XIN_REAL_MODE);
XIntc_Enable(&InterruptController, DEVICE_INTERRUPT_ID);
XIntc_Initialize(&InterruptController, XPAR_OPB_INTC_0_DEVICE_ID);
void PacketParser()
{
//BLAH
}
The MHS/MSS files were straight forward.
//MHS
//BLAH
PORT npa_INTR = INTR, VEC = [0:0], DIR = I, SIGIS = INTERRUPT,
SENSITIVITY = EDGE_RISING
BEGIN microblaze
PARAMETER INSTANCE = microblaze_0
PARAMETER HW_VER = 4.00.a
PARAMETER C_USE_FPU = 1
PARAMETER C_INTERRUPT_IS_EDGE = 1
PARAMETER C_USE_BARREL = 1
PARAMETER C_USE_DIV = 1
BUS_INTERFACE DLMB = dlmb
BUS_INTERFACE ILMB = ilmb
BUS_INTERFACE DOPB = mb_opb
BUS_INTERFACE IOPB = mb_opb
PORT CLK = sys_clk_s
PORT INTERRUPT = microblaze_0_INTERRUPT
END
BEGIN opb_intc
PARAMETER INSTANCE = opb_intc_0
PARAMETER HW_VER = 1.00.c
PARAMETER C_IRQ_IS_LEVEL = 0
PARAMETER C_BASEADDR = 0x41200000
PARAMETER C_HIGHADDR = 0x4120ffff
BUS_INTERFACE SOPB = mb_opb
PORT OPB_Clk = sys_clk_s
PORT Intr = INTR
PORT Irq = microblaze_0_INTERRUPT
END
Now when I include bus_reset_INTR in my design, everything collapses.
Both interrupts aren't detected by the processor. The C code for this
new hardware is:
XIntc_RegisterHandler(XPAR_OPB_INTC_0_BASEADDR,
XPAR_OPB_INTC_0_DCAM_SUPREMO_13_BUS_RESET_INTR_INTR,
(XInterruptHandler)BusReset, (void *)0);
XIntc_RegisterHandler(XPAR_OPB_INTC_0_BASEADDR,
XPAR_OPB_INTC_0_DCAM_SUPREMO_13_OPB_INTC_0_INTR_PIN_INTR,
(XInterruptHandler)PacketParser, (void *)0);
XIntc_mMasterEnable(XPAR_OPB_INTC_0_BASEADDR);
microblaze_enable_interrupts();
void PacketParser()
{
//BLAH
}
void BusReset()
{
//BLAH
}
The modified MHS is:
PORT opb_intc_0_Intr_pin = opb_intc_0_Intr, DIR = I, VEC = [0:0],
SIGIS = INTERRUPT, SENSITIVITY = EDGE_RISING
PORT bus_reset_INTR = bus_reset_L, DIR = I, SIGIS = INTERRUPT,
SENSITIVITY = EDGE_RISING, VEC = [0:0]
//BLAH
BEGIN microblaze
PARAMETER INSTANCE = microblaze_0
PARAMETER HW_VER = 4.00.a
PARAMETER C_USE_FPU = 0
PARAMETER C_USE_DIV = 1
PARAMETER C_INTERRUPT_IS_EDGE = 1
BUS_INTERFACE DLMB = dlmb
BUS_INTERFACE ILMB = ilmb
BUS_INTERFACE DOPB = mb_opb
BUS_INTERFACE IOPB = mb_opb
PORT CLK = sys_clk_s
PORT INTERRUPT = opb_intc_0_Irq
END
BEGIN opb_intc
PARAMETER INSTANCE = opb_intc_0
PARAMETER HW_VER = 1.00.c
PARAMETER C_NUM_INTR_INPUTS = 2
PARAMETER C_IRQ_IS_LEVEL = 0
PARAMETER C_BASEADDR = 0x41200000
PARAMETER C_HIGHADDR = 0x4120ffff
BUS_INTERFACE SOPB = mb_opb
PORT Irq = opb_intc_0_Irq
PORT Intr = opb_intc_0_Intr&bus_reset_L
END
And my MSS file reads:
PARAMETER VERSION = 2.2.0
PARAMETER int_handler = PacketParser, int_port = opb_intc_0_Intr_pin
PARAMETER int_handler = BusReset, int_port = bus_reset_INTR
//BLAH
Now I am wondering where the problem could lie. If someone could help
me make this work, then that would be great!!!
Thanks
Viswanathan
Article: 108902Jim Granville schrieb: > betterone11@gmail.com wrote: > > fpgaman wrote: > > > >>"http://www.latticesemi.com/products/intellectualproperty/latticemico32" > > finally - a 100% Eclipse-+GNU based SoC system with open-source RTL that just works. AnttiArticle: 108903
Hi all.
I'm using ISE 8.1.03i EDK 8.1.02i
I have found the header file "mb_interface.h" and it seems to be perfect for my goal. I have to read internal uBlaze registers.
In the header file there are some pseudo assembler macro to do it.
For example: #define mfmsr()...
I'm not sure if to get the unsigned int value returned is enough to call a xil_printf(), like xil_printf("mfmsr=0x%x\r\n", mfmsr());. In fact I got always 0 like return value...
Please any suggestion?
Thanks in advace.
Cheers, Alfmyk.
Article: 108904Antti wrote: > Jim Granville schrieb: > > > betterone11@gmail.com wrote: > > > fpgaman wrote: > > > > > >>"http://www.latticesemi.com/products/intellectualproperty/latticemico32" > > > > finally - a 100% Eclipse-+GNU based SoC system with open-source RTL > that just works. Have you used it yet? Cheers, JonArticle: 108905
Hi all. I'm using EDK 8.1.02i and I'm programming uBlaze. I have seen that related to uBlaze configuration (HW/SW FPU, Barrel shifter ON/OFF, and so on...) there are different directives to inform compiler.Example "-mhard-float" (using HW floating point). My question: these type of directives are ONLY for target (I mean used) that is for the linker command or the directives are also used in compiling time? I mean obj code are different if different are condition of "-m<..>" ? For me is important to know if I must use this compile setting also in my external library. Thanks in advance. Cheers, Alfmyk.Article: 108906
Jon Beniston schrieb: > Antti wrote: > > Jim Granville schrieb: > > > > > betterone11@gmail.com wrote: > > > > fpgaman wrote: > > > > > > > >>"http://www.latticesemi.com/products/intellectualproperty/latticemico32" > > > > > > finally - a 100% Eclipse-+GNU based SoC system with open-source RTL > > that just works. > > Have you used it yet? > > Cheers, > Jon I started the Eclipse based builder, made a project generated the RTL it was blazing fast and easy. The IP cores are described in XML, the generated source code is plain verilog, the compiler toolchain is GCC based, I see no reasons why it would not work. Its not so hard to make things that work actually. I havent yet tested it - I do not own any Lattice boards with some largish FPGA - I was about to buy from private money for my collection the LatticeSC PCIe single lane eval board - but unfortunatly it is not yet available for purchases. So I possible have make some wrappers around Xilinx primitives and check it out on Xilinx FPGA. I opened the proect in ISE project navigator it all looks eays and understandable. GSR, ADDSUB and EBR components from Lattice libraries should be substituted then I guess it would synthesize. Lattice I would love to test LM32 out on Lattice silicon, but see above the only board I was/am ready to buy isnt available. After ECP2/M announce I maybe will wait up ECP2/M PCIe board, or XP2 board. AnttiArticle: 108907
Jim, > Jim Granville wrote: >> I think you are asking about moving the DSP into the FPGA That's right. >> but we have no info on important details like: Well, my aims are to get into SoC and replace MCUs/DSPs, where applicable, in the long term. I do not intend to replace a particular DSP in a particular existing design at the moment. Thanks, Markus -- Markus Fuchs - http://www.yeahware.comArticle: 108908
> Guru wrote: >> An affordable and VERY compact solution is a Avnet Virtex-4FX12 >> MiniModule with a PowerPC, Giga LAN, 64MB DDR, 4MB flash and a price of >> 250$. There might be also enough logic for a simple DSP to preprocess >> data for a final processing in the PPC. This looks interesting. Looks like a really competitive price indeed. Thanks, Markus -- Markus Fuchs - http://www.yeahware.comArticle: 108909
On Mon, 18 Sep 2006 14:50:42 -0700, David Ashley <dash@nowhere.net.dont.email.me> wrote: >Mostly for xilinx people, > >xapp802 Xilinx XAPP802 Virtex Series Memory Interface Application Notes >Available here: >http://www.xilinx.com/bvdocs/appnotes/xapp802.pdf#search=%22xilinx%20ddr%20fae%22 > >On page 3 is figure 2. There is an FDDR shown on the diagram that has >left and right data going into the D0 and D1 inputs, but both clocks >are coming from the same source (CLK0 from the DCM). Shouldn't >C1 be coming from the CLK180? Notice the clock inversion circle on one of the clock input pins. (I hope Xilinx explain their schematic conventions somewhere - not everyone still has those fat orange (sorry Peter - red) books on their shelves!) - BrianArticle: 108910
On Tue, 19 Sep 2006 01:55:58 -0700, Alfmyk <alfmyk@hotmail.com> wrote: >Hi all. > >I'm using EDK 8.1.02i and I'm programming uBlaze. > >I have seen that related to uBlaze configuration (HW/SW FPU, Barrel shifter ON/OFF, and so on...) there are different directives to inform compiler.Example "-mhard-float" (using HW floating point). My question: these type of directives are ONLY for target (I mean used) that is for the linker command or the directives are also used in compiling time? I mean obj code are different if different are condition of "-m<..>" ? For me is important to know if I must use this compile setting also in my external library. > >Thanks in advance. > >Cheers, Alfmyk. It is really important for the compiler and assembler. That is the main reason why Xilinx has been forced to create an automatic system to recompile all system libraries whenerver hardware changes (apart form the interrupt mapping). Regards, ZaraArticle: 108911
hi all, i'm doing a research about " E1 to Ethernet conversion" can any one suggest books or papers to read?? thanksArticle: 108912
bart schrieb: > thanks for the heads up. i've notified the Lattice store. the mico32 > development kit should be up on the store later today. rgds, bart, > Lattice > > The LatticeMico32 Development Kit is available now and is priced at > $995. The Kit includes both the ispLEVER design tools, regularly priced > at $695, and the development board, which as a stand-alone is priced at > $595. > > Looks like the web store is a little slower in the loop... and..Any plans for uClinux on Mico32? AnttiArticle: 108913
Hi Mikhai, Thanks. I tried but it doesn't work either. /Wayne MM wrote: > > I installed chipscope 8.1i instead of 8.2i. but It's the same. > > > > Make sure you rebuild everything. If you work entirely in XPS environment do > Hardware/Clean Hardware before rebuilding. > > /MikhailArticle: 108914
ITU-T G.703, G.704 IEEE 802.3 HTH, Syms "sherine" <en.sherine@gmail.com> wrote in message news:1158664186.952407.165290@k70g2000cwa.googlegroups.com... > hi all, i'm doing a research about " E1 to Ethernet conversion" can any > one suggest books or papers to read?? thanks >Article: 108915
Ok, thank you for your answer Zara. So I suppose that if I have to use Xfloat32 or Xfloat64 in my library module it's very important compile library with these directives... And now I understand better why when a add a simple float in my library the code became so bigger... Ok, now I retest adding directives. Thanks.Article: 108916
I can make you whatever you want! rickman wrote: > Well thanks for the answer. I have been out looking for an eval board > for the XPLA3 and I am having trouble finding a decent one. Digilent > has one with a "solderless breadboard" which is pretty pointless these > days. Otherwise, the only one I can find has to be ordered from India. > I was hoping the one listed on the Xilinx web site as being from Avnet > was available, but I can find neither hide nor hair yet. > > http://www.xilinx.com/xlnx/xebiz/designResources/ip_product_details.jsp?sSecondaryNavPick=BOARDS&key=ADS-XLX-X3-EVL&sGlobalNavPick=PRODUCTS&BV_SessionID=@@@@2132332454.1158622903@@@@&BV_EngineID=cccjaddikmdkkjhcefeceihdffhdfkf.0 > > > Peter Alfke wrote: > >>I checked with our CPLD folks in Xilinx, and here is their answer: >> >>"Absolutely no planned obsolescence for XPLA3. >>We never made a widely circulated XPLA3 development board that >>we sold. We had a few hundred that we gave away. >>XPLA3 has gained significant volume, with design wins in >>handheld computers etc. It has also been designed in at a major >>consumer house. >>It will be around for quite a while. >>The single 3.3V power supply has been a big plus for it." >> >>Peter Alfke >>=============================== >>rickman wrote: >> >>>I am looking at using the XPLA3 in a new design and am having trouble >>>finding an evaluation board. So I started looking around and see that >>>Xilinx seems to be severely curtailing support of these parts. There >>>Xilinx no longer offers evaluation boards and I can't find many third >>>party boards that are still offered. >>> >>>On the bright side, when I did a search at Nuhorizons for XCR3128, I >>>got lots of hits. That alone would not give me confidence, but not >>>only did I get the XCR3128XL that I need to use, I found the XCR3128 >>>without the XL which is an even older part. If they are still selling >>>those parts, I guess I can expect to see the XCR3128XL around for quite >>>a while. >>> >>>The Coolrunner II may be a bit lower power, but the XPLA3 parts are >>>nearly as low power for our application and only require a single power >>>voltage. That makes them *more* power efficient. I just wish Xilinx >>>provided as much support for the XPLA3 parts as they do for the >>>Coolrunner II. >>> >>>Are there any advantages of the Coolrunner II parts that I am missing? >>>I see they have input hysteresis, but otherwise they seem pretty much >>>the same as the Coolrunner XPLA3. > >Article: 108917
Hi there, Selecting DA or MAC fir in xilinx FPGA depends of: - your target (e.g. if you have an FPGA with hardware multipliers). - the output frequency of your FIR. Typically, if you have the "chance" to use an FPGA with embedded multipliers, you should prefer mac fir to avoid large silicon loss due to Distributed Arithmetic implementation. In some case D.A is preferable to improve the throughput of your fir (e.g if you don't have enough multipliers, the clock speed falls...) best regards David jalaram wrote: > please tell me which one core is more suitable fot digital > implementation , which are available in ISE. > DA or MAC. > Regards > J.RAm >Article: 108918
John Adair wrote: > Craignell family are are a set of DIL style 5V tolerant modules based on > Spartan-3E. Mainly aimed at obsolete component replacement they can also be > used for hobby electronics due to their mechanical pitch. I should have said > there are actually 3 members of this family to release supporting DIL28, > DIL32 and DIL40. > > John Adair > Enterpoint Ltd. - Home of Broaddown4. The Ultimate Virtex-4 Development > Board. > http://www.enterpoint.co.uk > > "Simon" <news@gornall.net> wrote in message > news:2006091710251416807-news@gornallnet... > > On 2006-09-17 01:03:05 -0700, "John Adair" <g1@enterpoint.co.uk> said: > > > >> Did you mean the Tarfessock1? > >> > >> We have slipped a little due to the amount of customer work that has > >> come in over the summer but will like be available in approximately 3-4 > >> weeks. Our main limitation is the arrival of the cardbus frames and > >> covers which we are waiting for. > > > > No, I meant the Darnaw1 (S3S1200E module, yes ?) - it's for a different > > project than the V4FX board :-) > > > >> Darnaw1 and Craignell1/2 are roughly on the same timescale. > > > > I'm assuming the casual mention of a completely unknown (at least to me, > > and I can't find it on your site :-) board is a marketing ploy designed to > > tease out the question: "What is Craignell1 and 2 ?". Ok then [grin], > > dish! > > > > Simon > > Any info on the Craignell boards would be nice. Will these have built-in platform flash?Article: 108919
Why there is such a limitation. Why cant we pass a rest to all ram cells. Please advice me. Thanks and regards Sumesh V SArticle: 108920
> Thanks. I tried but it doesn't work either. Post your MHS file... /MikhailArticle: 108921
vssumesh wrote: > Why there is such a limitation. Why cant we pass a rest to all ram > cells. Please advice me. > Thanks and regards > Sumesh V S > The reason is the silicon does not support it, there is no reset line that clears the RAM. The reason it is not designed into the silicon is that adding a reset just about doubles the size of a RAM cell, plus requires a very high fan-out signal. The area and speed implications are both strong disincentives to including a reset that clears the whole array at once.Article: 108922
jalaram wrote: > please tell me which one core is more suitable fot digital > implementation , which are available in ISE. > DA or MAC. > Regards > J.RAm > Both are suitable for digital implementation. Which one you use depends on your application. MAC filters require multipliers, and for large filters, the number of multpliers can be prohibitive. DA filters hide the multiplications in small tables of partial products, which allows a large number of filter taps in a small amount of logic. The disadvantage is the DA filters either require a multiplied clock or need to be duplicated once for each bit in the input. A full parallel DA circuit gets to be close to the area of a MAC circuit constructed withoug the benefit of the embedded multipliers.Article: 108923
Brian Drummond wrote: > > Notice the clock inversion circle on one of the clock input pins. > > (I hope Xilinx explain their schematic conventions somewhere - not > everyone still has those fat orange (sorry Peter - red) books on their > shelves!) > > - Brian > The inversion bubble is an IEEE standard.Article: 108924
For $200? I can make a board too... in fact, that is what I am going to do right after I evaluate the three CPLD candidates. Eli Hughes wrote: > I can make you whatever you want! > > > > rickman wrote: > > Well thanks for the answer. I have been out looking for an eval board > > for the XPLA3 and I am having trouble finding a decent one. Digilent > > has one with a "solderless breadboard" which is pretty pointless these > > days. Otherwise, the only one I can find has to be ordered from India. > > I was hoping the one listed on the Xilinx web site as being from Avnet > > was available, but I can find neither hide nor hair yet. > > > > http://www.xilinx.com/xlnx/xebiz/designResources/ip_product_details.jsp?sSecondaryNavPick=BOARDS&key=ADS-XLX-X3-EVL&sGlobalNavPick=PRODUCTS&BV_SessionID=@@@@2132332454.1158622903@@@@&BV_EngineID=cccjaddikmdkkjhcefeceihdffhdfkf.0 > > > > > > Peter Alfke wrote: > > > >>I checked with our CPLD folks in Xilinx, and here is their answer: > >> > >>"Absolutely no planned obsolescence for XPLA3. > >>We never made a widely circulated XPLA3 development board that > >>we sold. We had a few hundred that we gave away. > >>XPLA3 has gained significant volume, with design wins in > >>handheld computers etc. It has also been designed in at a major > >>consumer house. > >>It will be around for quite a while. > >>The single 3.3V power supply has been a big plus for it." > >> > >>Peter Alfke > >>=============================== > >>rickman wrote: > >> > >>>I am looking at using the XPLA3 in a new design and am having trouble > >>>finding an evaluation board. So I started looking around and see that > >>>Xilinx seems to be severely curtailing support of these parts. There > >>>Xilinx no longer offers evaluation boards and I can't find many third > >>>party boards that are still offered. > >>> > >>>On the bright side, when I did a search at Nuhorizons for XCR3128, I > >>>got lots of hits. That alone would not give me confidence, but not > >>>only did I get the XCR3128XL that I need to use, I found the XCR3128 > >>>without the XL which is an even older part. If they are still selling > >>>those parts, I guess I can expect to see the XCR3128XL around for quite > >>>a while. > >>> > >>>The Coolrunner II may be a bit lower power, but the XPLA3 parts are > >>>nearly as low power for our application and only require a single power > >>>voltage. That makes them *more* power efficient. I just wish Xilinx > >>>provided as much support for the XPLA3 parts as they do for the > >>>Coolrunner II. > >>> > >>>Are there any advantages of the Coolrunner II parts that I am missing? > >>>I see they have input hysteresis, but otherwise they seem pretty much > >>>the same as the Coolrunner XPLA3. > > > >
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