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Messages from 108825

Article: 108825
Subject: Re: What resources do the Xilinx tools require on a PC?`
From: "PeteS" <PeterSmith1954@googlemail.com>
Date: 17 Sep 2006 14:24:30 -0700
Links: << >>  << T >>  << A >>
rickman wrote:
> Nico Coesel wrote:
> > "rickman" <gnuarm@gmail.com> wrote:
> >
> > >I checked on the web page for the Xilinx tools and this is what I
> > >found...
> > >
> > >"The memory requirements for both RAM and hard disk space will vary
> > >depending on your target device family and size as well as the unique
> > >characteristics of your design. "
> > >
> > >Anyone have an idea of how much hard drive space is needed for the full
> > >toolset?  I don't get why they don't provide some sort of figure either
> > >a base or a maximum.  I guess if you have to ask, you don't have enough
> > >space?
> >
> > Count on 1GB of hard drive space for the Xilinx ISE software. A P4
> > with 512MB memory is enough.
>
> I got it to work with about 4 GB of free disk space after it failed
> with over 2 GB of free space.  I watched the HD usage as it installed
> and the high water mark seemed to be about 3.25 GB.  The final storage
> used is about 2.25 GB.  This was WebPack ver 8.1.

If you are going to be working with anything above the -200 mark (as in
XC3S200), figure on 1GByte memory for reasonable response, particularly
for sims.

I had to reinstall once I started telecommuting, but I was installing
on a 200GByte second drive, so space didn't seem to be an issue :)

Cheers

PeteS


Article: 108826
Subject: Re: Board Opinions TS7300
From: "John Adair" <g1@enterpoint.co.uk>
Date: 17 Sep 2006 15:29:02 -0700
Links: << >>  << T >>  << A >>
Most people on the group are usually fairly helpful if not faced by
silly questions. You my been unluckly last time with responders.

If you are looking at doing things like ethernet or processors then you
do want to watch the size of part you want. Simple uarts don't take
much usually. If you want to compare Xilinx and Altera part sizes then
I usually convert both in flip-flops and luts as a first line
comparative measure and then weigh up the minor details.

Sometimes parts like the Virtex-4 FX12 distort the equation. We use
this in customer products because it has a PowerPC and 2 gigabit MACs
as hard logic with a reasonable balance of FPGA logic left for anything
else. It is one the best value parts outside the Spartan etc arena and
doesn't cost a fortune.

Some of the silicon vendors like Xilinx have datsheets for IP that
indicate size so worth looking them up to get an idea of what you might
need. As usual play safe and add a margin to whatever numbers you find.

John Adair
Enterpoint Ltd.

ziggy wrote:
> In article <1158478826.601785.144780@b28g2000cwb.googlegroups.com>,
>  "John Adair" <g1@enterpoint.co.uk> wrote:
>
> > The Altera 2C8 that is on that board is relatively small. I have not
> > found an accurate size for Leon but it is likely to use a large
> > percentage of that chip.
> >
> > There also appears to be a very limited I/O capability in/out of the
> > FPGA.
> >
> > Both factors will limit any SOC projects.
> >
> > If it is mainly a FPGA you want out of a board then there is a list of
> > boards here http://www.fpga-faq.com/ including our own products. This
> > list isn't totally comprehensive but is the best I have seen in one
> > place.
> >
> > Alternatively tell the group what attracts you to the board you started
> > looking at and someone may suggest a better match for your
> > requirements.
> >
> > John Adair
> > Enterpoint Ltd.
> >
> > ziggy wrote:
> > > Ran across this board the other day, was wondering if anyone has any
> > > experiences with it, good or bad.
> > >
> > > Also, not really being too experiences in sizing yet, would something
> > > like this be big enough for a complete system, using a leon sparc or
> > > similar sized core?
> > >
> > > it seems to have the basic features i want, ethernet, vga, serial, ram,
> > > reasonable cost, etc.. But if it is too small to be useable for SOC type
> > > projects, it wont help me much.
> > >
> > > http://www.embeddedarm.com/epc/ts7300-spec-h.htm
>
> Tks, ill steer clear due to its size. I have learned to recognize xilinx
> sizes, but not altera.  If it wont comfortably fit a leon ( the largest
> plan i have ) + support cores then it wont be of much good even if it
> did have ethernet and CF. ( plus the standard, VGA, serial, ram )
>
> While asking the group sounds like a good idea, the last time i tried
> something like that around here i was told to goto hell and do it myself.


Article: 108827
Subject: Re: Spartan3: Multiplier Madness
From: "alterauser" <fpgaengineerfrankfurt@arcor.de>
Date: 17 Sep 2006 16:45:05 -0700
Links: << >>  << T >>  << A >>
Can't you use a multi cycle constraint ?


Article: 108828
Subject: Re: SSFP16 GPL licensed 16 Fpga processor released
From: avionion@gmail.com
Date: 17 Sep 2006 18:07:38 -0700
Links: << >>  << T >>  << A >>
Here is ttranslation :
" in the last weeks a small RISC processor sketched.     A few data:  -
described completely in VHDL  - Harvard architecture  - 16-bit data
capacity (other one at something expenditure naturally possible) -
16-bit of instructions  - optimizes for Spartan 3 (a few
Instanziierungen)  - internal command Rome (max. 2^16 of instructions =
128 KB)  - internal and external RAM, per max. 64 KB  - separate I/O  -
Multipliers signed/unsigned  - Dividierer unsigned pipelined (17 clocks
with 16 bits data capacity) - interrupt input  - Parity checks for
internal RAM and ROM (goes if necessary on external interrupt
CONTROLLERs)  - altogether not pipelined (fetch, decode and execute
with nearly all instructions in a clock)  - Clock frequency with
Spartan 3, class of data signaling rates 4:50 - 60 MHz - approx. 200
Slices without periphery, at least 3 BRAM and 1 multiplier.    For it I
would have to offer an assembler (programs in C) and a simple
debugger/simulator (programs in Java).    If here serious interest
exists, I would make myself the trouble, few pages a Doku would
arrange. If not, I can save those; -).    Of course everything free of
charge for non-commercial purposes and without each warranty.    For a
first impression I attached times the command set. "
ziggy wrote:
> In article <1158485668.999811.326430@e3g2000cwe.googlegroups.com>,
>  "Antti" <Antti.Lukats@xilant.com> wrote:
>
> > Hi,
> >
> > the original announcement is at the bottom of the thread there
> >
> > http://www.mikrocontroller.net/forum/read-9-411815.html#new
> >
> > or the direct download link
> >
> > http://www.mikrocontroller.net/attachment.php/418674/Ssfp16_1.0.zip
> >
> > all the documentation is in german only at the moment,
> > but it should be still useable - the download archive includes
> >
> > vhdl files
> > example toplevel and ucd for Digilent S3 starterkit
> > assembler (with C sources)
> > simulator (in java)
> > script to use data2mem for rom initialization
> > documentation
> >
> > there is no ISE project, so new project must be made, then just add all
> > vhdl files. on my test build the UCF caused errors on timing
> > constraints and bram loc constrains, after removing them the build was
> > succesful.
> >
> > for succesful data2mem script merging the UCF-BMM must match or the
> > data2mem will not be able to init the bitstream correctly so that may
> > have to be fixed manually, otherwise is the project ready to go for S3
> > starterkit.
> >
> > and size - just for testing I synthesized for S3-50:
> > used slices 43%
> > not bad for an 16 bit processor.
> >
> > Antti
>
> Any ETA on translations for us over here in the us that never learned
> another language?


Article: 108829
Subject: A strange problem of Chipscope
From: quickwayne@gmail.com
Date: 17 Sep 2006 18:19:54 -0700
Links: << >>  << T >>  << A >>
Hello,

I am trying to design a multiprocessor system for my master project.
Chipscope is necessary to debug the system. But I got a strange problem
when I synthesize my design in EDK. It says,

ERROR:MDT - ERROR FROM TCL:- chipscope_opb_iba_0 (chipscope_opb_iba) -
Release

At the end of the report, it says,

       while executing
   "exec xst -ifn $xst_scr_filename"
       (procedure "synthesize_cs_edk_port_mapper_core" line 55)
       invoked from within
   "synthesize_cs_edk_port_mapper_core $param_table"
       (procedure "::hw_chipscope_opb_iba_v1_01_a::opb_iba_generate"
line 95)
       invoked from within
   "::hw_chipscope_opb_iba_v1_01_a::opb_iba_generate 38052152"
ERROR:MDT - platgen failed with errors!

The version of tools is EDK 8.1.02i, ISE 8.1.03i, chipscope 8.2.02i.

Can you help me to figure out the problem? Thanks a lot.

/Wayne


Article: 108830
Subject: Re: Spartan3: Multiplier Madness
From: Bob Perlman <bobsrefusebin@hotmail.com>
Date: Sun, 17 Sep 2006 18:29:27 -0700
Links: << >>  << T >>  << A >>
On 15 Sep 2006 11:33:56 +0200, "Symon" <symon_brewer@hotmail.com>
wrote:

>"James Morrison" <spam1@emorrison.ca> wrote in message 
>news:1158283978.4061.39.camel@spice.emorrison.ca...
>> uing.  So it was using the unsigned library!  Needless to say, that
>> didn't work too well.  I changed to using the signed library and it
>> worked fine.
>>
>> Cheers,
>>
>> James.
>>
>>
>Hi James,
>
>Only a multiplier madman would use other than numeric.std ! :-)
>
>You might find Jim Lewis's excellent paper useful, I know I do.
>
>http://www.synthworks.com/papers/vhdl_math_tricks_mapld_2003.pdf

Thanks for the pointer to the paper, Symon.  

MAPLD always has some interesting presentations.  One of these days
I'm going to attend, provided my cheap boss will pay for the trip.

Bob Perlman
Cambrian Design Works
http://www.cambriandesign.com

Article: 108831
Subject: Re: uclinux on spartan-3e starter kit
From: "Todd Fleming" <tbfleming@gmail.com>
Date: 17 Sep 2006 19:06:29 -0700
Links: << >>  << T >>  << A >>
Antti,

Is there somewhere I can download the source for this?  I'd like to
modify it to drop its xil dependancy:

/cygdrive/f/hw/mbgcc/bin/../lib/gcc/microblaze/3.4.1/../../../../microblaze/bin/ld:
cannot find -lxil

Thanks,
Todd

Antti wrote:
> For those who want to use GPL tools to compile MicroBlaze 5.0
> applications on WinXP platform here is the cygwin compiled MicroBlaze
> toolchain from EDK 8.2 release.
>
> http://www.xilant.com/downloads/mb_gnu_8_2.zip
>
> I have only tested it to succesfully compile MicroBlaze u-boot, so the
> toolchain is working at least.
> 
> Antti Lukats


Article: 108832
Subject: Re: A strange problem of Chipscope
From: "Weng Tianxiang" <wtxwtx@gmail.com>
Date: 17 Sep 2006 19:36:01 -0700
Links: << >>  << T >>  << A >>

quickwayne@gmail.com wrote:
> Hello,
>
> I am trying to design a multiprocessor system for my master project.
> Chipscope is necessary to debug the system. But I got a strange problem
> when I synthesize my design in EDK. It says,
>
> ERROR:MDT - ERROR FROM TCL:- chipscope_opb_iba_0 (chipscope_opb_iba) -
> Release
>
> At the end of the report, it says,
>
>        while executing
>    "exec xst -ifn $xst_scr_filename"
>        (procedure "synthesize_cs_edk_port_mapper_core" line 55)
>        invoked from within
>    "synthesize_cs_edk_port_mapper_core $param_table"
>        (procedure "::hw_chipscope_opb_iba_v1_01_a::opb_iba_generate"
> line 95)
>        invoked from within
>    "::hw_chipscope_opb_iba_v1_01_a::opb_iba_generate 38052152"
> ERROR:MDT - platgen failed with errors!
>
> The version of tools is EDK 8.1.02i, ISE 8.1.03i, chipscope 8.2.02i.
>
> Can you help me to figure out the problem? Thanks a lot.
>
> /Wayne

Hi,
The problem may be the different versions:
EDK 8.1.02i, ISE 8.1.03i, chipscope 8.2.02i.

They must be the same version: 8.1 or 8.2 and cannot be mixed. It is my
guess!

Weng


Article: 108833
Subject: Re: What resources do the Xilinx tools require on a PC?`
From: "rickman" <gnuarm@gmail.com>
Date: 17 Sep 2006 19:53:02 -0700
Links: << >>  << T >>  << A >>
rickman wrote:
> Nico Coesel wrote:
> > "rickman" <gnuarm@gmail.com> wrote:
> >
> > >I checked on the web page for the Xilinx tools and this is what I
> > >found...
> > >
> > >"The memory requirements for both RAM and hard disk space will vary
> > >depending on your target device family and size as well as the unique
> > >characteristics of your design. "
> > >
> > >Anyone have an idea of how much hard drive space is needed for the full
> > >toolset?  I don't get why they don't provide some sort of figure either
> > >a base or a maximum.  I guess if you have to ask, you don't have enough
> > >space?
> >
> > Count on 1GB of hard drive space for the Xilinx ISE software. A P4
> > with 512MB memory is enough.
>
> I got it to work with about 4 GB of free disk space after it failed
> with over 2 GB of free space.  I watched the HD usage as it installed
> and the high water mark seemed to be about 3.25 GB.  The final storage
> used is about 2.25 GB.  This was WebPack ver 8.1.

Opps, I mispoke.  This was ver 8.2 which seems to have a significantly
larger install file, so I assume it uses more disk space while
installing.


Article: 108834
Subject: ISE Simulator Error 222: SuSE 10.1 Linux
From: "gauckler" <gauckler@fh-furtwangen.de>
Date: 17 Sep 2006 23:49:25 -0700
Links: << >>  << T >>  << A >>
Hi,

i tried to simulate a small vhdl design with xilinx ISE (8.1 - 8.2
spxx, Webpack or foundation) running SuSE 10.1 linux, unfortunately
there is an error. Because the  VHDL code simulates  with SuSE 9.2  I
assume the code is fine and there are no spaces in the file path.

    Started : "Check Syntax".
    Running vhpcomp
    Compiling vhdl file "/home/PBuser2/parity/parity.vhd" in Library
isim_temp.
    Entity <parity> compiled.
    Entity <parity> (Architecture <behavior>) compiled.
    Compiling vhdl file "/home/PBuser2/parity/tb_parity.vhd" in Library
 isim_temp.
    Entity <tb_parity_vhd> compiled.
    Entity <tb_parity_vhd> (Architecture <behavior>) compiled.
    Parsing "tb_parity_vhd_stx.prj": 0.03

    Process "Check Syntax" completed successfully

   Running Fuse ...
   Parsing "tb_parity_vhd_beh.prj": 0.00
   Building tb_parity_vhd_isim_beh.exe
   ERROR:Simulator:222 - Generated C++ compilation was unsuccessful

Has anybody simulated ISE isim under SuSE 10.1.  Any hint is
appreciated.

Andreas


Article: 108835
Subject: Re: uclinux on spartan-3e starter kit
From: "Antti" <Antti.Lukats@xilant.com>
Date: 18 Sep 2006 00:36:09 -0700
Links: << >>  << T >>  << A >>
Todd Fleming schrieb:
> Antti,
>
> Is there somewhere I can download the source for this?  I'd like to
> modify it to drop its xil dependancy:
>
> /cygdrive/f/hw/mbgcc/bin/../lib/gcc/microblaze/3.4.1/../../../../microblaze/bin/ld:
> cannot find -lxil
>
> Thanks,
> Todd
>
Hi Todd,

try adding
-nostartfiles
to command line options, also look at XAPP482
the -lxil is the default xilinx runtime library what is created at EDK
system build time so the content of it depends on the system drivers
and options, those there is no source code of it. look at the lib srces
of any EDK project, there are the sources the libxil is made of. I
think most of those sources are also GPL (the are also part of uclinux
as example) so it is possible to have a 3rd party libxil I think by
using the GPL drivers and adding some small portion of runtime init
code

the binary mb-gcc that I made available is just 1:1 compile result of
the GPL licensed GNU GCC code from Xilinx website (EDK 8.2 release) -
that source code is available from Xilinx. You can recompile it
yourself or study the source code if you wish. The Xilinx source
compiles 'out of box' on WinXP/Cygwin - only change I had todo was the
default path to tcsh

one hint though, if you let cygwin to update your cygwin install it
renders EDK non functional. so after compiling mb-gcc goto cygwin/bin
and delete or rename make.exe

next start of XPS will copy make exe from EDK tree back into Cygwin bin
and everything will work again. there is an Xilinx AR about the make
incompatibility (eg the explanation why EDK doesnt work with latest
cygwin make)

Antti


Article: 108836
Subject: Re: microblaze startup problem
From: "sjulhes" <t@aol.fr>
Date: Mon, 18 Sep 2006 10:20:55 +0200
Links: << >>  << T >>  << A >>
We have identified the problem.

In fact it is due to the xx.bmm file use by data2mem.
EDK generates this file initialized with the software.

When ISE uses this file, we don't know why, but due to timing constraints 
ISE changes the block ram for the timing constraint implementation so ISE 
generates another xxx_bd.bmm file which is different from the one generated 
by EDK. So all the relevant software addresses are changed ( reset, jump to 
main, exception ... ) and the first intruction executed by the MB is bad and 
it crashes.

Does someone experienced such problems ?
Is there something to add in the constraints or some option to click in the 
ISE flow to avois this ?
Is it a Xilinx flow bug ??

Any feedback is welcome.

Thank you.

Stephane.

"Antti" <Antti.Lukats@xilant.com> a écrit dans le message de news: 
1158055377.500784.282240@h48g2000cwc.googlegroups.com...
sjulhes schrieb:

> Hello all,
>
> We are trying to design a small microblaze design in a spartan 3 and the
> problem we have is that the microblaze does not always start when the
> bitsream is downloaded with JTAG.
>
> But when we implement the debug module it always works.
>
> Does anyone has a clue ?
> Is it timing problems ? Is there specific timing constraints to add for
> microblaze ?
> Software problem ( linker script is automatically generated by edk)?
>
> Any idea is welcome.
>
> Thank you.
>
> Stéphane.

when it doesnt start use impact and read back the status word
look if GHIGH=1
(and that all other relevant bits are set properly)

Antti



Article: 108837
Subject: MPMC2 : npi issues #2
From: ivo <ivo@ideas.no>
Date: Mon, 18 Sep 2006 01:28:34 -0700
Links: << >>  << T >>  << A >>
This is a follow-up from my previous discussion. ivo, "MPMC2 : npi issues" #, 31 Aug 2006 1:44 am </cgi-bin/forum?50@@.ee9e44c>

I am now able to get addrAck back from the MPMC2, but it seems like the FIFO never dumps data to the DDR. After a number of acks (depending on the size of the FIFO) followed by WrFIFO_push the FIFO_almostfull signal is asserted and no more acks are received. The FIFO_almostfull signal never goes low again.

Someone have an idea what is wrong ? I assume that my npi never gets prioritized by the arbiter, but my arbiter algorithm is quite simple(round robin). The PPC which is also attached onto the MPMC2 works as expected.

Article: 108838
Subject: Re: microblaze startup problem
From: "Antti" <Antti.Lukats@xilant.com>
Date: 18 Sep 2006 01:39:58 -0700
Links: << >>  << T >>  << A >>
sjulhes schrieb:

> We have identified the problem.
>
> In fact it is due to the xx.bmm file use by data2mem.
> EDK generates this file initialized with the software.
>
> When ISE uses this file, we don't know why, but due to timing constraints
> ISE changes the block ram for the timing constraint implementation so ISE

Stephane,

you did not specify that you are using ISE flow - the BMM file
integration into ISE is the least working feature, it is working better
than it used too, but in all cases where the XPS GUI is not used
and XPS project is not the main toplelevel the BMM file should
be checked that that properly initialiyed file is used for data2mem

Antti


Article: 108839
Subject: Little help for Spartan 2 and 3 Programmer
From: "Ali" <sadatakhavi.ali@gmail.com>
Date: 18 Sep 2006 01:48:56 -0700
Links: << >>  << T >>  << A >>
I like to work with Spartan but my computer have not the parallel port
it just has
serial and USB , Is there any programmer which works with these ports ?


Article: 108840
Subject: Re: net skew
From: "Symon" <symon_brewer@hotmail.com>
Date: 18 Sep 2006 12:20:08 +0200
Links: << >>  << T >>  << A >>
"maxascent" <maxascent@yahoo.co.uk> wrote in message 
news:vPKdncq4qcHzxpfYRVn_vA@giganews.com...
>
> Hi
>
> I have a design that I am having trouble routing. When I look at the clock
> signals the net skew for one is about 0.8ns were the other are less than
> 0.1ns. Could this be my problem and if so does anyone have any
> surgestions.
>
> Thanks
>
Hi Jon,
Did you connect your clock signal to any non-clock circuitry. E.g. LUTs, 
IOBs?
Cheers, Syms. 



Article: 108841
Subject: lwip Out of semaphore resources
From: "u_stadler@yahoo.de" <u_stadler@yahoo.de>
Date: 18 Sep 2006 03:51:36 -0700
Links: << >>  << T >>  << A >>
hi

i'm still struggeling trying to get the lwip stack running on a
microblaze processor with
the xilkernel.
my code is still pretty simple and other the initializing the kernel
it don't do much. in a sperate thread i call the functions :

mem_init();
memp_init();
pbuf_init();

as debug output i get the message:

"sys_sem_new: Error --  Out of semaphore resources"  three times for
every function.

any hints what i have to do?

another problem is when i try to create a socket. i pretty much use the
code from the xilinx os_libs.pdf.  when i try to create a socket the
programm just gets stuck there. don't know if this is connected with
the above problem...

thanks
urban


Article: 108842
Subject: Re: SSFP16 GPL licensed 16 Fpga processor released
From: "Antti" <Antti.Lukats@xilant.com>
Date: 18 Sep 2006 04:16:39 -0700
Links: << >>  << T >>  << A >>
ziggy schrieb:

> In article <1158485668.999811.326430@e3g2000cwe.googlegroups.com>,
>  "Antti" <Antti.Lukats@xilant.com> wrote:
>
> Antti
>
> Any ETA on translations for us over here in the us that never learned
> another language?

ETA of google translation: 5 minutes from now, so have have fun:

http://www.mikrocontroller.net/attachment.php/419502/ssfp16.pdf

funny to read, like WebPack is now Web luggage !!

Antti


Article: 108843
Subject: Re: A strange problem of Chipscope
From: quickwayne@gmail.com
Date: 18 Sep 2006 04:27:41 -0700
Links: << >>  << T >>  << A >>

Weng Tianxiang wrote:
> quickwayne@gmail.com wrote:
> > Hello,
> >
> > I am trying to design a multiprocessor system for my master project.
> > Chipscope is necessary to debug the system. But I got a strange problem
> > when I synthesize my design in EDK. It says,
> >
> > ERROR:MDT - ERROR FROM TCL:- chipscope_opb_iba_0 (chipscope_opb_iba) -
> > Release
> >
> > At the end of the report, it says,
> >
> >        while executing
> >    "exec xst -ifn $xst_scr_filename"
> >        (procedure "synthesize_cs_edk_port_mapper_core" line 55)
> >        invoked from within
> >    "synthesize_cs_edk_port_mapper_core $param_table"
> >        (procedure "::hw_chipscope_opb_iba_v1_01_a::opb_iba_generate"
> > line 95)
> >        invoked from within
> >    "::hw_chipscope_opb_iba_v1_01_a::opb_iba_generate 38052152"
> > ERROR:MDT - platgen failed with errors!
> >
> > The version of tools is EDK 8.1.02i, ISE 8.1.03i, chipscope 8.2.02i.
> >
> > Can you help me to figure out the problem? Thanks a lot.
> >
> > /Wayne
>
> Hi,
> The problem may be the different versions:
> EDK 8.1.02i, ISE 8.1.03i, chipscope 8.2.02i.
>
> They must be the same version: 8.1 or 8.2 and cannot be mixed. It is my
> guess!
> 
> Weng

Oh, that's also possible.


Article: 108844
Subject: Writing VHDL, Software dummy!
From: chadland@online.no
Date: 18 Sep 2006 04:31:33 -0700
Links: << >>  << T >>  << A >>
I have a couple of questions regarding VHDL and FPGAs as I am starting
a project on them shortly0.  Before I start I would  like to apologize
for my lack of knowledge on them.  I am a software developer not a
hardware so you might have to take this into consideration when
explaining.

I know VHDL is a hardware description language, but what is the biggest
challenge when writing code in VHDL compared to for example C.

Is it writing your code as close to elemtary logic as possible(that
will result in efficiency)??
Or is it perhaps timing challenges?

As you can see I am pretty fresh and I will dig down in VHDL literature
pretty soon but I would appreaciate a little input from people who are
experienced in it before I start. 

Cheers,
Chris


Article: 108845
Subject: Re: Writing VHDL, Software dummy!
From: "Antti" <Antti.Lukats@xilant.com>
Date: 18 Sep 2006 04:36:31 -0700
Links: << >>  << T >>  << A >>
chadl...@online.no schrieb:

> I have a couple of questions regarding VHDL and FPGAs as I am starting
> a project on them shortly0.  Before I start I would  like to apologize
> for my lack of knowledge on them.  I am a software developer not a
> hardware so you might have to take this into consideration when
> explaining.
>
> I know VHDL is a hardware description language, but what is the biggest
> challenge when writing code in VHDL compared to for example C.

you do not write code in VHDL
,
in VHDL you __describe__ the hardware.

thats the difference, you are not programming as VHDL is not a
programming language, you are describing the hardware you want to be
implemented.

this is the first thing you have to understand.

Antti


Article: 108846
Subject: Re: Writing VHDL, Software dummy!
From: Mike Harrison <mike@whitewing.co.uk>
Date: Mon, 18 Sep 2006 12:45:42 GMT
Links: << >>  << T >>  << A >>
On 18 Sep 2006 04:36:31 -0700, "Antti" <Antti.Lukats@xilant.com> wrote:

>chadl...@online.no schrieb:
>
>> I have a couple of questions regarding VHDL and FPGAs as I am starting
>> a project on them shortly0.  Before I start I would  like to apologize
>> for my lack of knowledge on them.  I am a software developer not a
>> hardware so you might have to take this into consideration when
>> explaining.
>>
>> I know VHDL is a hardware description language, but what is the biggest
>> challenge when writing code in VHDL compared to for example C.
>
>you do not write code in VHDL
>,
>in VHDL you __describe__ the hardware.
>
>thats the difference, you are not programming as VHDL is not a
>programming language, you are describing the hardware you want to be
>implemented.

..so you have to have at least a reasonable idea of the hardware design and functionality you are
trying to describe. 

Having said that, once you get your head round the basic concepts, you can write code that starts to
look and behave rather like software..... this can be a good or bad thing...


Article: 108847
Subject: Re: A strange problem of Chipscope
From: quickwayne@gmail.com
Date: 18 Sep 2006 06:18:14 -0700
Links: << >>  << T >>  << A >>
I installed chipscope 8.1i instead of 8.2i. but It's the same.

/Wayne

Weng Tianxiang wrote:
> quickwayne@gmail.com wrote:
> > Hello,
> >
> > I am trying to design a multiprocessor system for my master project.
> > Chipscope is necessary to debug the system. But I got a strange problem
> > when I synthesize my design in EDK. It says,
> >
> > ERROR:MDT - ERROR FROM TCL:- chipscope_opb_iba_0 (chipscope_opb_iba) -
> > Release
> >
> > At the end of the report, it says,
> >
> >        while executing
> >    "exec xst -ifn $xst_scr_filename"
> >        (procedure "synthesize_cs_edk_port_mapper_core" line 55)
> >        invoked from within
> >    "synthesize_cs_edk_port_mapper_core $param_table"
> >        (procedure "::hw_chipscope_opb_iba_v1_01_a::opb_iba_generate"
> > line 95)
> >        invoked from within
> >    "::hw_chipscope_opb_iba_v1_01_a::opb_iba_generate 38052152"
> > ERROR:MDT - platgen failed with errors!
> >
> > The version of tools is EDK 8.1.02i, ISE 8.1.03i, chipscope 8.2.02i.
> >
> > Can you help me to figure out the problem? Thanks a lot.
> >
> > /Wayne
>
> Hi,
> The problem may be the different versions:
> EDK 8.1.02i, ISE 8.1.03i, chipscope 8.2.02i.
>
> They must be the same version: 8.1 or 8.2 and cannot be mixed. It is my
> guess!
> 
> Weng


Article: 108848
Subject: Re: SoC Development Board
From: "John Adair" <removethisthenleavejea@replacewithcompanyname.co.uk>
Date: Mon, 18 Sep 2006 14:19:47 +0100
Links: << >>  << T >>  << A >>
John

We use Protel/Altium Designer for schematics and PCB. We don't use the 
autorouter so I can't comment on it. Everything is hand routed which gives 
very good results.

John Adair
Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 Development 
Board.
http://www.enterpoint.co.uk


"John" <bogus@bogus.ema> wrote in message 
news:MA8Og.5161$xg7.2918@tornado.socal.rr.com...
> Hi,
>
> In article <1158142703.3706.0@demeter.uk.clara.net>,
> removethisthenleavejea@replacewithcompanyname.co.uk says...
> Commercial bit - If you don't find what you need we
>> specialise in doing derivatives quickly too. The best example, in the 
>> public
>> domain of what we do in fast turn, is our MINI-CAN board that had a 
>> design
>> cycle, manufacture, 5 days of bench test and boards delivered to the
>> customer in 18 calendar days.
>
> That's pretty impressive!  Can you comment on what schematic
> capture/board layout progarms you're using?
>
> John. 



Article: 108849
Subject: Re: Little help for Spartan 2 and 3 Programmer
From: John_H <newsgroup@johnhandwork.com>
Date: Mon, 18 Sep 2006 13:29:25 GMT
Links: << >>  << T >>  << A >>
Ali wrote:
> I like to work with Spartan but my computer have not the parallel port
> it just has
> serial and USB , Is there any programmer which works with these ports ?


I've been using the Xilinx Platform Cable USB for some time.  They now 
have a second generation out there with lower power *and* is lead free. 
  I only wish I could have multiple USBs connected at once since my 
Xilinx Spartan3E starter kit board has a "built-in" platform USB cable 
that just needs a standard USB cable to connect to my system.  So nice.


"Simon" <news@gornall.net> wrote in message
news:2006091508283364440-news@gornallnet...
 > > So, having bought the V4FX-12 kit from NuHorizons, it arrived with a
 > > parallel-port JTAG cable. Normally I'd be just *fine* with this, 
but today
 > > my new quad-xeon Mac-pro arrives, and I bought that specifically to 
get
 > > some oomph in P&R (running linux using "parallels", of course).
 > >
 > > The mac doesn't have a parallel port. Ahhh. Is there a USB programming
 > > cable suitable for the FX-12 ? A fallback plan is to do most of the 
work
 > > on the Mac, but have a mini-itx machine next to it just for 
programming -
 > > the itx machine *does* have a // port, but it's woefully 
underpowered for
 > > any serious work on it...
 > >
 > > Ideas gratefully received  :-)
 > >
 > > Simon



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