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Geronimo Stempovski wrote: > > "John Fields" <jfields@austininstruments.com> schrieb im Newsbeitrag > news:urq0t2533bdm5e2t2ui82b7fo8ppvsbqs8@4ax.com... >> >> http://en.wikipedia.org/wiki/Microstrip >> > > Microstrip has absolutely nothing to do with the coaxial structure I > had in mind. http://en.wikipedia.org/wiki/Stripline You won't get any more TEM-like on a PCB. regards Henning F'up2 d.s.e. (Da darfst Du dann auch wieder deutsch sprechen.)Article: 115476
hi any release date for new version of MPMC2 and/or udpate for Virtex-5 support? I would like to test drive it on ML505 but there seems to be no update available since october:( AnttiArticle: 115477
I am converting a bsdl file to a private object format. The new thing this time are some entries which are fairly obvious, yet I would like some more certainty about them, if I can get it. Here is an excerpt: -- num cell port func safe [ccell dis rslt] "120 (BC_1, *, control, 1)," & "121 (BC_1, ext_ad_30, output3, 1, 120, 1, Z)," & "122 (BC_1, ext_ad_30, input, X)," & The line containing the new part is the one with "output3". Obviously its tristate control cell is 120; I wonder what "safe" means, just preferred initial state to preload the bsr with? Then "dis" and "rslt", do they mean that if I set the control cell (bsr bit 120) to 1 the output state will be Z? Looks obviously the case but given the stakes (smoke on error etc.) I would be grateful for any additional clarity. Thanks, Dimiter ------------------------------------------------------ Dimiter Popoff Transgalactic Instruments http://www.tgi-sci.com ------------------------------------------------------Article: 115478
On Feb 12, 6:10 am, "Geronimo Stempovski" <geronimo.stempov...@arcor.de> wrote: > I think transmitting high-speed signals is very easy when you have a > 360-degree ground reference, round conductors, > and no other nearby signals like in coaxial cables. My aim is to design PCB > tracks as much like a coaxial cable as > possible. Anyone tried this before? Is it possible with regular FR4, anyway? > Thanks for your help. > > Gero You can build a wave guide out of a multi-layer board with lots of micro vias. The performance gain was non-existent vs traditional micro/ strip/line, and cost a lot of money. These days you can satisfy yourself of this reality with a 3D field solver. Back when we tried this, workstations were as slow as building it "for real", and more expensive. Just break out to a connector, use a coax assembly, and connect back in. Easy peasy.Article: 115479
a7yvm109gf5d1@netzero.com wrote: > On Feb 12, 6:10 am, "Geronimo Stempovski" > <geronimo.stempov...@arcor.de> wrote: > >>I think transmitting high-speed signals is very easy when you have a >>360-degree ground reference, round conductors, >>and no other nearby signals like in coaxial cables. My aim is to design PCB >>tracks as much like a coaxial cable as >>possible. Anyone tried this before? Is it possible with regular FR4, anyway? >>Thanks for your help. >> >>Gero > > > You can build a wave guide out of a multi-layer board with lots of > micro vias. The performance gain was non-existent vs traditional micro/ > strip/line, and cost a lot of money. These days you can satisfy > yourself of this reality with a 3D field solver. Back when we tried > this, workstations were as slow as building it "for real", and more > expensive. > Just break out to a connector, use a coax assembly, and connect back > in. Easy peasy. > There is such a thing as microcoax, so he can chisel out a little groove in a thick pc and stuff that in there.Article: 115480
Thank you. I will have try.Article: 115481
> > "EEngineer" <mari...@gmail.com> writes: > > > I am interested in image processing of 128x128 image using wavelet > > > transform compression, 12 bits per pixel, monochrome. > Frame rate expected is 30fps. 128x128x30 fps should be trivial to implement "by-hand" ... That's 0.5 Msamples/s The resources will depend on how much effort you're willing to put ... But even with a "dumb" architecture that should fit in almost the smallest FPGA. There are several paper on how to implement them and even the simplest one (i.e., your pipeline is basically the lifting steps of the wavelet) should fit your purposes. In a Virtex4 SX35 we do a 5 level 9/7 daubechie 4096x2048 50fps 3 components, that's 1250 Msamples/s That requires slightly more attention ;) SylvainArticle: 115482
On Feb 12, 4:31 am, backhus <n...@nirgends.xyz> wrote: > Hi CMOS, > here's the solution you want: > > Assume the two input matrices to be stored in two separate RAMs (e.G. > Blockrams). Dual Ported, if necessary. > > Connect a subtractor circuit to the DataOut of these RAMs. > The Output of that circuit is identical to the output of your Result-RAM > > Now the result is virtually existent. If anyone has a doubt, just make a > readout of the Result-RAM. The result will be there. :-) > > Have a nice synthesis > Eilert Are you saying that the above mechanism will compute a difference of two arrays in one clock cycle? If so then, I am not following... maybe you can explain a bit more.Article: 115483
On Mon, 12 Feb 2007 14:17:50 GMT, Fred Bloggs <nospam@nospam.com> Gave us: > > >a7yvm109gf5d1@netzero.com wrote: >> On Feb 12, 6:10 am, "Geronimo Stempovski" >> <geronimo.stempov...@arcor.de> wrote: >> >>>I think transmitting high-speed signals is very easy when you have a >>>360-degree ground reference, round conductors, >>>and no other nearby signals like in coaxial cables. My aim is to design PCB >>>tracks as much like a coaxial cable as >>>possible. Anyone tried this before? Is it possible with regular FR4, anyway? >>>Thanks for your help. >>> >>>Gero >> >> >> You can build a wave guide out of a multi-layer board with lots of >> micro vias. The performance gain was non-existent vs traditional micro/ >> strip/line, and cost a lot of money. These days you can satisfy >> yourself of this reality with a 3D field solver. Back when we tried >> this, workstations were as slow as building it "for real", and more >> expensive. >> Just break out to a connector, use a coax assembly, and connect back >> in. Easy peasy. >> > >There is such a thing as microcoax, so he can chisel out a little groove >in a thick pc and stuff that in there. Semi-rigid is the term, and if it is in coax, it doesn't need to be IN the PCB from point to point. I wish you guys would stop cross posting all over the place. Many ISPs have group inclusion limits. It is also not considered proper Usenet practice.Article: 115484
Why do you need the result in one clock cycle? What are you doing with the result? Is your opeation all perallel? Peter Alfke On Feb 12, 7:20 am, "fpgabuilder" <fpgabuilder-gro...@yahoo.com> wrote: > On Feb 12, 4:31 am, backhus <n...@nirgends.xyz> wrote: > > > Hi CMOS, > > here's the solution you want: > > > Assume the two input matrices to be stored in two separate RAMs (e.G. > > Blockrams). Dual Ported, if necessary. > > > Connect a subtractor circuit to the DataOut of these RAMs. > > The Output of that circuit is identical to the output of your Result-RAM > > > Now the result is virtually existent. If anyone has a doubt, just make a > > readout of the Result-RAM. The result will be there. :-) > > > Have a nice synthesis > > Eilert > > Are you saying that the above mechanism will compute a difference of > two arrays in one clock cycle? If so then, I am not following... > maybe you can explain a bit more.Article: 115485
On Mon, 12 Feb 2007 12:10:43 +0100, "Geronimo Stempovski" <geronimo.stempovski@arcor.de> wrote: >I think transmitting high-speed signals is very easy when you have a >360-degree ground reference, round conductors, >and no other nearby signals like in coaxial cables. My aim is to design PCB >tracks as much like a coaxial cable as >possible. Anyone tried this before? Is it possible with regular FR4, anyway? >Thanks for your help. > >Gero > Sure. Microstrip, stripline, coplanar waveguide, or even the very strange slotline. JohnArticle: 115486
"Himlam8484" <creativeperson8584@gmail.com> wrote: >Hi people, > > >i am a new person in the FPGA field. I have just made something with >IC from Xilinx( just make a FPGA'sboard at home). I know it worked >well when i check it with some program.I started to learn to control >it.It is said that There is a processor inside FPGA called Picoblaze. >I try to program for it, but i have no following thing. > >I can program with the C software, then use a C compiler to compile it >then load into FPGA. I do not know if this process is Ok or not. i >also want to know when programming in C, Should i use the standard C >language or Use the Picoblaze languge but written in C. Programming Picoblaze in C might not be the best route for now (there is no good C compiler available). However, programming the picoblaze using its assembly language is quite straightforward. -- Reply to nico@nctdevpuntnl (punt=.) Bedrijven en winkels vindt U op www.adresboekje.nlArticle: 115487
Hi guys, I'm currently running a series of polls on Verilog, SystemVerilog, VHDL, and SystemC. I'd like to get you guys to vote for your favorite FPGA language use for design entry and synthesis. All poll results will remain in public domain, and will never be used for commercial purposes. So, here's the link to the poll: http://zeemz.com/forum/viewtopic.php?t=6 Thanks, for voting.Article: 115488
"Peter Alfke" <peter@xilinx.com> wrote in message news:1171298749.505302.219460@v33g2000cwv.googlegroups.com... > Why do you need the result in one clock cycle? What are you doing with > the result? Is your opeation all perallel? Sounds like he's trying to do MAD for motion compensation.Article: 115489
Hi everyone, I am working on my brother's school project to develop a STM-16 framer in FPGA but I have no idea about SONET so I am really appreciated if you can give me some instruction or idea to do it. There is also one question for the project "What are the main functions and how do you test it ?" Regards ThuyArticle: 115490
Thanks for your reply! Sean Durkin wrote: > Magne Munkejord wrote: >> Hello, >> >> I have a design with several LVDS transceivers. The design works well >> when all ports are connected but once some ports are unconnected I start >> receiving garbage from the floating inputs. > Well, what do you expect them to give you? If they are not connected, > and neither pulled to ground nor to VCC, you get something in between, > and that depends on the temperature, humidity, moon phase, your karma, > whatever... That's why it's called "floating", because the input floats > somewhere in between. Most of the time somewhere around the middle > exactly where the decision threshold between 0 and 1 is, so sometimes > you get 0, other times you get 1, which translates to garbage. > > As the warning states, if you do attach PULLUP or PULLDOWN primitives, > this might affect signal integrity. You might be OK with that, or it > might screw up your data, that's for you to decide. As you know, the > differential termination won't resolve the issue with the floating > inputs. So, pullups/-downs might be a solution, but only if it doesn't > affect signal integrity too much, which it seems to do in yout case > (since you still get garbage sometimes despite of the pullups). Sorry, inaccurate information from my part. When I leave all ports unconnected (no cables attached) 1 out of 8 channels still receives garbage. When I connect cables from one port to another data-transmission seems to be in order (2 of to 2 words received, 100% signal integrity :) I need more statistics on this). > >> If anyone have any suggestions on how to handle unconnected ports please >> let me know. > Yes, ignore everything you get from floating inputs. Easier said then done. The final design will have 120 serial channels. Received data words from each channel will be stored in a shared memory so I need to filter out the garbage words before I store them. > > HTH, > Sean > I am well aware of the problem that a floating input acts like an antenna. (At least I am now :) Since pullups and pulldowns are not an ideal solution, I was hoping there might be a way to detect an unconnected port/input and disable this channel. I see that in my original post, I left out some vital information; The lvds lines are used for serial data transmission over cat5 TP cables. Non-Return-to-Zero encoding with 4 cycles per bit, 32 bit words, 2 start bits, one parity bit and one stop bit. When the lines are idle the transmitters should hold the lines high (when looking at the single-ended signals from my IBUFDS/OBUFDS). The situation now is that, if by chance, a floating input stays low for 4 cycles and high for the 4 next, I start sampling for data bits. Of course I can discard words with stop bit error and/or parity errors but this method is not bullet-proof. Maybe I should try to make a more demanding/critical start condition? I will try to experiment a bit or two. As you say, these are design considerations I will have to make myself. I was thinking that this might be a common problem with a good solution but I can't find any discussions/articles about it on the Xilinx website. Thats why I made this thread. If anyone have some experience to share with me I'd be grateful.Article: 115491
On Feb 12, 3:39 am, me_2...@walla.co.il wrote: > On Feb 12, 1:49 am, "motty" <mottobla...@yahoo.com> wrote: > > > You should be able to pass the correct value for that parameter where > > you instantiate the ILA. However, you didn't say whether you are > > using the core inserter or genrating the ICON and ILA and > > instantiating them is the design. My suggestion will work for the > > later. > > Hi motty, > > I'm using the core inserter - its just more convenient that way. > Is there a way to pass this parameter when using the core inserter ? > Thanks, Mordehay. I've never seen that option, but I've never looked since I haven't used the inserter on an EDK project (ISE with MDM module).Article: 115492
On Mon, 12 Feb 2007 14:39:30 +0100, "Geronimo Stempovski" <geronimo.stempovski@arcor.de> wrote: > >"John Fields" <jfields@austininstruments.com> schrieb im Newsbeitrag >news:urq0t2533bdm5e2t2ui82b7fo8ppvsbqs8@4ax.com... >> >> http://en.wikipedia.org/wiki/Microstrip >> > >Microstrip has absolutely nothing to do with the coaxial structure I had in >mind. --- Well, Mister Nasty-Ass, what exactly did you have in mind, then? -- JFArticle: 115493
It's been a few years since I was working with SONET/SDH (OC-48 is SONET parlance and STM-16 is SDH last I knew). You need: 1) Frame detection (looking for a specific unscrambled bit sequence at the same location frame after frame) 2) (De)scrambler 3) Payload insert/extract along with the specified speed-adjustment mechanism to keep the payload frequency independent of the STM-16 rate. I'm assuming you already have the physical layer including clock extraction. What are you framing? Different payloads have different requirements. The appropriate specs will guide you to what you need for your various payloads including the rate adjustment mechanism is applicable. Packet based protocols may not need the speed adjustments I had to contend with for delivering lower-speed tributaries on the STM-16. "Thuy Pham" <thuyp@xilinx.com> wrote in message news:45D0A475.9522C423@xilinx.com... > Hi everyone, > > I am working on my brother's school project to develop a STM-16 framer > in FPGA but I have no idea about SONET so I am really appreciated if you > can give me some instruction or idea to do it. There is also one > question for the project "What are the main functions and how do you > test it ?" > > Regards > Thuy >Article: 115494
On 2007-02-12, Geronimo Stempovski <geronimo.stempovski@arcor.de> wrote:
>
> "John Fields" <jfields@austininstruments.com> schrieb im Newsbeitrag
> news:urq0t2533bdm5e2t2ui82b7fo8ppvsbqs8@4ax.com...
>>
>> http://en.wikipedia.org/wiki/Microstrip
>
> Microstrip has absolutely nothing to do with the coaxial
> structure I had in mind.
If you're such an expert, why are you asking here?
In my experience working with stuff in the low end of the
microwave region (~ 1GHz), microstrip is pretty much what
everybody uses as a PC board alternative to coax.
--
Grant Edwards grante Yow! NANCY!! Why is
at everything RED?!
visi.com
Article: 115495On Feb 12, 10:45 am, "Peter Alfke" <p...@xilinx.com> wrote: > Why do you need the result in one clock cycle? What are you doing with > the result? Is your opeation all perallel? > Peter Alfke > On Feb 12, 7:20 am, "fpgabuilder" <fpgabuilder-gro...@yahoo.com> > wrote: > > > > > On Feb 12, 4:31 am, backhus <n...@nirgends.xyz> wrote: > > > > Hi CMOS, > > > here's the solution you want: > > > > Assume the two input matrices to be stored in two separate RAMs (e.G. > > > Blockrams). Dual Ported, if necessary. > > > > Connect a subtractor circuit to the DataOut of these RAMs. > > > The Output of that circuit is identical to the output of your Result-RAM > > > > Now the result is virtually existent. If anyone has a doubt, just make a > > > readout of the Result-RAM. The result will be there. :-) > > > > Have a nice synthesis > > > Eilert > > > Are you saying that the above mechanism will compute a difference of > > two arrays in one clock cycle? If so then, I am not following... > > maybe you can explain a bit more.- Hide quoted text - > > - Show quoted text -Article: 115496
On Feb 12, 11:26 am, "Pete Fraser" <pfra...@covad.net> wrote: > "Peter Alfke" <p...@xilinx.com> wrote in message > > news:1171298749.505302.219460@v33g2000cwv.googlegroups.com... > > > Why do you need the result in one clock cycle? What are you doing with > > the result? Is your opeation all perallel? > > Sounds like he's trying to do MAD for motion compensation. I think he meant it '1 refresh cycle' instead of '1 clock cycle'Article: 115497
"Marlboro" <ccon67@netscape.net> wrote in message news:1171305434.728662.163300@h3g2000cwc.googlegroups.com... > On Feb 12, 11:26 am, "Pete Fraser" <pfra...@covad.net> wrote: >> "Peter Alfke" <p...@xilinx.com> wrote in message >> >> news:1171298749.505302.219460@v33g2000cwv.googlegroups.com... >> >> > Why do you need the result in one clock cycle? What are you doing with >> > the result? Is your opeation all perallel? >> >> Sounds like he's trying to do MAD for motion compensation. > > I think he meant it '1 refresh cycle' instead of '1 clock cycle' That kind of difference is too huge not to properly disclose. If that is the case, the orignal poster REALLY needs to clarify the expectations. Bottom line: the needs - as stated - are not realistic. The true needs must be explained to entertain solutions. It takes a huge number of cycles to accumulate pixels and a huge number to read the pixels back to make decisions. Asking for one "clock cycle" between these lengthy events is unrealistic. A specific number of clock cycles for a refresh cycle is more realistic but must be specified to bound the problem.Article: 115498
Hi Jim, I have been reviewing the XST VHDL IEEE support documentation and there is no mention of 1076-2002 support. XST does support 1076-1987, 1076-1993 and a partial implementation of 1076-2006. Might there be some revision from the 2002 to the 2006 spec in regards to shared variables? I don't know. What I read about shared variables for BRAMs with two write ports stated: "The XST VHDL analyzer accepts shared variables, but errors out in the HDL Synthesis step if a shared variable does not describe a valid RAM macro." Now everybodys interpretation is going to be different, but the wording 'accepts shared variables' seems to be a coding option rather than hard fast rule. On the other hand, the VHDL code example specifically uses shared variable syntax (as a general example). I would recommend that you (and any other engineer) looking to have a VHDL switch option to open a case with Technical Support and ask for an enhancement request to XST. -David "Jim Lewis" <jim@synthworks.com> wrote in message news:12ssn4bacp1g9bb@corp.supernews.com... > David, > Not have a setting is real bad. > > Last I looked Xilinx's recommended coding styles for > coding multiple edge FIFOs uses VHDL-93 shared variables. > In VHDL-2002 (the current IEEE revision) shared > variables require protected types. Hence Xlinx's coding > methodology is illegal in the current standard. > > Without a switch, what is going to happen to that > code that functions just fine, but is illegal? > > BTW there are 1076.6-2004 recommended coding styles > for this structure (a single process with 2 clock edges). > I haven't checked recently, does Xilinx support them. > > Cheers, > Jim > > >> Wojtek, >> >> The XST Users Guide gives specific details on which VHDL standard XST >> supports (and those that are conflicts). See the UG located here: >> http://toolbox.xilinx.com/docsan/xilinx9/books/docs/xst/xst.pdf >> >> I do not believe that there is a way to specify the exact standard that >> you may want to use. Verilog 2001 appears to be the only HDL standard >> that is selectable within the synthesis options. >> >> -David >> >> >> "wojt" <wojtek.bocer@gmail.com> wrote in message >> news:1171033608.993210.85410@a75g2000cwd.googlegroups.com... >>> Hi >>> >>> Does anyone here know, how to explicitly set which VHDL standard >>> should be used by Xilinx ISE (actually, by XST I think)? >>> >>> Cheers >>> Wojtek >>> >>Article: 115499
"Geronimo Stempovski" <geronimo.stempovski@arcor.de> wrote in message
news:45d04b34$0$27624$9b4e6d93@newsspool2.arcor-online.net...
>I think transmitting high-speed signals is very easy when you have a
>360-degree ground reference, round conductors,
> and no other nearby signals like in coaxial cables. My aim is to design PCB
> tracks as much like a coaxial cable as
> possible. Anyone tried this before?
I haven't tried it myself, but it's not entirely uncommon in microwave designs
to do something like this -- it's essentially a stripline design with a
"picket fence" worth of vias to serve as the sidewalls. I suspect the reason
it isn't particular popular is that the performance isn't that much better
than a stripline, the models for it aren't found in ADS/Microwave
Office/Ansoft Designer, and the manufacturing costs may be higher. ("Maybe"
because I've seen a lot of people who've started transitioning from microstrip
to a co-planar waveguide, which requires a bazillion drill hits as well. You
trade off the number of drill hits for isolation...)
---Joel
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