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jean-baptiste.nouvel@jdsu.com wrote: > Reading you, screws is the right option. Makes sense. > PCB will have to be reinforced from underneath. > > To control the force that is applied by the scew, Xilinx mentions some > spring based mechanism > that prevents the screw to deform the solder balls. Last time I looked at this, a few years ago, the best solution was something designed for the PC market. That market is big enough to support engineering design work on screws, springs, backplates, and so on. And the end product is often amazingly inexpensive, though that wasn't a consideration for my project.Article: 116626
hi,
I want to operate the XILINX Virtex-4 XC4VLX60(Speed -12) at a
frequenz of 130 MHz. So i write the following constraints to my
UCF(user constraint files).
NET "i_clk_adc" PERIOD = 6 ns HIGH 50 %; # clock periode,
6ns(about 160MHz)
OFFSET = IN 3 ns BEFORE "i_clk_adc" HIGH ; # Input signal must be
ready, 3 ns before rising edge
OFFSET = OUT 5 ns AFTER "i_clk_adc" HIGH ; # Output signal must be
at the PAD, 5 ns after the rising edge.
However, the constraints OFFSET = OUT 5 ns AFTER "i_clk_adc" HIGH ;
cannot be met. Actual timing is about 7.8ns.
The specification from XILINX says that, this device can be operated
at about 300MHz. Why i cannt achieve this timing level?
This is the code, i use this to test the device:
output: PROCESS(rst_n, i_clk)
BEGIN
IF(rst_n = '0') THEN
o_data <= '0';
cnt_exp <= '0';
ELSIF(RISING_EDGE(i_clk)) THEN
cnt_exp <= NOT cnt_exp;
IF(cnt_exp = '0') THEN
o_data <= '0';
ELSE
o_data <= '1';
END IF;
debug_data <= i_data;
END IF;
END PROCESS;
Thanks
Cheng
Article: 116627You're welcome. I personally like the torsion bar and I have seen it on a few PC motherboards. The bar regulates pressure and if you use a soft, sticky(-ish) thermal pad between the heatsink and FPGA, it will dampen vibrations while maintain contact and heatsink position. Of course, this method is suitable only for small thermal loads (<15W) due to low contact pressure and low-profile (10-20mm) lightweight (<100 grams) heatsinks unless you want to risk the heatsink ripping the eyelets off if the box is roughed up while either upside-down or standing up. The two points bar is only suitable for low vibration exposure applications. For somewhat larger thermal loads and significantly improved vibration tolerance, instead of using a single bar, some designs I have seen used an H-shaped hold-down clip. With four anchor points, the heatsink is fully locked down on all axis and won't wobble anywhere near as much or easily as it would with the two-point torsion bar, significantly reducing the vibration stress on each anchor point and the likelyhood that the heatsink could fall off if someone (Fed-Ex employee?) kicked the box around repeatedly. For applications where a device will be regularly exposed to vibrations, the four points H/X clips are noteworthy (the best I know) screw-less options. jean-baptiste.nouvel@jdsu.com wrote: > Thanks Daniel! > > Daniel S. a écrit : >> Ray Andraka wrote: >>> jean-baptiste.nouvel@jdsu.com wrote: >>> >>>> Hi, >>>> >>>> Anybody has experience with heatsinks on FPGAs? >>>> >>>> In the V5 documentation, Xilinx says the heatsink can be glued to the >>>> FPGA but that it >>>> is safer to screw it to the board to avoid mechanical contraints to >>>> the FPGA >>>> ball when under vibrations. >>>> >>>> But then the screws take some space on the board that we can't really >>>> afford... >>>> This would be at the expense of signal integrity (longer PCB >>>> tracks...). >>>> >> Another small heatsing fastening method I have seen is a simple torsion bar hooked into a >> pair of through-hole eyelets placed on opposite sides. PCB real-estate for a pair of these >> is something like 3-4 square milimeters. No screws, easy to service, negligible PCB area >> and the eyelet tabs can be however long as necessary to clear nearby SMT components. >Article: 116628
On Mar 13, 11:33 am, "VHDL_HELP" <abai...@gmail.com> wrote: > On 13 mar, 16:27, "John_H" <newsgr...@johnhandwork.com> wrote: > > > > > Add them together? > > > Your problem is not clear. Do you have an array in memory that you need to > > cycle through the elements one-by-one through an accumulator? Do you have > > an array of registers that needs a sum through a simple adder tree? Do you > > need to add two arrays held in memory to get a third array? > > > Please clarify the help you would like. > > > "VHDL_HELP" <abai...@gmail.com> wrote in message > > >news:1173792287.141073.35720@t69g2000cwt.googlegroups.com... > > > > hi every body , > > > > please please how to calculate the sum of an array ( for example an > > > array of std_logic_vector(3 downto 0) ) > > > > thank you > > library IEEE; > use IEEE.STD_LOGIC_1164.ALL; > use IEEE.STD_LOGIC_ARITH.ALL; > use IEEE.STD_LOGIC_UNSIGNED.ALL; > > entity somme is > Port ( clk : in STD_LOGIC; > din : in STD_LOGIC_VECTOR (3 downto 0); > taille : in STD_LOGIC_VECTOR (2 downto 0); > -- clk_out : in STD_LOGIC; > dout : out STD_LOGIC_VECTOR (3 downto 0) > ); > end somme; > > architecture Behavioral of somme is > type tab is array(3 downto 0) of STD_LOGIC_VECTOR(3 DOWNTO 0); > signal s : tab; > begin > process(clk) > begin > if clk'event and clk ='1' then > s(conv_integer(taille)) <= din; > end if; > end process; > dout <= s(0) + s(1) + s(2) + s(3); > end Behavioral; > > ------------------------------------------------------------------------ > it is my program : correct on syntax but it dont give me results > dout=4'hX > that it is what i get on simulation As John_H pointed out, taille only needs to be 2 bits. In other words: taille : in STD_LOGIC_VECTOR (1 downto 0); As for your simulation problem, your test bench needs to supply the values to be loaded into your signal "s". Otherwise, you will see X for dout. -Dave PollumArticle: 116629
On Mar 14, 6:54 am, Tim <t...@nooospam.roockyloogic.com> wrote: > jean-baptiste.nou...@jdsu.com wrote: > > Reading you, screws is the right option. Makes sense. > > PCB will have to be reinforced from underneath. > > > To control the force that is applied by the scew, Xilinx mentions some > > spring based mechanism > > that prevents the screw to deform the solder balls. > > Last time I looked at this, a few years ago, the best solution was > something designed for the PC market. That market is big enough to > support engineering design work on screws, springs, backplates, and so > on. And the end product is often amazingly inexpensive, though that > wasn't a consideration for my project. A note on glue. We've been using glue to attach heatsinks for years and have thousands of boards in the field without detachment problems, BUT... 1) We have found that the heatsinks that come self-sticking do not hold. 2) We use only DeltaBond 156-K, which requires a long cure time. 3) We don't use fan-equipped heatsinks which may create their own vibration or supply boards for use in high-vibration environments. That being said, if you're short on board space and your board is going into a typical P.C. or similar environment, glue can work for you. Here's a picture of one of our high-volume boards: http://www.alacron.com/FRAMEGRABBERS/FastImage1300new.jpg 4 of the 8 devices with heatsinks are Xilinx FPGA's. The others are DSP chips in a similar BGA package. Regards, GaborArticle: 116630
Uncle Noah, I completely disagree. It's much better without printed material. Far better, online resources are the future. Even so the S3E kit I have came with no less than nine booklets, about four cds and a little printed book explaining an introduction to VHDL and programmable logic (mentioned before, about 190 pages) - if you REALLY want a printed copy of things, then just print off the manual from the web: http://www.xilinx.com/bvdocs/userguides/ug230.pdf I really dont see why this would be an issue. Plus, electronically, the kit is a complete steal for $149 ($130 now - if you act fast) Just my 2p. Ben "Jim Granville" <no.spam@designtools.maps.co.nz> wrote in message news:45f6f4be$1@clear.net.nz... > Uncle Noah wrote: > >> Hi >> >> i'm outraged! Those guys from the X* company STOPPED DELIVERING >> printed manuals with their boards!!!! >> >> This is not right. For $149 plus international shipping rates, I >> demand a printed manual as well!!! >> >> What is your opinion? Does this happen for all (after mid 2006) Xilinx >> boards? > > I thought this had already happened, some years back, on most low-cost > eval level systems ? > Some vendors now off-load their manuals to a Web printing company, > who have a library of PDFs and they print/bind a book, just for you. > [for a fee, of course] > > -jg > >Article: 116631
On Mar 14, 7:38 am, "uvbaz" <u...@stud.uni-karlsruhe.de> wrote: > hi, > > I want to operate the XILINX Virtex-4 XC4VLX60(Speed -12) at a > frequenz of 130 MHz. So i write the following constraints to my > UCF(user constraint files). > > NET "i_clk_adc" PERIOD = 6 ns HIGH 50 %; # clock periode, > 6ns(about 160MHz) > OFFSET = IN 3 ns BEFORE "i_clk_adc" HIGH ; # Input signal must be > ready, 3 ns before rising edge > OFFSET = OUT 5 ns AFTER "i_clk_adc" HIGH ; # Output signal must be > at the PAD, 5 ns after the rising edge. > > However, the constraints OFFSET = OUT 5 ns AFTER "i_clk_adc" HIGH ; > cannot be met. Actual timing is about 7.8ns. > > The specification from XILINX says that, this device can be operated > at about 300MHz. Why i cannt achieve this timing level? > > This is the code, i use this to test the device: > > output: PROCESS(rst_n, i_clk) > BEGIN > IF(rst_n = '0') THEN > o_data <= '0'; > cnt_exp <= '0'; > ELSIF(RISING_EDGE(i_clk)) THEN > cnt_exp <= NOT cnt_exp; > IF(cnt_exp = '0') THEN > o_data <= '0'; > ELSE > o_data <= '1'; > END IF; > debug_data <= i_data; > END IF; > END PROCESS; > > Thanks > Cheng There are a number of factors that can cause long clock to output delays. 1) Output I/O standard. If you use LVTTL or LVCMOS standards, the default mode is slew-rate limited. This can add nanoseconds to your output delay. You can disable the slew-rate limits by attaching the FAST attribute to the port in your .ucf file. 2) Placement of output register. If the output register is not placed in the IOB you can have additional routing delays. Make sure you allow the mapper to push flip-flops into IOB's for outputs. In XST there is also the option for the synthesis stage to place flip-flops in the IOB. 3) Additional timing paths. Sometimes the timing report is not showing your normal clock-to-output delay but rather the reset to output delay. This occurs if your reset term is synchronous to the clock. Thus for example if rst_n was created on a rising edge of i_clk, the timing report will see a path from i_clk to rst_n through the reset of the output flip-flop and finally to the output pad. Usually this is not a path that needs to meet your OUT AFTER specification. You can use TIG on your reset nets to avoid this. You can see this in the timing report if you look at the path that fails and see the reset net somewhere in the chain. HTH, GaborArticle: 116632
Is there an easy way to get the Xilinx design manager to spit out a netlist for a synthesized VHDL file? AdamArticle: 116633
On Mar 14, 3:28 am, "michael" <yanw...@gmail.com> wrote: > can some one give me a hint on how to interface AD9229 a to d > converter with stratix II lvds interface? the AD9229 output sample > word of 12 bits, however the lvds serdes factor is 10 at the max. > > -thanks I ran into similar issues with a 1:7 (Channel-Link) receiver design. What I did was to use a 1:4 deserializer on each data channel and capture the 1x clock (in your case the FCO output) with a similar deserializer. Then using the value on the clock (FCO) deserializer I used a simple state machine to frame and compose the 7-bit (12-bit) input data word. HTH, GaborArticle: 116634
On Mar 14, 9:11 am, "AdamE" <aelb...@cs.uml.edu> wrote: > Is there an easy way to get the Xilinx design manager to spit out a > netlist for a synthesized VHDL file? > > Adam Do you want an EDIF netlist? Xilinx tools generally create a .ngc file which can be converted using ngc2edif from the command line.Article: 116635
Hi, I have set of registers implemented as internal RAM blocks (in Cyclone FPGA). Is there any way to clear contents of this registers on demand (just like clear signal in D flip-flops)? For answers thanks in advance.Article: 116636
On 2007-03-14, AdamE <aelbirt@cs.uml.edu> wrote: > Is there an easy way to get the Xilinx design manager to spit out a > netlist for a synthesized VHDL file? It depends on what kind of netlist you want. As mentioned earlier it is easy to get an EDIF netlist after the synthesis tool has run. But something which could also be useful is an XDL netlist which you can get after map or par has been executed. (I guess I'm guilty of advocating XDL a lot lately but you can do some really nifty tricks with it if you don't care about portability that much :)) /AndreasArticle: 116637
On 2007-03-14, Andreas Ehliar <ehliar@lysator.liu.se> wrote: > It depends on what kind of netlist you want. As mentioned earlier it > is easy to get an EDIF netlist after the synthesis tool has run. But > something which could also be useful is an XDL netlist which you can > get after map or par has been executed. Ahem.. perhaps I should mention how to get such a netlist as well... Use the xdl tool from the command line: xdl -ncd2xdl yourdesign.ncd /AndreasArticle: 116638
Hi, On Tue, 13 Mar 2007 14:34:14 +0100, Sylvain Munaut wrote: > Grant Likely wrote: >> I wasn't able to get it to work on an x86_64 system, but in a i386 >> chroot I had no problems. > It works fine for me with ISE9.1 x86_64. Nice to hear that it now works on x86_64. I had no chance to test it on such a machine with a connected cable, so I just got the driver to the point to not detect a cable when I got access to such a machine. > Again, Nice work ;) Thanks :-) Regards, MichaelArticle: 116639
"Yrjola" <yrjola@op.pl> wrote in message news:et8ugq$uaq$1@node4.news.atman.pl... > Hi, I have set of registers implemented as internal RAM blocks (in Cyclone > FPGA). Is there any way to clear contents of this registers on demand > (just like clear signal in D flip-flops)? > > For answers thanks in advance. Just like flops? Absolutely not. No memories come with resets. Not DDR SDRAMs, not SRAMs, not BlockRAMs, not distributed CLB SelectRAMs, not TriMatrix Memory. To clear the memory you either need to write every address or keep a separate bunch of registers as tags for each entry to label them as "not updated" in which case the value should be forced zero when read (at which time the flag is cleared). Some people call these "dirty bits" to keep track of which entries provides clean data and which don't. People who do fancy code can even have dirty bit registers to track a dirty bit memory array for those larger memory tasks. The basic idea is: Clear: Set all dirty bits. Read: value <= Dirty[addr] ? 0 : yourMem[addr]; Dirty[addr] <= 0; - John_HArticle: 116640
On 13 Mar 2007 11:43:56 -0700, "Peter Alfke" <peter@xilinx.com> wrote: "... grant [...] right to use my name, picture, likeness and/or photograph,[...] in all manners, including composite or distorted representations, for [...] any other purposes whatsoever." >Poof ! The offensive paragraph is now gone for American and Asian >registration also. >Sanity prevailed! >Peter Alfke Not that anyone here seriously expected to see their face photoshopped onto Paris Hilton, or worse, ... but still! Good riddance, - BrianArticle: 116641
> To clear the memory you either need to write every address or keep a > separate bunch of registers as tags for each entry to label them as "not > updated" in which case the value should be forced zero when read (at which > time the flag is cleared). Some people call these "dirty bits" to keep > track of which entries provides clean data and which don't. > > People who do fancy code can even have dirty bit registers to track a dirty > bit memory array for those larger memory tasks. > > The basic idea is: > > Clear: Set all dirty bits. > Read: value <= Dirty[addr] ? 0 : yourMem[addr]; Dirty[addr] <= 0; Well, I would only clear the dirty bits on writes ... Or if it's bram, you must force wren to 1 and write 0x00...00 at the same address you read to clear it. SylvainArticle: 116642
One asked: "The /*synopsys enum state_code*/ constraint is pretty handy to handle the FSM state encoding. Unfortunately XST doesn't seem to be managing it correctly (as opposed to other synthesisers). Not reporting errors but breaking the FSM!" XST used to (and maybe still does) not properly implement VHDL's ENUM_ENCODING attribute. "Anybody has a workaround? I have a design I want to convert to XST with 10s of files and 10s of FSMs..." Select Process --> Properties --> HDL Options --> FSM Encoding Algorithm --> various encodings.Article: 116643
> 1 Detect phase to see if there's a receiver connected > 2 Send TS1s > 3 Send 1024 TS1 after at least one TS1 has been received Step 2 and 3 are combined and the transmitter must send 1024 TS1's and 8 TS1 or TS2's must be received. > 4 Send TS2s and continue to send them until 8 TS2s have been received > 5 Send a further 16 TS2s Step 4 and 5 are combined as the count of 16 TS2's sent begins after receiving 1 of the 8 consecutive TS2's > 6 Send TS1s and wait for 2 TS1s with Link number rather than PAD symbol > 7 Return TS1s with Link number and wait to receive 2 TS1s with Lane number > 8 Return TS1s with Link and lane number the lane number sent in step 8 may be different than the lane number received in step 7. 9 Continue sending TS1s with link # and lane #, wait for receipt of 2 TS1's with same link # and a lane # different than the lane # beign transmitted, or receipt of 2 TS2's 10. Continue sending TS1s with link # and lane #, if 2 TS2's with matching link and lane numbers are received, move to next step. Otherwise if 2 TS1's are received with matching link numbers and some of the lanes have matching lane numbers or are receiving TS1's with non-PAD lane numbers, make a decision about the number of usable lanes and go back to step 9. 11. Send TS2's with the link and lane numbers from the received TS2's. Must receive 8 TS2's with matching link and lane # and must send 16 TS2's after receiving one TS2 12. Send Idle data and transition to L0 after receiving 8 consecutive idle data symbols and transmitting 16 idle data symbols after receiving 1 idle data symbol. There are some other details, such as polarity inversion, N_FTS, and other configuration information, but as far as a straight shot initialisation, that is the gist of it. Colin "Tim" <Tim@spamtrap.com> wrote in message news:1173807047.4904.0@proxy02.news.clara.net... > My understanding of the initialising sequence for a PCI-E card is as > follows: > > 1 Detect phase to see if there's a receiver connected > 2 Send TS1s > 3 Send 1024 TS1 after at least one TS1 has been received > 4 Send TS2s and continue to send them until 8 TS2s have been received > 5 Send a further 16 TS2s > 6 Send TS1s and wait for 2 TS1s with Link number rather than PAD symbol > 7 Return TS1s with Link number and wait to receive 2 TS1s with Lane number > 8 Return TS1s with Link and lane number > > What's wrong with the above? > > Regards > > Tim > > >Article: 116644
On Mar 14, 7:59 am, Andreas Ehliar <ehl...@lysator.liu.se> wrote: > On 2007-03-14, Andreas Ehliar <ehl...@lysator.liu.se> wrote: > > > It depends on what kind of netlist you want. As mentioned earlier it > > is easy to get an EDIF netlist after the synthesis tool has run. But > > something which could also be useful is an XDL netlist which you can > > get after map or par has been executed. > > Ahem.. perhaps I should mention how to get such a netlist as well... > > Use the xdl tool from the command line: > > xdl -ncd2xdl yourdesign.ncd > > /Andreas What are some of the tricks you do with the xdl netlist? Does it give you a way to take a core through map and PAR and then use it as a block box in a design that is going to go through map/PAR again? I have been wanting to harden some cores that I use in all my EDK designs, does this help any? I already have several cores that I pull in as black boxes and put area group constraints on. It would be nice to take those cores through PAR, and bring an already placed net list in as a block box. Regards, John McCaskill www.fastertechnology.comArticle: 116645
Brian, I was very surprised by this language, but, as you may have guessed it, someone was bringing suit against a distributor for using their photo in advertising when they were attending some 'affair'. My wife has been a professional photographer for 29 years, and on her website, she does have signed permission from all the subjects in the photos. There are also rules for when you do not need a release form: attending a public event, being in a public place, and so on. Privacy laws also differ from place to place, and what might be allowed in the US, may be illegal in Germany. If I am a global distribution company, I have a lot of work to do if I decide to have a photographer take pictures. If I am the photographer, I am aware of the law, and I inform my employer of what is legal and what forms need to be used (if any). A "one size fits all disclaimer" is not the answer. Often the reason for someone enforcing their "right to privacy" has to do with them being caught by a spouse doing something they would rather not have been caught doing. "I will be in London at the conference all week" and there they are, at the dinner event, with a glass of wine it their hands, and with their arm around someone not their spouse... But, it is not for us to judge. To laugh, yes. AustinArticle: 116646
On 14 mar, 13:44, "Dave Pollum" <vze24...@verizon.net> wrote: > On Mar 13, 11:33 am, "VHDL_HELP" <abai...@gmail.com> wrote: > > > > > On 13 mar, 16:27, "John_H" <newsgr...@johnhandwork.com> wrote: > > > > Add them together? > > > > Your problem is not clear. Do you have an array in memory that you need to > > > cycle through the elements one-by-one through an accumulator? Do you have > > > an array of registers that needs a sum through a simple adder tree? Do you > > > need to add two arrays held in memory to get a third array? > > > > Please clarify the help you would like. > > > > "VHDL_HELP" <abai...@gmail.com> wrote in message > > > >news:1173792287.141073.35720@t69g2000cwt.googlegroups.com... > > > > > hi every body , > > > > > please please how to calculate the sum of an array ( for example an > > > > array of std_logic_vector(3 downto 0) ) > > > > > thank you > > > library IEEE; > > use IEEE.STD_LOGIC_1164.ALL; > > use IEEE.STD_LOGIC_ARITH.ALL; > > use IEEE.STD_LOGIC_UNSIGNED.ALL; > > > entity somme is > > Port ( clk : in STD_LOGIC; > > din : in STD_LOGIC_VECTOR (3 downto 0); > > taille : in STD_LOGIC_VECTOR (2 downto 0); > > -- clk_out : in STD_LOGIC; > > dout : out STD_LOGIC_VECTOR (3 downto 0) > > ); > > end somme; > > > architecture Behavioral of somme is > > type tab is array(3 downto 0) of STD_LOGIC_VECTOR(3 DOWNTO 0); > > signal s : tab; > > begin > > process(clk) > > begin > > if clk'event and clk ='1' then > > s(conv_integer(taille)) <= din; > > end if; > > end process; > > dout <= s(0) + s(1) + s(2) + s(3); > > end Behavioral; > > > ------------------------------------------------------------------------ > > it is my program : correct on syntax but it dont give me results > > dout=4'hX > > that it is what i get on simulation > > As John_H pointed out, taille only needs to be 2 bits. In other > words: > taille : in STD_LOGIC_VECTOR (1 downto 0); > > As for your simulation problem, your test bench needs to supply the > values to be loaded into your signal "s". Otherwise, you will see X > for dout. > > -Dave Pollum i dont know it still the same problemArticle: 116647
In news:1173392175.030094.327500@h3g2000cwc.googlegroups.com timestamped 8 Mar 2007 14:16:15 -0800, "KJ" <Kevin.Jennings@Unisys.com> posted: "[..] > > #3 -- Latch equations written as a sum of products > > Q <= (C and D) or (not(C) and Q); > > > #4 -- Latch equation written in a sum of products form that includes a > > 'cover' term > > Q <= (C and D) or (not(C) and Q) or (D and Q); > [..] [..] suffice it to say that any time you have something of the form of equations #3 and #4 where you have the same signal on both sides of the '<=' in a concurrent statement you have some form of storage or memory being inferred that will cause you the exact same timing/glitch/hazard issues to deal with as you would if you have something that matches exactly #3 and #4. The important thing to take away is not whether it's a latch or an oscillator or anything else, just that red flags should go off in your head when you see the output being used on the right side of the equation. [..] [..]" True. "[..] Also keep in mind, that latches do not need to fit into a single equation, [..] A simple example of this would be #5 Q <= (C and X) or (not(C) and Y); -- Eqn. 5a Y <= Q and Z; -- Eqn. 5b Equation 5a, on the surface appears to be a 2->1 multiplexer where 'C' is simply used to select between two signals 'X' and 'Y'. Equation 5b, on the surface appears to be a simple anding of two signals 'Q' and 'Z'. But when you put them together the two form a [..] loop because 'Q' depends on 'Y' and 'Y' depends on 'Q'. [..]" This is a good point. "[..] [..] any time that you form a combinatorial loop you have to be concerned about how this will get implemented. A combinatorial loop happens when you have multiple equations, none of which inherently shows any feedback but taken together the whole set does. [..] [..]" Perhaps an unfortunate homonym of "combinatorial" has been used: do people use "combinatorial" in this way? A circuit which is described as "combinatorial" or its "combinational" in literature is one which does not have an output of its as an input of its, unlike a "sequential" (not in the VHDL sense) circuit. Regards, Colin Paul GlosterArticle: 116648
Someone made such a not particularly unique claim in this thread as: "[..] [..] Latches are only half as big as flipflops [..] [..]" A latch is a type of flip-flop.Article: 116649
Hi everybody, I am working with Sundance modules, specifically I have adquired Smt338vp30 which has a Virtex II Pro 30 (ff896-6). I have bought Diamond FPGA too, but I need to work with the PowerPC builts in the FPGA, so I have decided to use Xilinx EDK and ISE for this. I have asked Sundance for Constraint (UCF) files to program it but at this moment I have no experience with this kind of boards. Can anyone tell me if he/she has some experience with it ?? Regards Pablo
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