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hi, I'm here again. I know that, i've too many questions posted, please let me know, when you find that my messages bother you. :) Thanks There is a "ON NBC 12429" on the Board as clock oscilator, its output signal is PECL signal, can i use this signal direct as input clock for the Virtex-4 FPGA. Or i need an extra interface? Thanks in advance ChengArticle: 112151
Hi this may sound strange but I need flip flop or divide by 2 element that is made purely out of combinatorical logic and passes fpga implementation without being optimized away, and work in FPGA fabric. I tried some D-flop code but it gets really optimized away and doesnt work. I wonder if someone has a solution for this. It really must be pure logic, eg using DCM or BUFR is not ok, the solution must not use any fabric flip flops or fabric clocked primitives at all. AnttiArticle: 112152
> If you're using a hybrid technology like ACT logic where the inputs are > TTL compatible but the outputs are CMOS swing, simple series resistors > will allow your 3.3V Vcco powered LVTTL inputs to deal with the high > rails. It might be "safer" to include those resistors with classic 5V > powered TTL devices anyway. > > The series resistor is a consideration if you're doing I/Os over long > lines for high slew rate edges because the resistor value is much larger > than the characteristic impedance of the circuit board trace. Those are > the only signals you have to pay closer attention to. > > The appropriate resistor values and the data to back up the value > selection are found in various pieces of the FPGA documentation. Somehow I blanked out about the series resistor solution. The bus can have a 5v swing and that's why I was concerned. Thanks. GrantArticle: 112153
Hi, all I need to have a pulse signal. His frequency is 12.5 Mhz but my problem is rise time. I would like to get a maximum rise time of 2ns. Which is FPGA board (Xilinx) that i neeed? Thanks.Article: 112154
Antti wrote: > Hi > > this may sound strange but I need flip flop or divide by 2 element that > is made purely out of combinatorical logic and passes fpga > implementation without being optimized away, and work in FPGA fabric. I > tried some D-flop code but it gets really optimized away and doesnt > work. > > I wonder if someone has a solution for this. It really must be pure > logic, eg using DCM or BUFR is not ok, the solution must not use any > fabric flip flops or fabric clocked primitives at all. Hi Antti, One has to wonder .. why ? :) You will have to fight/override the tools, as this is not-natural as far as they are concerned. I tried this a while ago - in my case, a latch in PLD foldback nodes, and the logic itself is not complex, but the tools take one look at the buried hold loops, and optimize them away ! -jgArticle: 112155
funkrhythm wrote: > edit arch/ppc/platforms/xilinx_ocp/xilinx_syms.c > and change references to XpacketFifoV100a -> XpacketFifoV200a > (there's an include file and 4 EXPORT_SYMBOLs) Thanks for your reply, I tried what you said, I changed the lines: #include "xpacket_fifo_v1_00_b.h" EXPORT_SYMBOL(XPacketFifoV100b_Initialize); EXPORT_SYMBOL(XPacketFifoV100b_Read); EXPORT_SYMBOL(XPacketFifoV100b_SelfTest); EXPORT_SYMBOL(XPacketFifoV100b_Write); To read: #include "xpacket_fifo_v2_00_a.h" EXPORT_SYMBOL(XPacketFifoV200a_Initialize); EXPORT_SYMBOL(XPacketFifoV200a_Read); EXPORT_SYMBOL(XPacketFifoV200a_SelfTest); EXPORT_SYMBOL(XPacketFifoV200a_Write); I then did a make distclean, re-configured, did make dep then make bzImage. I got exactly the same errors: undefined references to the XPacketFifoV200a_* functions. I understand your fix, I just don't understand why it hasn't worked. Maybe I've done something wrong? If I look in arc/ppc/platforms/xilinx_ocp after the attempted build, there is a xpacket_fifo_v1_00_b.o but not a xpacket_fifo_v2_00_a.o, there is also a .xpacket_fifo_v1_00_b.o.flags but no equivalent v2 file. Any ideas? Thanks, -- PeterArticle: 112156
florent.peyrard@gmail.com wrote: > Hi all, > > i'm new to boundary scan and want to make it work in the xilinx starter > board, which contains a spartan-3 FPGA (xc3s200) and a platform flash > PROM (xcF02s). > > i'd like to make just a simple test, independantly of any design, just > to become familiar with this protocol: monitor the value of one of the > 8 switches of the board. here is what i did: i entered an instruction: > 000001 11111111 to put the PROM in bypass mode and the fpga in SAMPLE > mode. then i shift data out but the expected value doen't appear on TDO > after the expected number of clock edges, it seems that the capture > state doesn't work. i've read that during configuration, I/Os are not > connected, maybe this is my problem: i intentionnally changed the > jumpers to prevent configuration otherwise once configured, boundary > scan features aren't available any more. but maybe the system stays in > configuration mode, waiting for configuration and disabling I/Os until > configuration is done...can you help about this fact? > > and if i give up and try to instantiate the BSCAN_SPARTAN3 component in > a design in order to make the boundary scan feature available after > configuration, i just don't undertand at all how to instantiate it: > what should i link the pins of the symbol to? > > thanks a lot in advance, i'm very interested in this technology and it > would be a shame to give up.. > > florent > Hi Florent, If you start with JTAG topic, I can advice to just try to place both device in bypass mode and then go to DRSHIF, shift a pattern in TDI and get back it from TDO. In this case, you are sure to have a 2bits shift-register in the JTAG chain. NOTE: Do not forget that when you shift in the last bit, you have to update the TMS signal too ! This is maybe your error ! This will help you to understand the JTAG mechanism. When it works, go with a more complex scan. Regards, Laurent http://www.amontec.com _________________________________ Introducing new JTAGkey DLL, for easy USB to JTAG convertion !Article: 112157
<vsrpkumar@rediffmail.com> wrote in message
news:1163745004.396126.143160@m7g2000cwm.googlegroups.com...
>I have some combinational loops in my design.2 blocks are there with
> interface .1 st block output is going to second one input. and vice
> versa.problem is the pins of the blocks are dissappearing in the
> postfitting of design.How to constrain.I am using quartus s/w 6.0
> version with cyclone II device
>
This is talking about two different things (I think). A combinatorial loop
is one where there is a logical path from the input of some logic all the
way back to the same point with no intervening register. A trivial example
is
a<=b;
b<=a;
You fix that by putting a register in there somewhere....one possible
solution is
process(Clock)
begin
if rising_edge(Clock) then
a<=b;
end if;
end process;
b<=a;
The other thing you're talking about is that the pins of the block are
'disappearing'. What this means is that there is no output of the overall
design that in any way depends on the signals that are 'disappearing'. The
synthesis operation removes these simply because no output in way depends on
those signals so they are not needed. The following is a simple example.
entity Foo
a: in std_ulogic;
b: out std_ulogic;
end Foo;
architecture RTL of Foo is
signal c, d: std_ulogic;
begin
b <= a;
c <= a;
d <= a and b;
end RTL;
The signals c and d will 'disappear' and be optomized out since there is
only one output 'b' and it does not depend on either 'c' or 'd'. Even if
'c' and 'd' were pins on a different entity would not make a difference.
There is no 'fix' for this or constraint because the logic you've described
does not depend on them. What this likely means is that you need to go back
and look at your logic some more, and figure out what is not connected
properly so that it does not get removed.
KJ
Article: 112158Hi Laurent and Colin, at first thanks for taking some time helping me. Colin, the action of just shifting data through the chain does work. As you advice Laurent, i first started with just using the bypass mode for both devices, and it worked because when i shift data in, they are out a number of top clocks later which is equal to the chain lenght: 599 for the fpga plus 1 for the bypass register of the PROM plus 1 to make it appear on the DOUT port. (using SAMPLE instruction) i'm now trying what i described above, my aim is: to monitor the state of a slide switch, and it's close to work (using SAMPLE instruction); it seems it just does not CAPTURE the inputs coming from the board (in my case i'm more precisely interested in a slide switch). maybe the I/O are not available for capture while configuring? ( i intentionnaly prevent configuration by modifying the jumpers cause once configured, boundary scan is not available any more....) i need some help about this precise fact. Regards, Florent AMONTEC a =E9crit : > florent.peyrard@gmail.com wrote: > > Hi all, > > > > i'm new to boundary scan and want to make it work in the xilinx starter > > board, which contains a spartan-3 FPGA (xc3s200) and a platform flash > > PROM (xcF02s). > > > > i'd like to make just a simple test, independantly of any design, just > > to become familiar with this protocol: monitor the value of one of the > > 8 switches of the board. here is what i did: i entered an instruction: > > 000001 11111111 to put the PROM in bypass mode and the fpga in SAMPLE > > mode. then i shift data out but the expected value doen't appear on TDO > > after the expected number of clock edges, it seems that the capture > > state doesn't work. i've read that during configuration, I/Os are not > > connected, maybe this is my problem: i intentionnally changed the > > jumpers to prevent configuration otherwise once configured, boundary > > scan features aren't available any more. but maybe the system stays in > > configuration mode, waiting for configuration and disabling I/Os until > > configuration is done...can you help about this fact? > > > > and if i give up and try to instantiate the BSCAN_SPARTAN3 component in > > a design in order to make the boundary scan feature available after > > configuration, i just don't undertand at all how to instantiate it: > > what should i link the pins of the symbol to? > > > > thanks a lot in advance, i'm very interested in this technology and it > > would be a shame to give up.. > > > > florent > > > Hi Florent, > > If you start with JTAG topic, I can advice to just try to place both > device in bypass mode and then go to DRSHIF, shift a pattern in TDI and > get back it from TDO. In this case, you are sure to have a 2bits > shift-register in the JTAG chain. > > NOTE: > Do not forget that when you shift in the last bit, you have to update > the TMS signal too ! This is maybe your error ! > > This will help you to understand the JTAG mechanism. > When it works, go with a more complex scan. > > Regards, > Laurent > http://www.amontec.com > _________________________________ > Introducing new JTAGkey DLL, > for easy USB to JTAG convertion !Article: 112159
Jim Granville schrieb: > Antti wrote: > > > Hi > > > > this may sound strange but I need flip flop or divide by 2 element that > > is made purely out of combinatorical logic and passes fpga > > implementation without being optimized away, and work in FPGA fabric. I > > tried some D-flop code but it gets really optimized away and doesnt > > work. > > > > I wonder if someone has a solution for this. It really must be pure > > logic, eg using DCM or BUFR is not ok, the solution must not use any > > fabric flip flops or fabric clocked primitives at all. > > Hi Antti, > One has to wonder .. why ? :) > > You will have to fight/override the tools, as this is not-natural as > far as they are concerned. > I tried this a while ago - in my case, a latch in PLD foldback nodes, > and the logic itself is not complex, but the tools take one look at > the buried hold loops, and optimize them away ! > -jg why? I can answer this, I need the flip flop to toggle *BEFORE* FPGA configuration is completed, eg at the time when fabric clocked resources are not useable. and yes it seems like kinda PITA thing todo. Antti From Iwo.Mergler@soton.sc.philips.com Fri Nov 17 03:15:05 2006 Path: newsdbm05.news.prodigy.com!newsdst01.news.prodigy.net!prodigy.com!newscon04.news.prodigy.net!prodigy.net!newshub.sdsu.edu!newsfeed.news2me.com!newsfeed.icl.net!news-lond.gip.net!news.gsl.net!gip.net!lon04-news-philips!53ab2750!not-for-mail Message-Id: <p6i034-nsg.ln1@c2968.soton.sc.philips.com> From: Iwo Mergler <Iwo.Mergler@soton.sc.philips.com> Subject: Re: USB and AHB Newsgroups: comp.arch.fpga References: <1163633657.029718.142070@f16g2000cwb.googlegroups.com> <s6cu24-r7f.ln1@c2968.soton.sc.philips.com> <1163698923.449856.133200@b28g2000cwb.googlegroups.com> Lines: 23 Organization: Not organised User-Agent: KNode/0.9.2 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7Bit Date: Fri, 17 Nov 2006 11:15:05 +0000 NNTP-Posting-Host: 161.85.127.140 X-Complaints-To: newsmaster@rain.fr X-Trace: lon04-news-philips 1163764151 161.85.127.140 (Fri, 17 Nov 2006 11:49:11 GMT) NNTP-Posting-Date: Fri, 17 Nov 2006 11:49:11 GMT Xref: prodigy.net comp.arch.fpga:123165 terabits wrote: > > Thanks a lot for your replies and clarifications... > > so let me summarize what i have understood. > > suppose i have a usb device with dma controller integrated that can sit > on ahb bus as a master and slave can be some memory device > or if it doesn't have any dma inside it it is still a slave and only > host controller can be master on it (with ahb interface) > right ? Any busmaster in the system can access it. Especially with a USB2.0 high speed device, you really don't want to move data with the processor. If the USB device is a AHB slave, you probably want to use the system's DMA controller as the master device for data transfer, not the processor. Kind regards, IwoArticle: 112160
Antti <Antti.Lukats@xilant.com> wrote: > Jim Granville schrieb: > > Antti wrote: > > > > > Hi > > > > > > this may sound strange but I need flip flop or divide by 2 element that > > > is made purely out of combinatorical logic and passes fpga > > > implementation without being optimized away, and work in FPGA fabric. I > > > tried some D-flop code but it gets really optimized away and doesnt > > > work. > > > > > > I wonder if someone has a solution for this. It really must be pure > > > logic, eg using DCM or BUFR is not ok, the solution must not use any > > > fabric flip flops or fabric clocked primitives at all. > > > > Hi Antti, > > One has to wonder .. why ? :) > > > > You will have to fight/override the tools, as this is not-natural as > > far as they are concerned. > > I tried this a while ago - in my case, a latch in PLD foldback nodes, > > and the logic itself is not complex, but the tools take one look at > > the buried hold loops, and optimize them away ! > > -jg > why? I can answer this, I need the flip flop to toggle *BEFORE* FPGA > configuration is completed, eg at the time when fabric clocked > resources are not useable. > and yes it seems like kinda PITA thing todo. Can't you delay startup of the rest of the circuit while starting the divider immediately after configuartion? -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 112161
Uwe Bonnes schrieb: > Antti <Antti.Lukats@xilant.com> wrote: > > Jim Granville schrieb: > > > > Antti wrote: > > > > > > > Hi > > > > > > > > this may sound strange but I need flip flop or divide by 2 element that > > > > is made purely out of combinatorical logic and passes fpga > > > > implementation without being optimized away, and work in FPGA fabric. I > > > > tried some D-flop code but it gets really optimized away and doesnt > > > > work. > > > > > > > > I wonder if someone has a solution for this. It really must be pure > > > > logic, eg using DCM or BUFR is not ok, the solution must not use any > > > > fabric flip flops or fabric clocked primitives at all. > > > > > > Hi Antti, > > > One has to wonder .. why ? :) > > > > > > You will have to fight/override the tools, as this is not-natural as > > > far as they are concerned. > > > I tried this a while ago - in my case, a latch in PLD foldback nodes, > > > and the logic itself is not complex, but the tools take one look at > > > the buried hold loops, and optimize them away ! > > > -jg > > > why? I can answer this, I need the flip flop to toggle *BEFORE* FPGA > > configuration is completed, eg at the time when fabric clocked > > resources are not useable. > > > and yes it seems like kinda PITA thing todo. > > Can't you delay startup of the rest of the circuit while starting the divider > immediately after configuartion? > > -- > Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de > > Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt > --------- Tel. 06151 162516 -------- Fax. 06151 164321 ---------- I want to quick start the STARTUP primitive without the use of external clocks. so I need 10 pulses at the time when GSR GTS are asserted and GWE is not released. this is maybe just a few config clokc pulses *BEFORE* the FPGA actually starts to work. only wiring and combinatorical logic is activated. the divider is only need *until* done goes high, not any more after that. Antti From removethisthenleavejea@replacewithcompanyname.co.uk Fri Nov 17 04:06:44 2006 Path: newsdbm05.news.prodigy.com!newsdst01.news.prodigy.net!prodigy.com!newscon04.news.prodigy.net!prodigy.net!newshub.sdsu.edu!newsfeed.freenet.de!border2.nntp.ams.giganews.com!nntp.giganews.com!proxad.net!news.clara.net!wagner.news.clara.net!monkeydust.news.clara.net!demeter.uk.clara.net From: "John Adair" <removethisthenleavejea@replacewithcompanyname.co.uk> Newsgroups: comp.arch.fpga References: <1163728657.685622.99030@f16g2000cwb.googlegroups.com> Subject: Re: Spartan 3/3E to Standard TTL/Low power devices Date: Fri, 17 Nov 2006 12:06:44 -0000 Lines: 23 X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 6.00.2900.2869 X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2900.2962 X-RFC2646: Format=Flowed; Original X-Complaints-To: abuse@clara.net (please include full headers) X-Trace: 16d3270c13165276e0e0610003442d00e3213839c330362823029070455da5ce NNTP-Posting-Date: Fri, 17 Nov 2006 12:06:38 +0000 Message-Id: <1163765198.23895.0@demeter.uk.clara.net> Xref: prodigy.net comp.arch.fpga:123166 LCX sub-family is good for going from TTL to LVTTL. It is 5V tolerant. If you want bi-directional then is hard to beat the use of a bus switch which passively limits voltage to the sensative side. We QS3861 regularly for this purpose. John Adair Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 Development Board. http://www.enterpoint.co.uk "Grant Stockly" <grant@stockly.com> wrote in message news:1163728657.685622.99030@f16g2000cwb.googlegroups.com... > What would you guys recomend as a bus transciever for interfacing with > standard TTL and low power TTL logic? I'm thinking that the TI > 74AC11245 would work. The high/low thresholds seem to be good and it > will tollerate 5v input on the bus side... > > Thanks, > Grant >Article: 112162
Grant Stockly <grant@stockly.com> wrote: > What would you guys recomend as a bus transciever for interfacing with > standard TTL and low power TTL logic? I'm thinking that the TI > 74AC11245 would work. The high/low thresholds seem to be good and it > will tollerate 5v input on the bus side... There are zilions of options. With the requirement of "standard TTL" levels, the output voltage of a 3.3 Volt powered bank is fine for the TTL standard. Only protection of the Spartan is needed. This can be done: - current limit resistors - Bus switch like SN74CBTD338 - Level translating transceivers like SN74LVC8T245 - 3.3Volt powered SN74LVC245 First is cheapest, but eventually requires a 3.3 Volt supply that can sink current Second is a no-brainer, as no direction switching is needed. It's also fastest. Third is most universal, as this with work with lower voltages on the Spartan too. And for the last possibility, you probably already have the parts on hands. Choose yourself. -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 112163
"Antti" <Antti.Lukats@xilant.com> wrote in message news:1163754102.129370.31240@k70g2000cwa.googlegroups.com... > Hi > > this may sound strange but I need flip flop or divide by 2 element that > is made purely out of combinatorical logic and passes fpga > implementation without being optimized away, and work in FPGA fabric. I > tried some D-flop code but it gets really optimized away and doesnt > work. > > I wonder if someone has a solution for this. It really must be pure > logic, eg using DCM or BUFR is not ok, the solution must not use any > fabric flip flops or fabric clocked primitives at all. > > Antti > Hi Antti, A while back I did something similar by instantiating LUT primitives. e.g.:- component LUT4 generic ( INIT : bit_vector := X"0000"); port (O : out STD_ULOGIC; I0 : in STD_ULOGIC; I1 : in STD_ULOGIC; I2 : in STD_ULOGIC; I3 : in STD_ULOGIC); end component; The tools weren't clever enough to look at the INIT number and attempt 'optimisation'. Good luck, Syms.Article: 112164
olive_dominguez@yahoo.fr wrote: > Hi, all > > I need to have a pulse signal. His frequency is 12.5 Mhz but my problem > is rise time. I would like to get a maximum > rise time of 2ns. Which is FPGA board (Xilinx) that i neeed? > > Thanks. If you need a rise time of less than 2 ns into a load that isn't exceedingly capacitive, virtually any FPGA device will do. If you need a rise time of 2 ns or longer, you need to look at external methods of slowing the signal. This is a case where Signal Integrity simulations will open your eyes as to what the physical signal should look like. - John_HArticle: 112165
Antti wrote: > Hi > > this may sound strange but I need flip flop or divide by 2 element that > is made purely out of combinatorical logic and passes fpga > implementation without being optimized away, and work in FPGA fabric. I > tried some D-flop code but it gets really optimized away and doesnt > work. > > I wonder if someone has a solution for this. It really must be pure > logic, eg using DCM or BUFR is not ok, the solution must not use any > fabric flip flops or fabric clocked primitives at all. > > Antti Sounds like you need a master/slave pair of latches (a DFF made out of gates). The only trouble would be convincing the tool to not optimize out or complain too harshly about the combinatorial loops. Two SR Latches chained together. The S and R inputs are the normal and inverted signal from the other stage (inverted between one pair) and the clock acts as a 3rd input - normal on one SR Latch, inverted on the other - to each NAND gate to make the latch transparent or to allow the latch. I'm thinking back to the old TI data book that mapped out all the simple TTL logic. Since you don't need asynchronous set/reset logic, you should need just the 4 LUTs.Article: 112166
Antti wrote... > Hi > > this may sound strange but I need flip flop or divide by 2 element that > is made purely out of combinatorical logic and passes fpga > implementation without being optimized away, and work in FPGA fabric. I > tried some D-flop code but it gets really optimized away and doesnt > work. > > I wonder if someone has a solution for this. It really must be pure > logic, eg using DCM or BUFR is not ok, the solution must not use any > fabric flip flops or fabric clocked primitives at all. LUT instantiation. But you already know that. A good excuse to revisit those Digital Logic 101 textbooks... My memory is that Peter Alfke did this a while back, possibly in his search for the fastest frequency counter in the galaxy ;-) Check the archives.Article: 112167
Tim schrieb: > Antti wrote... > > Hi > > > > this may sound strange but I need flip flop or divide by 2 element that > > is made purely out of combinatorical logic and passes fpga > > implementation without being optimized away, and work in FPGA fabric. I > > tried some D-flop code but it gets really optimized away and doesnt > > work. > > > > I wonder if someone has a solution for this. It really must be pure > > logic, eg using DCM or BUFR is not ok, the solution must not use any > > fabric flip flops or fabric clocked primitives at all. > > LUT instantiation. But you already know that. A good excuse to revisit those > Digital Logic 101 textbooks... > > My memory is that Peter Alfke did this a while back, possibly in his search > for the fastest frequency counter in the galaxy ;-) Check the archives. yeah, I know the LUT path, will have todo it that way AnttiArticle: 112168
Hi As I know Coregen generate Aurora core as source code (as well RocketIO wiz), so you can correct some attributes depend on using stepping. BRArticle: 112169
John_H wrote: > Antti wrote: > > Hi > > > > this may sound strange but I need flip flop or divide by 2 element that > > is made purely out of combinatorical logic and passes fpga > > implementation without being optimized away, and work in FPGA fabric. I > > tried some D-flop code but it gets really optimized away and doesnt > > work. > > > > I wonder if someone has a solution for this. It really must be pure > > logic, eg using DCM or BUFR is not ok, the solution must not use any > > fabric flip flops or fabric clocked primitives at all. > > > > Antti > > Sounds like you need a master/slave pair of latches (a DFF made out of > gates). The only trouble would be convincing the tool to not optimize > out or complain too harshly about the combinatorial loops. > > Two SR Latches chained together. The S and R inputs are the normal and > inverted signal from the other stage (inverted between one pair) and the > clock acts as a 3rd input - normal on one SR Latch, inverted on the > other - to each NAND gate to make the latch transparent or to allow the > latch. > > I'm thinking back to the old TI data book that mapped out all the simple > TTL logic. Since you don't need asynchronous set/reset logic, you > should need just the 4 LUTs. Two LUTS/FF. Only one LUT required per latch, one for master latch, one for slave, and . wiring, err routing, delays should be verified. I'd list the init values, but haven't had my coffee yet this morning. Just JohnArticle: 112170
Search on the xilinx website and on your webpack/ISE installation help for BSDLANNO and you will quickly find out how xilinx fpga's behave when configured. Colin florent.peyrard@gmail.com wrote: > Hi Laurent and Colin, > > at first thanks for taking some time helping me. > Colin, the action of just shifting data through the chain does work. > As you advice Laurent, i first started with just using the bypass mode > for both devices, and it worked because when i shift data in, they are > out a number of top clocks later which is equal to the chain lenght: > 599 for the fpga plus 1 for the bypass register of the PROM plus 1 to > make it appear on the DOUT port. (using SAMPLE instruction) > i'm now trying what i described above, my aim is: to monitor the state > of a slide switch, and it's close to work (using SAMPLE instruction); > it seems it just does not CAPTURE the inputs coming from the board (in > my case i'm more precisely interested in a slide switch). maybe the I/O > are not available for capture while configuring? ( i intentionnaly > prevent configuration by modifying the jumpers cause once configured, > boundary scan is not available any more....) i need some help about > this precise fact. > > Regards, > Florent > AMONTEC a =E9crit : > > > florent.peyrard@gmail.com wrote: > > > Hi all, > > > > > > i'm new to boundary scan and want to make it work in the xilinx start= er > > > board, which contains a spartan-3 FPGA (xc3s200) and a platform flash > > > PROM (xcF02s). > > > > > > i'd like to make just a simple test, independantly of any design, just > > > to become familiar with this protocol: monitor the value of one of the > > > 8 switches of the board. here is what i did: i entered an instruction: > > > 000001 11111111 to put the PROM in bypass mode and the fpga in SAMPLE > > > mode. then i shift data out but the expected value doen't appear on T= DO > > > after the expected number of clock edges, it seems that the capture > > > state doesn't work. i've read that during configuration, I/Os are not > > > connected, maybe this is my problem: i intentionnally changed the > > > jumpers to prevent configuration otherwise once configured, boundary > > > scan features aren't available any more. but maybe the system stays in > > > configuration mode, waiting for configuration and disabling I/Os until > > > configuration is done...can you help about this fact? > > > > > > and if i give up and try to instantiate the BSCAN_SPARTAN3 component = in > > > a design in order to make the boundary scan feature available after > > > configuration, i just don't undertand at all how to instantiate it: > > > what should i link the pins of the symbol to? > > > > > > thanks a lot in advance, i'm very interested in this technology and it > > > would be a shame to give up.. > > > > > > florent > > > > > Hi Florent, > > > > If you start with JTAG topic, I can advice to just try to place both > > device in bypass mode and then go to DRSHIF, shift a pattern in TDI and > > get back it from TDO. In this case, you are sure to have a 2bits > > shift-register in the JTAG chain. > > > > NOTE: > > Do not forget that when you shift in the last bit, you have to update > > the TMS signal too ! This is maybe your error ! > > > > This will help you to understand the JTAG mechanism. > > When it works, go with a more complex scan. > > > > Regards, > > Laurent > > http://www.amontec.com > > _________________________________ > > Introducing new JTAGkey DLL, > > for easy USB to JTAG convertion !Article: 112171
"nfirtaps" <lloyd.rochester@gmail.com> wrote in message news:1163716501.256076.123930@e3g2000cwe.googlegroups.com... > > This will have a horrible outcome because the data is not valid on the > rising edge? Right? What is a nice way to get around this? Besides > using things like clock managers? > Hi Lloyd, You might want to read about hold time. If you look at the V4 timing datasheet, DS302, you'll find the CLB FFs have a negative hold time. HTH, Syms.Article: 112172
"uvbaz" <uvbaz@stud.uni-karlsruhe.de> wrote in message news:1163753960.151544.119270@m73g2000cwd.googlegroups.com... > hi, > > I'm here again. I know that, i've too many questions posted, please let > me know, when you find that my messages bother you. :) Thanks > > There is a "ON NBC 12429" on the Board as clock oscilator, its output > signal is PECL signal, can i use this signal direct as input clock for > the Virtex-4 FPGA. Or i need an extra interface? > > Thanks in advance > Cheng > LVPECL?Article: 112173
Hi, Altera is promoting its own soft-core processor, but it seems that they have "forgotten" the one of the most important things out of their tool-flow, namly it seems to impossible to merge the FPGA tool generated files after the flow with memory init files, like it doable with Xilinx and Lattice FPGA's. I just cant belive it, its one of the most useful things for the FPGA SoC designs, and its just not there? I really doesnt have time or fun to reverse engineer the .SOF format only to be able write the data2sof utility for Altera. Antti PS I am almost impressed about the Quality of Quartus 6.0, it took over 2 hours before it trapped into internal error and self terminated. For ISE 8.2 this time was 20 minutes, so Altera is leading as of software tool quality. Hm, nops, I dont recall Lattice tools to have self termination effects.Article: 112174
JustJohn schrieb: > John_H wrote: > > Antti wrote: > > > Hi > > > > > > this may sound strange but I need flip flop or divide by 2 element that > > > is made purely out of combinatorical logic and passes fpga > > > implementation without being optimized away, and work in FPGA fabric. I > > > tried some D-flop code but it gets really optimized away and doesnt > > > work. > > > > > > I wonder if someone has a solution for this. It really must be pure > > > logic, eg using DCM or BUFR is not ok, the solution must not use any > > > fabric flip flops or fabric clocked primitives at all. > > > > > > Antti > > > > Sounds like you need a master/slave pair of latches (a DFF made out of > > gates). The only trouble would be convincing the tool to not optimize > > out or complain too harshly about the combinatorial loops. > > > > Two SR Latches chained together. The S and R inputs are the normal and > > inverted signal from the other stage (inverted between one pair) and the > > clock acts as a 3rd input - normal on one SR Latch, inverted on the > > other - to each NAND gate to make the latch transparent or to allow the > > latch. > > > > I'm thinking back to the old TI data book that mapped out all the simple > > TTL logic. Since you don't need asynchronous set/reset logic, you > > should need just the 4 LUTs. > > Two LUTS/FF. Only one LUT required per latch, one for master latch, one > for slave, and . wiring, err routing, delays should be verified. > I'd list the init values, but haven't had my coffee yet this morning. > Just John hm, get your coffee and write it down :) and you get extra e-coffe from me. the non-LUT version of the master slave thing did not yield anyuseful result. sounds interesting to have a FF out of 2LUT (if it work also..) Antti
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