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> As long as there is a *single* flop to synchronize the signal, only one > flop is needed. The design must not have more than one register that > depends on the live signal. Once synchronized, the rare addition of 1-3 > ns will not be a problem for downstream logic. That's what I was thinking. Thanks. JonArticle: 121376
pbFJKD@ludd.invalid writes: > In article <uzm2elyy1.fsf@trw.com> you wrote: >>Matthieu <m.a.t.t.h.i.e.u.m.i.c.h.o.n@laposte.net> writes: > >>> However ISE will run faster with CPUs featuring 4 MB L2 cache, such as >>> th mid/high-end Intel Core2 Duo CPUs (if I recall correctly models >>> E6320, E6420, E6600 and higher). > >>To give you a single data point, my MAP/PAR time reduced by about >>20% when i went from a 2MB Core2Duo (E6400?) to 4MB (E6600) at the same clock >>speed (2.4GHz). > >>BTW, going to the 2MB Core2Duo from my previous 3GHz P4 halved the time! > > Unfortunly the Intel Core2Duo seems to have both security & integrity > problems: > http://www.buildyourown.org.uk/forums/topic.asp?topic_ID=25527 > marc.info/index.html?l=openbsd-misc&m=118296441702631 > > When loading data from L1 cache it will occasionally have stale data. > It looks like it could occasionally get it's cache wrong. Very occasionally - "not been seen in commercial systems". > Any tip on a AMD cpu that will perform? > Not that is guaranteed errata-free :-) Just get 1) a big cache 2) Low latency main memory... 3) ... and lots of it Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.net/electronics.htmlArticle: 121377
> > You are dealing with binary fractions, not integers, right? That is, > > numbers between 0 and 1 (or -1 to 1)? In your case, just take the > > leftmost 16 bits of the 20 bit result. > I am coming into this discussion late, but if you ha 20 bit result (prod[19:0]) from a 4 and 16 bit signed fractional mult, you would want to keep prod[18:3] to keep it in the range of -1 to 1. You end up with two sign bits when you multiply two signed fractions together so you can throw one of them away. Note, you should also have a rounding scheme for prod[2:0] to keep it as accurate as possible. TomArticle: 121378
For a Xilinx V4, there is an IBUFDS_DIFF buffer that you can use in the I/O pad. However, it appears that there is no differential termination resistor available for this setup. In XAPP861, it shows the buffer and the "optional DIFF_TERM" across the I and IB inputs. When I set the attribute to use the DIFF_TERM, Xilinx tools report that it is an invalid attribute. I assume that the tools are right and that for this particular buffer, there is not termination available. Could anyone give me a definitive answer? Documentation and/or other info on this primitive is limited at best. Also, there is a ULVDS standard supported in the I/O's but there isn't much info on that either (ie electrical specs). Thanks in advance.Article: 121379
I swear every time I post here, I find some relevant info on Xilinx' site. It appears that the warning that the DIFF_TERM is not applicable is false. The diff term is applied to the IBUFDS_DIFF_OUT. However, the answer record did say that the warning would be fixed in 8.1 tools. I saw this problem in 8.2 tools.Article: 121380
"motty" <mottoblatto@yahoo.com> wrote in message news:1183476070.282133.230570@n2g2000hse.googlegroups.com... > For a Xilinx V4, there is an IBUFDS_DIFF buffer that you can use in > the I/O pad. However, it appears that there is no differential > termination resistor available for this setup. In XAPP861, it shows > the buffer and the "optional DIFF_TERM" across the I and IB inputs. > When I set the attribute to use the DIFF_TERM, Xilinx tools report > that it is an invalid attribute. I assume that the tools are right > and that for this particular buffer, there is not termination > available. Could anyone give me a definitive answer? > > Documentation and/or other info on this primitive is limited at > best. > > Also, there is a ULVDS standard supported in the I/O's but there isn't > much info on that either (ie electrical specs). > > Thanks in advance. > How are you setting the attribute? From what I recall, you have to add (something like) "DIFF_TERM = TRUE" in the UCF. I think that's different from the way you do it in V2Pro. Also, the differential termination only works for banks where VCCO is 2.5V. What is the bank voltage (what are the other i/o standards defined for) in that bank? BobArticle: 121381
I have been reading through UG331 for information on the DCM,
especially in the case with external clock feedback. On a previous
project we used a Microblaze with an SDRAM controller, but did not
have the external feedback. On this project, I have the board
designers giving me a feedback clock path so I can deskew the SDRAM
signals with a DCM.
The basic setup is (forgive the ASCII art; you probably need a fixed
font to see it correctly):
+-----------------+ +------------------+ +-------+
clk -->| CLKIN CLK90 |-+--->| CLKIN CLK0 |--->|> |
| DCM | | | DCM | | DDR Q|--
>sdram clk
+->| CLKFB | | +->| CLKFB CLK180 |-->o|>
| |
| +-----------------+ | | +------------------+ +-------
+ |
| |
| |
+----------------------+
+------------------------------------------+
This follows the recommendation on p. 7 of DS492 (the MC OPB SDRAM
Controller) in the EDK. The addition of the DDR register was a
suggestion from our FAE and follows the recommendation on p. 111 of
UG331. The DDR register is packed into the I/O and gives a clean,
sharp clock signal.
The issue is how to reset the second DCM appropriately to make sure it
locks onto a clean signal. I understand the need for the SRL16, so
that the SDRAM DCM can get a clean lock. However, on p. 101 of UG331,
Figure 3-19 shows the clock to the SRL16 being connected to CLKIN. At
high speeds (100MHz or so) it only takes 160ns for the SRL16 to clear
out. This means from the time from the end of the startup sequence to
GTS deasserting must be less than 160ns. However, I cannot find any
reference to the actual time from DCM startup to GTS deassertion.
It seems to me that the SRL16 in Figure 3-19 should be clocked by the
feedback clock. This way the reset pulse occurs after the feedback
clock is present, which is after GTS deasserts.
Any thoughts?
Article: 121382On Jul 3, 11:12 am, "comp.arch.fpga" <ksuli...@googlemail.com> wrote: > On 3 Jul., 15:24, cs_post...@hotmail.com wrote: > > > On Jul 3, 8:02 am, AugustoEinsfeldt <a...@terra.com.br> wrote: > > > > I may stick to the pull-down resistor idea because the system MTBF. > > > Resistors cause less impact here. > > > My concern with the pulldown resistors would be, what if one of them > > doesn't effectively installed (open)? The board will probably work > > just fine. But now the protection diode will be taking all the > > current. If that's okay, fine - but if it's not, presumably the worry > > that caused you to put the resistors there in the first place, then > > you have a board that might fail early. > > So use a number of resistors in parallel and include the voltage at > these nodes > into the production test procedure. > > Kolja An open resistor would fall in the MTBUR prediction since every unit shall be stressed in thermal and vibration cycles for infant mortality. More resistors in parallel would reduce the system MTBF. The best would be to have a T like structure (2 resistors and a zener or TVS) in a device with MTBF as high as single resistors or single diode. This would improve the overall system but I don't know if it does exist. -AugustoArticle: 121383
ram wrote:
> I am prototyping a IP core which was written in verilog languge in
> cyclone II FPGA.My application engineer wrote code in C for
> application level.Can i simulate the both in cadence simulation
> environment so that i can find the bug in real environment .Can anyone
> suggest on this.I am in desperate situation.Please help me.
I would work on STA and on increasing coverage
on my functional fpga and memory testbench. Once that is
verified the apps guy can use a software debugger.
-- Mike Treseler
Article: 121384The multipliers in Altera Stratix FPGAs can be operated in a Q1.15 fractional binary mode that I have found to be useful in a previous project. If the Xilinx multipliers can be operated in a similar mode it might be a/the answer to your problem.Article: 121385
i am using MPC 8321E POWER PC ,can any one tell me how to interface 2GBYTE DDR2 SDRAM. problem is it has only 32 bit data bus. regards anandArticle: 121386
pladow, Use the Locked signal from the first DCM to release resetting the second DCM. Locked ---> invert -----> Reset AustinArticle: 121387
On Jul 2, 7:47 pm, Matthew Hicks <mdhic...@uiuc.edu> wrote: > By the way, the programming model for the cell is by far worse > than anything I've seen on an FPGA, and the programming model for video cards > in the user domain isn't much better, but it's getting there as Nvidia prioritizes > it higher. As a programming model, having to design circuits around an array of DSP and bRAM slices is BY FAR MUCH MORE OF A HORRIBLE PROGRAMMING MODEL ... and a LOT more effort when you also have to fight timing closure, placement, layout, etc. That array of DSP slices exists exactly to exploit this same market ... and lacking competitive system level solutions (packaged hardware and software) the volumes for these parts will ultimately be lacking, and with it a self fulfilling promise that the tools will never mature behind them either. Nvidia is simply doing with GPUs, what Xilinx should have done (or allowed to be done) to get their chips out front as a easy to use gigaflop/teraflop systems level product to drive embedded comodity volume sales. I personally still believe FPGAs offer greater promise, but only if there is a systems level vision behind the product to allow it to mature before becoming obsolete.Article: 121388
<anandraj7k@gmail.com> wrote in message news:1183480237.874553.200500@z28g2000prd.googlegroups.com... >i am using MPC 8321E POWER PC ,can any one tell me how to interface > 2GBYTE DDR2 SDRAM. > > problem is it has only 32 bit data bus. > > regards anand Use 32-bit modules. They aren't PC mainstream, but they are available.Article: 121389
<Eddie H> wrote in message news:eea7bce.-1@webx.sUN8CHnE... >I would like to know why the coregen software uses the PLL to generate the >two user clocks - one for the GTP and one for the fpga fabric? There are >very limited number of PLLs so why not use the DLL for this task? I haven't looked at V5 GTPs or PLLs for that matter at all yet. So, what follows is just a guess... Maybe jitter spec for PLL is better? Or maybe you choose a frequency that can't be produced with a DLL? /MikhailArticle: 121390
I am trying to get an xc3s250e-4tq144c to configure using JTAG.
1. impact reads 0x00000000 as idcode
This causes impact to error out during identify with a strange
error about missing bsdl's
2. JTAG works using impact debug mode. I can put it in bypass and
also see the length of the instruction register. I can see data
shifting in and out so I know JTAG works.
3. Part markings are:
XC3250E
TQ144AGQ0601
D1392255A0
4C
so it is a step 0 part.
4. I have tried impact 8.1.3 and 9.1
5. I get identical results with two pc boards.
6. Same software / computer / cable setup works fine with a virtex2p
design.
7. All power supplies look good. (1.2Vint, 2.5Vaux, 3.3Vio)
8. spartan-3e is the only part in the JTAG chain.
I have tried removing all the parts except the spartan and power to
make sure nothing else was interfering with it.
I have not made any progress with my Avnet FAE and Xilinx webcase so I
thought to try here.
I have run out of things to try. Does this look familiar to anyone?
Any ideas to try?
Alan Nishioka
alan@nishioka.com
Article: 121391On 3 Jul., 20:06, Alan Nishioka <a...@nishioka.com> wrote: > I am trying to get an xc3s250e-4tq144c to configure using JTAG. > > 1. impact reads 0x00000000 as idcode > This causes impact to error out during identify with a strange > error about missing bsdl's > 2. JTAG works using impact debug mode. I can put it in bypass and > also see the length of the instruction register. I can see data > shifting in and out so I know JTAG works. > 3. Part markings are: > XC3250E > TQ144AGQ0601 > D1392255A0 > 4C > so it is a step 0 part. > 4. I have tried impact 8.1.3 and 9.1 > 5. I get identical results with two pc boards. > 6. Same software / computer / cable setup works fine with a virtex2p > design. > 7. All power supplies look good. (1.2Vint, 2.5Vaux, 3.3Vio) > 8. spartan-3e is the only part in the JTAG chain. > > I have tried removing all the parts except the spartan and power to > make sure nothing else was interfering with it. > > I have not made any progress with my Avnet FAE and Xilinx webcase so I > thought to try here. > > I have run out of things to try. Does this look familiar to anyone? > Any ideas to try? > > Alan Nishioka > a...@nishioka.com prog_b is high? AnttiArticle: 121392
I've spent several hours browsing the Xilinx site (and not so much less the Altrera site), and I'm starting to get some idea of what all the different device families are. However, after digging through numerous pdfs, it looks like everything is 3.3v and under. All of the cool stuff I'd like to try to do interfaces with old computers, vintage stuff. How does one interface to TTL logic? Which devices can be used for that, and what does it take to safely hook them up to something that is 5v? (Note: I realize that some/all of the Xilinx cpld's can do 5v, but I'm really wanting to play with something heftier.)Article: 121393
Mikhail, Good guess. The V5 PLL does attenuate jitter, so to get the best possible, lowest jitter clock, this is the choice. Not using the PLL will most likely work just fine, it is just that one would have to verify that the transmit jitter was within whatever applicable specification. As well, the receive input jitter tolerance would also have to be verified. Check the characterization reports for the standard(s) of interest, and see how the tests were done. If they used the V5 PLL, then if you do not use it, you should repeat these tests (to be sure your source clock is good enough). If they did not use this resource, then no issue. I haven't checked these out, so I will go do a little light reading. AustinArticle: 121394
<john.m.oyler@gmail.com> wrote in message news:1183486887.598253.267900@w5g2000hsg.googlegroups.com... > > How does one interface to TTL logic? Which devices can be used for > that, and what does it take to safely hook them up to something that > is 5v? What do you need TTL logic for if you have an FPGA? What is it you are trying to build? If you really need to interface to 5V logic you could use some of the level translation techniques/devices... Just google on level translation and you'll find a bunch of ideas.... /MikhailArticle: 121395
<john.m.oyler@gmail.com> wrote in message news:1183486887.598253.267900@w5g2000hsg.googlegroups.com... > > However, after digging through numerous pdfs, it looks like everything > is 3.3v and under. All of the cool stuff I'd like to try to do > interfaces with old computers, vintage stuff. > > How does one interface to TTL logic? Which devices can be used for > that, and what does it take to safely hook them up to something that > is 5v? > Hi John, Here's an example of one way of doing it. http://www.enterpoint.co.uk/component_replacements/craignell.html HTH., Syms.Article: 121396
On Jul 3, 11:13 am, Antti <Antti.Luk...@googlemail.com> wrote: > On 3 Jul., 20:06, Alan Nishioka <a...@nishioka.com> wrote: > > > > > I am trying to get an xc3s250e-4tq144c to configure using JTAG. > > > 1. impact reads 0x00000000 as idcode > > This causes impact to error out during identify with a strange > > error about missing bsdl's > > 2. JTAG works using impact debug mode. I can put it in bypass and > > also see the length of the instruction register. I can see data > > shifting in and out so I know JTAG works. > > 3. Part markings are: > > XC3250E > > TQ144AGQ0601 > > D1392255A0 > > 4C > > so it is a step 0 part. > > 4. I have tried impact 8.1.3 and 9.1 > > 5. I get identical results with two pc boards. > > 6. Same software / computer / cable setup works fine with a virtex2p > > design. > > 7. All power supplies look good. (1.2Vint, 2.5Vaux, 3.3Vio) > > 8. spartan-3e is the only part in the JTAG chain. > > > I have tried removing all the parts except the spartan and power to > > make sure nothing else was interfering with it. > > > I have not made any progress with my Avnet FAE and Xilinx webcase so I > > thought to try here. > > > I have run out of things to try. Does this look familiar to anyone? > > Any ideas to try? > > > Alan Nishioka > > a...@nishioka.com > > prog_b is high? > > Antti Yes. Originally it had a 10K pullup. One of the things I tried was lifting this pin so it relies on the internal pullup. Also measured high with a scope. AlanArticle: 121397
On 3 Jul., 20:35, Alan Nishioka <a...@nishioka.com> wrote: > On Jul 3, 11:13 am, Antti <Antti.Luk...@googlemail.com> wrote: > > > > On 3 Jul., 20:06, Alan Nishioka <a...@nishioka.com> wrote: > > > > I am trying to get an xc3s250e-4tq144c to configure using JTAG. > > > > 1. impact reads 0x00000000 as idcode > > > This causes impact to error out during identify with a strange > > > error about missing bsdl's > > > 2. JTAG works using impact debug mode. I can put it in bypass and > > > also see the length of the instruction register. I can see data > > > shifting in and out so I know JTAG works. > > > 3. Part markings are: > > > XC3250E > > > TQ144AGQ0601 > > > D1392255A0 > > > 4C > > > so it is a step 0 part. > > > 4. I have tried impact 8.1.3 and 9.1 > > > 5. I get identical results with two pc boards. > > > 6. Same software / computer / cable setup works fine with a virtex2p > > > design. > > > 7. All power supplies look good. (1.2Vint, 2.5Vaux, 3.3Vio) > > > 8. spartan-3e is the only part in the JTAG chain. > > > > I have tried removing all the parts except the spartan and power to > > > make sure nothing else was interfering with it. > > > > I have not made any progress with my Avnet FAE and Xilinx webcase so I > > > thought to try here. > > > > I have run out of things to try. Does this look familiar to anyone? > > > Any ideas to try? > > > > Alan Nishioka > > > a...@nishioka.com > > > prog_b is high? > > > Antti > > Yes. Originally it had a 10K pullup. One of the things I tried was > lifting this pin so it relies on the internal pullup. Also measured > high with a scope. > > Alan- Zitierten Text ausblenden - > > - Zitierten Text anzeigen - and you are not pulling init_b low either? strange I had no issues with 250e on my self made boards AnttiArticle: 121398
Antti, I even hate to bring this up, but how do we know it really is the part it is supposed to be? We have seen counterfeit parts (some odd die, packaged, and marked as Xilinx) sold to unsuspecting people by "gray market" resellers... If it doesn't wake up, and say "I am the Xilinx FPGA you expect me to be" perhaps it isn't? I certainly hope this is a simple case of a mis-wired pcb, and not a case of bogus components sold to an unsuspecting buyer. AustinArticle: 121399
Antti, Further, we have seen where old board test continuity systems apply voltages (and currents) that my damage the newer 90nm and smaller devices. I certainly hope no one exceeded the absolute maximum voltage stress limits, and has damaged the parts. Austin
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Compare FPGA features and resources
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