Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarAprMayJunJulAugSepOctNovDec2017
2018JanFebMarAprMayJunJulAugSepOctNovDec2018
2019JanFebMarAprMayJunJulAugSepOctNovDec2019
2020JanFebMarAprMay2020

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search

Messages from 128425

Article: 128425
Subject: Re: Initialize RAM in IGLOO
From: Antti <Antti.Lukats@googlemail.com>
Date: Fri, 25 Jan 2008 06:59:31 -0800 (PST)
Links: << >>  << T >>  << A >>
On 25 Jan., 15:33, Kris Vorwerk <kris.vorw...@gmail.com> wrote:
> > Can anyone help me with how I can make this part of the RAM (from addres=
s 0
> > and forward) initialized with the content of my Intel Hex File even afte=
r
> > synthesis?
>
> SRAM blocks in PA3/Fusion/Igloo are initialized via the UJTAG
> interface or from the design logic. =A0You might find this helpful:
>
> http://www.actel.com/documents/Fusion_RAM_FIFO_AN.pdf
>
> Although I've never tried, it may be possible to use the Igloo's
> FlashROM (along with a bit of design logic) to initialize the RAM
> (although, this may or may not be enough data for what you want to
> initialize).
>
> regards,
> Kris

NONO, there is no JTAG access to the RAM (like it is available in
xilinx)

there is possibility to ADD USER LOGIC connected to UJTAG that
will allow the rams to be loaded, but it also needs external JTAG tap
master to actually load the init data

the flashROM is way too small, so not an option at all.

so whatever you do, you need USER logic to WRITE tot he RAM
so there is no real init possible, means user logic writes AFTER
the FPGA comes alive, the RAMs are not initialized during power up

Antti













Article: 128426
Subject: Re: Random Number Generation in VHDL
From: Jonathan Bromley <jonathan.bromley@MYCOMPANY.com>
Date: Fri, 25 Jan 2008 15:13:14 +0000
Links: << >>  << T >>  << A >>
On Fri, 25 Jan 2008 06:44:10 -0800 (PST), 
Ann <thakkar.anuja@gmail.com> wrote:

>I just found out that I need random number generator just for
>simulation. I do not need to synthesize it. Some feedback on this
>would be helpful. I am having a look at some of the links posted here.

OK, that's easy.  The math_real package contains an excellent
random number generator that you can adapt for your own purposes.

  use ieee.math_real.all;
  ...
  process
    variable R: real;
    variable S1, S2: positive := 42;
    --- seed variables, change initialization to
    --- get a different random number stream
  begin
    ...
    uniform(S1, S2, R);
    ...

This modifies seed variables S1 and S2 ready for the
next call to uniform() - DON'T DO ANYTHING ELSE with
these two variables.  And it also puts a random number
into R, uniformly distributed in the real range 0.0 to
0.99999...; you can then very easily scale this
number to get whatever you want.  A couple of examples:

  --- Get the integer value "5" with 20% probability,
  --- and "7" with 80% probability
  if R < 0.2 then 
    x := 5;
  else
    x := 7;
  end if;
  ---
  --- Get an integer in the range LO to HI (where LO, HI
  --- are both integers and LO<=HI)
  R := R * real(HI-LO) + real(LO);
  x := integer(floor(R));

HTH
-- 
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which 
are not the views of Doulos Ltd., unless specifically stated.

Article: 128427
Subject: Re: Random Number Generation in VHDL
From: Jonathan Bromley <jonathan.bromley@MYCOMPANY.com>
Date: Fri, 25 Jan 2008 15:20:52 +0000
Links: << >>  << T >>  << A >>
On Fri, 25 Jan 2008 15:13:14 +0000,
Jonathan Bromley wrote:

>OK, that's easy.

Not so easy, it seems: apologies for this 
off-by-one error...

>  --- Get an integer in the range LO to HI (where LO, HI
>  --- are both integers and LO<=HI)
>  R := R * real(HI-LO) + real(LO);

That should be
   R := R * real(HI+1-LO) + real(LO);

Sorry
-- 
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which 
are not the views of Doulos Ltd., unless specifically stated.

Article: 128428
Subject: OV7660 CMOS camera
From: chakra <narashimanc@gmail.com>
Date: Fri, 25 Jan 2008 08:57:49 -0800 (PST)
Links: << >>  << T >>  << A >>
Hi all,

Am working with this camera. wanted to know if anyone else has worked
with it before. I have a set of register settings and want to know if
that is right. i am working towards getting a RGB 555 VGA 640x480
configuration here is the register settings.

0x12,	0x80,
5ms delay
0x11,	0x81,
0x9E,	0x3f,
0x3B,	0x02,
0x13,	0xF2,

0x00,	0x00,
0x10,	0x00,
0x01,	0x80,
0x02,	0x80,
0x13,	0xF7,

0x12,	0x04,

0x04,	0x00,
0x0C,	0x00,

0x18,	0x61,
0x17,	0x11,
0x32,	0x89,

0x19,	0x02,
0x1A,	0x7A,
0x03,	0x00,

0x0E,	0x84,
0x0F,	0x62,
0x15,	0x02,
0x1B,	0x01,
0x1E,	0x01,
0x29,	0x3C,
0x33,	0x00,
0x34,	0x07,
0x35,	0x84,
0x36,	0x00,
0x38,	0x13,
0x39,	0x43,
0x3C,	0x68,
0x3D,	0x19,

0x40,	0xF1,

0x69,	0x80,
0x6B,	0x0A,
0xA1,	0x08,

0x8B,	0xCC,
0x8C,	0xCC,
0x8D,	0xCF,

0x14,	0x2E,
0x25,	0x58,
0x24,	0x68,

if anyone has worked on it before please do check the above config and
correct if something is wrong or i need to change something.

cheers!
chakra.

PS: I have based this setting on one other setting sent by the tech
support of the Omnivision.

Article: 128429
Subject: Re: Craignell FPGA DIP Module
From: Gabor <gabor@alacron.com>
Date: Fri, 25 Jan 2008 09:12:45 -0800 (PST)
Links: << >>  << T >>  << A >>
On Jan 25, 6:50 am, John Adair <g...@enterpoint.co.uk> wrote:
> Craignell user manual is now availablehttp://www.enterpoint.co.uk/component_replacements/CraignellUserManua....
> We also have UCF file available for the CR40 and the other sizes to
> follow shortly.
>
> John Adair
> Enterpoint Ltd.

Very interesting.  What do you mean by:

Craignell is currently available in 4 pinout sizes - 28 pins, 32 pins,
36 pins and 36 pins.

When is 36 pins not 36 pins ?

Article: 128430
Subject: Endpoint Block Plus v1.5 example design
From: miriemer@rumms.uni-mannheim.de
Date: Fri, 25 Jan 2008 09:13:03 -0800 (PST)
Links: << >>  << T >>  << A >>
Hello,

I'm trying to get running the example design coming with Endpoint
Block Plus v1.5.
I have generated the core with ise's coregen and compiled the
smartmodel libs also with with ise.
But when starting the simulation the following happens:


ncsim: 06.11-s002: (c) Copyright 1995-2007 Cadence Design Systems,
Inc.


***** Registering Synopsys SWIFT PLI tasks *****

      Runtime, LMTV v12.33
      Copyright (c) 1984-2008 Synopsys Inc. ALL RIGHTS RESERVED
      Platform Type: linux (32-bit).
      You can use the Browser tool to configure the SmartModel
      Library and access information about SmartModels:
         $LMC_HOME/bin/sl_browser

      SmartModel product documentation is available here:
         $LMC_HOME/doc/smartmodel/manuals/intro.pdf
         http://www.synopsys.com/products/lm/doc/smartmodel.html

(LMTV) (3027)Error: number of instance pins in Verilog: '1353', does
not match swift: '1325'

Note: Model pcie_internal_1_1_swift: Model Vendor: `Xilinx'.
      SmartModel Instance boardx01.xilinx_pci_exp_1_lane_ep.ep.\BU2/U0/
pcie_ep0/pcie_blk/
pcie_ep .pcie_internal_1_1_swift_1.I1(PCIE_INTERNAL_1_1_SWIFT:pcie_internal_1_1_swift),
at time 0.0 ns

Note: Model gt11_swift: Model Vendor: `Xilinx'.
      SmartModel Instance
boardx01.xilinx_pci_exp_1_lane_downstream_port.xilinx_pci_exp_1_lane_dsport.pci_exp_1_lane_64b_dsport.plm_v4f_mgt_gt11_by1_GT11_PCIEXP_2_INST.gt11_swift_1.I1(GT11_SWIFT:gt11_swift),
at time 0.0 ns
ncsim> run
Running default test {sample_smoke_test0}......
[                   0] : System Reset Asserted...
[             4995000] : System Reset De-asserted...
[             8522100] : Transaction Reset Is De-asserted...

and then nothing else.


Can someone tell me what I could've done wrong? Perhaps something with
the compilation of the libs?
Or does someone know what to do with this "(LMTV) (3027)Error"? I
can't find anything on this error in the internet or anywhere else.

Thanks in advance.
Michael

Article: 128431
Subject: Re: Craignell FPGA DIP Module
From: Jonathan Bromley <jonathan.bromley@MYCOMPANY.com>
Date: Fri, 25 Jan 2008 17:49:53 +0000
Links: << >>  << T >>  << A >>
On Fri, 25 Jan 2008 09:12:45 -0800 (PST), 
Gabor <gabor@alacron.com> wrote:

>When is 36 pins not 36 pins ?

When it's a typo for 40, I think.  C'mon, give the
guy a break - we all make tripyng mshtks.
-- 
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which 
are not the views of Doulos Ltd., unless specifically stated.

Article: 128432
Subject: Re: Random Number Generation in VHDL
From: "Dwayne Dilbeck" <ddilbeck@yahoo.com>
Date: Fri, 25 Jan 2008 10:40:11 -0800
Links: << >>  << T >>  << A >>
I usually use a maximal LFSR to obtain psuedo random numbers.

The following link will give you some good information.
www.xilinx.com/ipcenter/catalog/logicore/docs/lfsr.pdf

I like Appendix B wich lists the tap points up to 168bits for a maximal 
length LFSR.

The following would generate psudeo random 64 bit numbers starting with seed 
value 1.

entity generator is
  port (
     clk:in bit;
     a:out bit_vector(63 downto 0));
end;


achitecture processflow of generator is
begin
    CLKED:process
             variable temp:bit_vector(63 downto 0) := 
X"0000_0000_0000_0001";
    begin
                 temp := temp(63 downto 0 )  & (temp(63) xor temp(62) );
                a <= temp;
                wait until (clk = '0');
     end process
end

"glen herrmannsfeldt" <gah@ugcs.caltech.edu> wrote in message 
news:k4qdnWK4LOGX5wTanZ2dnUVZ_sHinZ2d@comcast.com...
> FPGA wrote:
>
>> I would like to know if VHDL already has functions defined to generate
>> Random Numbers.
>
>> If not, which would be the best algorithm for generating random
>> numbers for implementation on an FPGA.
>
> LFSR are pretty popular for random numbers, and very easy to
> implement in an FPGA.
>
> -- glen
> 



Article: 128433
Subject: Thoughts about memory controller problems
From: "jack.harvard@googlemail.com" <jack.harvard@googlemail.com>
Date: Fri, 25 Jan 2008 10:47:24 -0800 (PST)
Links: << >>  << T >>  << A >>
Hi,

I tried to boot Linux on my FPGA-prototyped SoC system. The Linux
image is running from SDRAM which is controlled by a Dynamic Memory
Controller, but the Linux boot always stop at somewhere around(not at
the same point each time):
Mount-cache hash table entries: 512
<6>CPU: Testing write buffer coherency: ok

I thought this could possibly point to some obscure timing issues of
the memory controller, as 1) Modelsim simulation didn't point to any
memory controller issues 2) the memory controller is on a different
board from the actual SDRAM 3) tools like Synplify and ISE are not
reliable from my limited experience 4) latches might also cause
problems.

I'm asking for thoughts about what can go wrong when prototyping a
memory controller into an FPGA. Please kindly offer your insights with
memory controllers especially if you had similar problems before.

Thanks a lot,

Article: 128434
Subject: Re: Random Number Generation in VHDL
From: Jonathan Bromley <jonathan.bromley@MYCOMPANY.com>
Date: Fri, 25 Jan 2008 18:54:18 +0000
Links: << >>  << T >>  << A >>
On Fri, 25 Jan 2008 10:40:11 -0800, 
Dwayne Dilbeck wrote:

>I usually use a maximal LFSR to obtain psuedo random numbers.
>
>The following link will give you some good information.
>www.xilinx.com/ipcenter/catalog/logicore/docs/lfsr.pdf
>
>I like Appendix B wich lists the tap points up to 168bits for a maximal 
>length LFSR.
>
>The following would generate psudeo random 64 bit numbers starting with seed 
>value 1.
>
>entity generator is
>  port (
>     clk:in bit;
>     a:out bit_vector(63 downto 0));
>end;
>
>
>achitecture processflow of generator is
>begin
>    CLKED:process
>             variable temp:bit_vector(63 downto 0) := 
>X"0000_0000_0000_0001";
>    begin
>                 temp := temp(63 downto 0 )  & (temp(63) xor temp(62) );
>                a <= temp;
>                wait until (clk = '0');
>     end process
>end

aaargh.... note that this gives you one pseudo-random BIT per
clock cycle.... but the 64-bit words are painfully strongly
correlated from one cycle to the next.  You need to clock 
your N-bit LFSR for at least N cycles before pulling the 
next N-bit value from it.

Even then, the random numbers aren't brilliantly random
(or at least that's what I am led to understand - I don't
have a particularly good grip on the somewhat scary math)
but LFSRs are indeed a good source of quasi-random stuff
for non-critical applications.  Just remember to clock
them enough times!
-- 
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which 
are not the views of Doulos Ltd., unless specifically stated.

Article: 128435
Subject: Re: Random Number Generation in VHDL
From: glen herrmannsfeldt <gah@ugcs.caltech.edu>
Date: Fri, 25 Jan 2008 11:01:35 -0800
Links: << >>  << T >>  << A >>
Ann wrote:
(snip)

> I just found out that I need random number generator just for
> simulation. I do not need to synthesize it. Some feedback on this
> would be helpful. I am having a look at some of the links posted here.

LFSR are fairly popular now for software implementations, though
linear congruential generators are also still popular.

Linear congruential is probably easy for simulation, not quite
as easy as LFSR for synthesis.

The favorite reference is Knuth, "The Art of Computer Programming",
volume 2.  Worth having for anyone working with computers.

-- glen


Article: 128436
Subject: Re: Thoughts about memory controller problems
From: PFC <lists@peufeu.com>
Date: Fri, 25 Jan 2008 20:04:52 +0100
Links: << >>  << T >>  << A >>

	Set your SDRAM clock to "as low as possible to get correct refresh of the  
SDRAM". If it then works, you have a timing problem. If it doesn't work,  
you have another problem.

> I'm asking for thoughts about what can go wrong when prototyping a
> memory controller into an FPGA. Please kindly offer your insights with
> memory controllers especially if you had similar problems before.

	I have a Suzaku FPGA module. This has SDRAM, an Ethernet MAC (LAN  
91c111), and a parallel Flash, all sharing the same external bus.  
Therefore, the FPGA contains an opb_sdram controller, an controller for  
the MAC, and a controller for the Flash, and a MUX to send the right  
signals from the right controller to the external bus according to  
whatever the CPU is accessing at any given time.
	This works, but the access to the MAC was too slow, so I added another  
core of mine to handle direct copy of packets from the MAC's internal  
buffer to a BRAM (the CPU can then parse the packet from BRAM which is  
much faster than re-reading it from SDRAM).
	The point that will be of interest to you is that, with the external MUX  
now having 4 inputs instead of 3, xst had to add another level of muxing,  
and all hell broke loose. It worked before, but this was luck since the  
timing constraint that would have specified that the time spent going  
through the MUX without going over the SDRAM's setup time requirements was  
missing. Plus I had no way to specify this constraint since I don't know  
the time it takes for the signal to propagate in the PCB traces. So I had  
to hand-place the stuff to get correct timing. So if your SDRAM is on  
another board, I'd say it smells of timing issues. Make it run at 1 MHz or  
something (but first check if that's allowed in the datasheet) and you'll  
know.
	Xilinx tools can apply timing constraints to whatever happens inside the  
FPGA, but they have no knowledge of the delay that may happen on your PCB  
traces, unless you tell it...

	How long is the signal path ?

	Alternately you could use clock feedback with the Xilinx sdram  
controller, where the controller sends the clock to the SDRAM, the clock  
then comes back in another trace and is used as an input, so the  
controller can take the prpgagation delay into account.

Article: 128437
Subject: Re: Virtex-4 driving a 5V CMOS
From: PFC <lists@peufeu.com>
Date: Fri, 25 Jan 2008 20:09:58 +0100
Links: << >>  << T >>  << A >>

> Hi all,
>
> I need to drive a 5V CMOS input from a 2.5V Virtex-4 bank. Is there  
> anything
> wrong with simply using a pullup to 5V? The speed doesn't matter.

	This is not recommended practice... the FPGA's protection diodes aren't  
going to be happy.
	If you only have 1 signal, and you don't care if it's slow, you can just  
use a SMD transistor to make an open collector/drain from your FPGA  
output, or an HCT IC, or an HCT picogate... or even simpler replace your  
5V CMOS IC by an HCT if possible.
	If you need something more elaborate, there are zillions of voltage  
translator chips...

Article: 128438
Subject: Re: Random Number Generation in VHDL
From: Mike Treseler <mike_treseler@comcast.net>
Date: Fri, 25 Jan 2008 11:31:59 -0800
Links: << >>  << T >>  << A >>
some typos:

> achitecture processflow of generator is

  architecture

> temp := temp(63 downto 0 )  & (temp(63) xor temp(62) );
                         1
> end  process
              ;
> end
      ;

Article: 128439
Subject: Re: Craignell FPGA DIP Module
From: John Adair <g1@enterpoint.co.uk>
Date: Fri, 25 Jan 2008 11:35:56 -0800 (PST)
Links: << >>  << T >>  << A >>
Thanks guys, I think we are suffering from too many new things in the
engine at once.

I have had an updated posted. Pinouts for the CR28, CR32 and CR36 now
also included as well. New link
http://www.enterpoint.co.uk/component_replacements/Craignell_User_Manual_Iss=
ue_1_01.pdf.

John Adair
Enterpoint Ltd.

On 25 Jan, 17:49, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com>
wrote:
> On Fri, 25 Jan 2008 09:12:45 -0800 (PST),
>
> Gabor <ga...@alacron.com> wrote:
> >When is 36 pins not 36 pins ?
>
> When it's a typo for 40, I think. =A0C'mon, give the
> guy a break - we all make tripyng mshtks.
> --
> Jonathan Bromley, Consultant
>
> DOULOS - Developing Design Know-how
> VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services
>
> Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
> jonathan.brom...@MYCOMPANY.comhttp://www.MYCOMPANY.com
>
> The contents of this message may contain personal views which
> are not the views of Doulos Ltd., unless specifically stated.


Article: 128440
Subject: Re: Random Number Generation in VHDL
From: sly <sly@none>
Date: Fri, 25 Jan 2008 21:56:43 +0100
Links: << >>  << T >>  << A >>
Mike Treseler a écrit :
> some typos:
> 
>> achitecture processflow of generator is
> 
>   architecture
> 
>> temp := temp(63 downto 0 )  & (temp(63) xor temp(62) );
>                          1
>> end  process
>               ;
>> end
>       ;

temp := temp(62 downto 0)  & (temp(63) xor temp(62) );

(shift register)

Article: 128441
Subject: Re: Random Number Generation in VHDL
From: "Dwayne Dilbeck" <ddilbeck@yahoo.com>
Date: Fri, 25 Jan 2008 13:30:05 -0800
Links: << >>  << T >>  << A >>
I was quickly typing an example.  I didn't even copy paste from my old vhdl 
code. or even verify the code would parse correctly.   Have to leave some 
thing for others to do.

Sly's and Mike's corrections are what the code should have had.


"Mike Treseler" <mike_treseler@comcast.net> wrote in message 
news:5vurphF1ljgbkU1@mid.individual.net...
> some typos:
>
>> achitecture processflow of generator is
>
>  architecture
>
>> temp := temp(63 downto 0 )  & (temp(63) xor temp(62) );
>                         1
>> end  process
>              ;
>> end
>      ; 



Article: 128442
Subject: Re: Random Number Generation in VHDL
From: glen herrmannsfeldt <gah@ugcs.caltech.edu>
Date: Fri, 25 Jan 2008 13:51:57 -0800
Links: << >>  << T >>  << A >>
Jonathan Bromley wrote:

> On Fri, 25 Jan 2008 10:40:11 -0800, 
> Dwayne Dilbeck wrote:

>>I usually use a maximal LFSR to obtain psuedo random numbers.

>>The following link will give you some good information.
>>www.xilinx.com/ipcenter/catalog/logicore/docs/lfsr.pdf

>>I like Appendix B wich lists the tap points up to 168bits for a maximal 
>>length LFSR.

>>The following would generate psudeo random 64 bit numbers starting with seed 
>>value 1.

>>entity generator is
>> port (
>>    clk:in bit;
>>    a:out bit_vector(63 downto 0));
>>end;

>>achitecture processflow of generator is
>>begin
>>   CLKED:process
>>            variable temp:bit_vector(63 downto 0) := 
>>X"0000_0000_0000_0001";
>>   begin
>>                temp := temp(63 downto 0 )  & (temp(63) xor temp(62) );
>>               a <= temp;
>>               wait until (clk = '0');
>>    end process
>>end

> aaargh.... note that this gives you one pseudo-random BIT per
> clock cycle.... but the 64-bit words are painfully strongly
> correlated from one cycle to the next.  You need to clock 
> your N-bit LFSR for at least N cycles before pulling the 
> next N-bit value from it.

It doesn't look like a very good one, either.  You want
one based on a primitive polynomial

http://en.wikipedia.org/wiki/Primitive_polynomial

which is sort of related to a prime number.  There is a good
explanation in "Numerical Recipes" including some primitive
polynomials.  The CRC32 polynomial has been well studied,
and should have pretty good properties.  For 64 bits you could
use multiple LFSR of different lengths and generate a new value
in much less than 64 cycles.

-- glen


> Even then, the random numbers aren't brilliantly random
> (or at least that's what I am led to understand - I don't
> have a particularly good grip on the somewhat scary math)
> but LFSRs are indeed a good source of quasi-random stuff
> for non-critical applications.  Just remember to clock
> them enough times!


Article: 128443
Subject: Re: microblaze question
From: mmihai <iiahim@yahoo.com>
Date: Fri, 25 Jan 2008 18:33:10 -0800 (PST)
Links: << >>  << T >>  << A >>
On Jan 25, 12:24 am, taco <trala...@joepie.nl> wrote:

> Right now I'm running an opencore 8051 which works fine and can be
> programmed in C, but for the project I'm doing it could be that this runs
> too slow and cannot handle to dataflow entering a FIFO. microblaze would
> certainly solve it unless I have to add hardware.

What is the complexity of your code?

If you want to minimize the code to fit inside block RAMs the 8051
might not be your best choice.
You can find some comparison data on my proc4 web page: http://www.delajii.net/proc4

As a note, a MCU based on proc4 core fits in a spartan3 50 (i.e. the
smallest) using only the internal RAM, making use of [almost] all pins
(as I/Os).

--
mmihai

Article: 128444
Subject: Re: CynApps Cynlib
From: Amal <akhailtash@gmail.com>
Date: Fri, 25 Jan 2008 18:45:28 -0800 (PST)
Links: << >>  << T >>  << A >>
On Jan 18, 8:55 am, Amal <akhailt...@gmail.com> wrote:
> On Jan 17, 3:07 pm, John McCaskill <jhmccask...@gmail.com> wrote:
>
>
>
> > On Jan 17, 1:43 pm, Amal <akhailt...@gmail.com> wrote:
>
> > > On Jan 17, 11:43 am, Uncle Noah <nk...@skiathos.physics.auth.gr>
> > > wrote:
>
> > > > On Jan 17, 5:59 am, Amal <akhailt...@gmail.com> wrote:
>
> > > > > Does anyone have a copy of Forte Design (CynApps) opensource Cynlib?
>
> > > > > I appreciate if you can send me a copy.
> > > > > -- Amal
>
> > > > Hi
>
> > > > i have this one: cynlib.1.2.1.source.tar.gz (3,876,003bytes)
>
> > > > I'll check the licensing issues (if i can pass it to you or not). But,
> > > > first of all, is this version OK for you?
>
> > > > And what about the company, it might be best if you asked them about
> > > > the legality of this.
>
> > > > Kind regards
> > > > Nikolaos Kavvadias
>
> > > I searched the net.  They released this and another tool to open
> > > source community a long time ago.  There is no mention of this
> > > anywhere on their web site anymore.
>
> > > Whatever version is fine.  Not looking for any specific version
> > > really.
>
> > > -- Amal
>
> > The Wayback machine has the cynapps web site in the archives, but the
> > couple of pages that I clicked on the download button brought up a
> > registration form. You might take a deeper look at that site and see
> > if you can find it in one of the archives:
>
> >http://web.archive.org/web/*/http://www.cynapps.com
>
> > You might also try asking on the geda mail list.  A search turned up
> > several people on one of those list discussing it that are still
> > participating in the list. Maybe one of them has a copy of it. See :
>
> >http://geda.seul.org/mailinglist/index.html
>
> > and use the search function on cynlib.
>
> > Good luck,
>
> > John McCaskillwww.FasterTechnology.com
>
> Thanks John.  I checked all that.  And those messages are way too
> old.  I had no success finding it yet.
>
> -- Amal

Can anyone provide a copy of this library?

-- Amal

Article: 128445
Subject: Re: Speed of remote JTAG with Quartus jtagd on linux
From: vaughnbetz@gmail.com
Date: Fri, 25 Jan 2008 19:54:55 -0800 (PST)
Links: << >>  << T >>  << A >>
Hi Ben,

The JTAG server implements the active serial protocol using a large
number of small data transfers across the client/server interface,
while JTAG and passive serial programming use a comparatively small
number of large data transfers.  So the speed of active serial
programming mode is more sensitive to the network latency between the
client and server than passive serial programming.  If you can reduce
the network latency between the client and server it will improve your
active serial programming speed.

Hope this helps.

Vaughn
Altera
[v b e t z (at) altera.com]

Article: 128446
Subject: buying fpga kits in denmark
From: "deepakvr@gmail.com" <deepakvr@gmail.com>
Date: Sat, 26 Jan 2008 06:29:54 -0800 (PST)
Links: << >>  << T >>  << A >>
Hi ,

Can anybody give me some information on buying fpga kits in
denmark? ..iam interested in the altera cyclone 3 starter kit! .,guess
its possible to order from Altera directly , but i might have to deal
with the import procedure myself ...I tried farnell elektronics
denmark (http://dk.farnell.com/jsp/home/homepage.jsp) ..but afaik they
deal only with companies and not individuals

any information will be helpful

Thank You,

Deepak

Article: 128447
Subject: Re: Craignell FPGA DIP Module
From: "Tim (one of many)" <tim@nooospam.roockyloogic.com>
Date: Sat, 26 Jan 2008 15:15:02 +0000
Links: << >>  << T >>  << A >>
Jonathan Bromley wrote:
> On Fri, 25 Jan 2008 09:12:45 -0800 (PST), 
> Gabor <gabor@alacron.com> wrote:
> 
>> When is 36 pins not 36 pins ?
> 
> When it's a typo for 40, I think.  C'mon, give the
> guy a break - we all make tripyng mshtks.

I was sent this (no references for the alleged Cantab research):

Olny srmat poelpe can raed this. I cdnuolt blveiee that I cluod aulaclty 
  uesdnatnrd what I was rdanieg. The phaonmneal pweor of the hmuan mnid, 
aoccdrnig  to a rscheearch at Cmabrigde Uinervtisy, it deosn't mttaer in 
what oredr the ltteers in a word are, the olny iprmoatnt tihng is that 
the first and last ltteer be in the rghit pclae. The rset can be a taotl 
mses and you can still raed it wouthit a porbelm.   Tihs is bcuseae the 
huamn mnid deos not raed ervey lteter by istlef, but the word as a 
wlohe. Amzanig huh?! Yaeh and I awlyas tghuhot slpeling was ipmorantt!

Article: 128448
Subject: Re: EDK 9.2i install issues in Linux
From: jaymode@gmail.com
Date: Sat, 26 Jan 2008 08:46:56 -0800 (PST)
Links: << >>  << T >>  << A >>
Thank you both. It turns out that the way my school changed the DVDs
caused some sort of issue. When using the actual EDK dvd the install
went fine. Now I am running into a little bit of a different problem
dealing with the cable connection in EDK. The cable connects and
starts talking to the board but terminates very quickly. This is the
output that I am getting:


XMD%
Processor(s) in System ::

Microblaze(1) : microblaze_0
Address Map for Processor microblaze_0
  (0000000000-0x00003fff) dlmb_cntlr    dlmb
  (0000000000-0x00003fff) ilmb_cntlr    ilmb
  (0x81000000-0x8100ffff) Ethernet_MAC  mb_plb
  (0x81400000-0x8140ffff) Rotarybutton  mb_plb
  (0x81420000-0x8142ffff) LEDs_8Bit     mb_plb
  (0x81440000-0x8144ffff) LCD   mb_plb
  (0x81460000-0x8146ffff) DIP_Switches_4Bit     mb_plb
  (0x81480000-0x8148ffff) Buttons_4Bit  mb_plb
  (0x81600000-0x8160ffff) xps_iic_J2    mb_plb
  (0x81620000-0x8162ffff) xps_iic_J1    mb_plb
  (0x81800000-0x8180ffff) xps_intc_0    mb_plb
  (0x83c00000-0x83c0ffff) xps_timer_2   mb_plb
  (0x83c20000-0x83c2ffff) xps_timer_1   mb_plb
  (0x84000000-0x8400ffff) RS232_DTE     mb_plb
  (0x84020000-0x8402ffff) RS232_DCE     mb_plb
  (0x84400000-0x8440ffff) debug_module  mb_plb
  (0x89000000-0x89ffffff) FLASH mb_plb
  (0x8c000000-0x8fffffff) DDR_SDRAM     mb_plb

Info:Reusing A0038001 key.
Info:Reusing 24038001 key.
Info:Connecting to cable (Usb Port - USB21).
Info:Checking cable driver.
Info:Overriding Xilinx file <> with local file </opt/EDK/bin/lin/>
Info:File version of /usr/share/xusbdfwu.hex = 1030.
Info: WinDriver v9.10 Jungo (c) 1997 - 2007 Build Date: Dec 12 2007
X86 32bit 09
:05:45.
Info:Cable connection failed.
Error:ERROR:MDT -

-- Error in XMD Initialization. Type "exit" to Quit XMD

I followed the instructions on the Gentoo wiki and used the 9.10
version of Windriver because of the kernel in opensuse. Will using the
driver from here work:
http://www.rmdir.de/~michael/xilinx/

Will it also allow me to use the board from Windows also?

Thanks again.
Jay

Article: 128449
Subject: Re: Random Number Generation in VHDL
From: FPGA <FPGA.unknown@gmail.com>
Date: Sat, 26 Jan 2008 10:42:49 -0800 (PST)
Links: << >>  << T >>  << A >>
On Jan 25, 4:51=A0pm, glen herrmannsfeldt <g...@ugcs.caltech.edu> wrote:
> Jonathan Bromley wrote:
> > On Fri, 25 Jan 2008 10:40:11 -0800,
> > Dwayne Dilbeck wrote:
> >>I usually use a maximal LFSR to obtain psuedo random numbers.
> >>The following link will give you some good information.
> >>www.xilinx.com/ipcenter/catalog/logicore/docs/lfsr.pdf
> >>I like Appendix B wich lists the tap points up to 168bits for a maximal
> >>length LFSR.
> >>The following would generate psudeo random 64 bit numbers starting with =
seed
> >>value 1.
> >>entity generator is
> >> port (
> >> =A0 =A0clk:in bit;
> >> =A0 =A0a:out bit_vector(63 downto 0));
> >>end;
> >>achitecture processflow of generator is
> >>begin
> >> =A0 CLKED:process
> >> =A0 =A0 =A0 =A0 =A0 =A0variable temp:bit_vector(63 downto 0) :=3D
> >>X"0000_0000_0000_0001";
> >> =A0 begin
> >> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0temp :=3D temp(63 downto 0 ) =A0& (temp(=
63) xor temp(62) );
> >> =A0 =A0 =A0 =A0 =A0 =A0 =A0 a <=3D temp;
> >> =A0 =A0 =A0 =A0 =A0 =A0 =A0 wait until (clk =3D '0');
> >> =A0 =A0end process
> >>end
> > aaargh.... note that this gives you one pseudo-random BIT per
> > clock cycle.... but the 64-bit words are painfully strongly
> > correlated from one cycle to the next. =A0You need to clock
> > your N-bit LFSR for at least N cycles before pulling the
> > next N-bit value from it.
>
> It doesn't look like a very good one, either. =A0You want
> one based on a primitive polynomial
>
> http://en.wikipedia.org/wiki/Primitive_polynomial
>
> which is sort of related to a prime number. =A0There is a good
> explanation in "Numerical Recipes" including some primitive
> polynomials. =A0The CRC32 polynomial has been well studied,
> and should have pretty good properties. =A0For 64 bits you could
> use multiple LFSR of different lengths and generate a new value
> in much less than 64 cycles.
>
> -- glen
>
>
>
> > Even then, the random numbers aren't brilliantly random
> > (or at least that's what I am led to understand - I don't
> > have a particularly good grip on the somewhat scary math)
> > but LFSRs are indeed a good source of quasi-random stuff
> > for non-critical applications. =A0Just remember to clock
> > them enough times!- Hide quoted text -
>
> - Show quoted text -- Hide quoted text -
>
> - Show quoted text -

I am very thankful to everyone for their feedback. I am a beginner in
this field and this forum has helped me a long way. I am thankful to
everyone who put in their valuable time to advise others. I appreciate
it.



Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarAprMayJunJulAugSepOctNovDec2017
2018JanFebMarAprMayJunJulAugSepOctNovDec2018
2019JanFebMarAprMayJunJulAugSepOctNovDec2019
2020JanFebMarAprMay2020

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search