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>...FPGA...two different programs because...two different modes >...need...a device that contains two programs... and depending >...on the user will program one... >One thing that came to...mind is...a PIC that would emulate a >PROM and...retrieve the...program from...FLASH memory. If the functions of the two programs are so similar, is it possible to contain them in a single configuration? For configuration with an external microcontroller, it's probably best to use "passive configuration" mode. How fast do you need the configuration to load? It can take a long time when done with an external micro!! For example, I use hand-optimised PIC assembler to load a compressed configuration to the smallest Altera Cyclone II. The PIC is clocked at 32MHz and controls only the clock signals. (The data is connected directly from the flash memory (an SD card) to the FPGA configuration data input). Even in this "Formula 1" arrangement (with loop unrolling and with the SD card and FPGA configuration clock signals on the same PIC port to save one instruction of the loop), it takes about 0.3s to load the FPGA. MikeArticle: 129226
On Feb 19, 5:25=A0am, "Nial Stewart" <nial*REMOVE_TH...@nialstewartdevelopments.co.uk> wrote: > > I absolutely agree that it's a smart move to keep the number > > of processes reasonably small (and, of course, Mike Treseler > > would be even more emphatic about that). =A0But to suggest that > > there should be only one per clock is truly nonsensical. > > What rationale is given for that rule? > > The explanation was that it was to cut down the mistakes made > with clock enables! > I guess a few simple follow up questions back to people at that company (if that's possible) then would be: 1. What types of mistakes get made with 'clock enables'? 2. Are they seeing fewer of these mistakes of those types since instituting the "Only one process per clock is allowed per entity" rule? But I guess it could go on endlessly trying to fathom the rationale without direct access to the rule maker and the reasoning that went into it. Kevin JenningsArticle: 129227
On Feb 19, 9:25 am, MikeShepherd...@btinternet.com wrote: > >...FPGA...two different programs because...two different modes > >...need...a device that contains two programs... and depending > >...on the user will program one... > >One thing that came to...mind is...a PIC that would emulate a > >PROM and...retrieve the...program from...FLASH memory. > > If the functions of the two programs are so similar, is it possible to > contain them in a single configuration? > > For configuration with an external microcontroller, it's probably best > to use "passive configuration" mode. > > How fast do you need the configuration to load? It can take a long > time when done with an external micro!! > > For example, I use hand-optimised PIC assembler to load a compressed > configuration to the smallest Altera Cyclone II. The PIC is clocked > at 32MHz and controls only the clock signals. (The data is connected > directly from the flash memory (an SD card) to the FPGA configuration > data input). > > Even in this "Formula 1" arrangement (with loop unrolling and with the > SD card and FPGA configuration clock signals on the same PIC port to > save one instruction of the loop), it takes about 0.3s to load the > FPGA. > > Mike Hi again , the function is similar but the design is different. I mean , both are digital filters but they use different architectures. 1- Where can I read about Dynamic Partial ? I am not using a very large FPGA ( xc3s500e) so I dont know if a Microblaze processor would fit in. 2- I will study a bit more about Slave serial mode but I dont understand how this can help me choose which program I will load on the FPGA. 3- Programming time is not an issue since it will be programmed once or twice a month in the worst case. 4- Has anyone evaluate SystemBIST , is it expensive ? not really useful? unconvenient? Thanks again , and sorry for my bad english.Article: 129228
On Feb 19, 5:15=A0am, "Nial Stewart" <nial*REMOVE_TH...@nialstewartdevelopments.co.uk> wrote: > I'm going to talk to a potential new client about using FPGAs to > accelerate part of their system. > > As part of what needs done there could be a significant amount of > division(s) done. > > Previously I've been able to multiply by a reciprocal then scale to > make division a double clock operation so this can be easily pipelined. > This is only achieveable if the divisor is pre-known and the > reciprocal can be pre-calculated. > > With what's coming up I'm not sure that I can do this, I know that > > Are there any clever techniques for streamlining divisions that > make them deterministic and don't use a big wodge of logic? > > Thanks for any pointers, > Check into the lpm_divide function that is part of the lpm package. It's synchronous and accepts new inputs on every clock. It is a standard, although people seem to rail against lpm as being mainly 'Altera'. Kevin JenningsArticle: 129229
>...I will study...Slave serial mode but I dont understand >how this can help me choose which program I will load I understand from http://www.xilinx.com/support/documentation/application_notes/xapp502.pdf that Xilinx "slave serial" mode is equivalent to Altera "passive serial mode". In this mode, the microcontroller loads the FPGA, so you have complete control in the microcontroller program of what data is sent to the FPGA as its configuration. MikeArticle: 129230
Nial Stewart wrote:
> Are there any clever techniques for streamlining divisions that
> make them deterministic and don't use a big wodge of logic?
That's a trade-off with speed.
A subtract loop is simple and deterministic but slow.
A binary search multiply-subtract is possible with dsp blocks.
-- Mike Treseler
Article: 129231> Do you need high throughput and short latency? I don't know yet :-) > If latency isn't that big > issue, I have successfully used the serial devider from opencores.Otherwise > there are more divider projects at opencores. I'll have a look at Opencores, I hadn't thought of trying there. Thanks, Nial.Article: 129232
> Check into the lpm_divide function that is part of the lpm package. > It's synchronous and accepts new inputs on every clock. It is a > standard, although people seem to rail against lpm as being mainly > 'Altera'. I'll have a look at this but my impression with this is that it uses a _lot_ of logic? NialArticle: 129233
Hi, I Love Linux, but currently i have to boot in XP because of xilinx toolset (ISE, EDK, sysgen Matlab, chipscope etc) May any body tell me , Any Linux Distro (other then commercial , like redhat, i cann't buy) which will work perfectly with all components(ISE, EDK, sysgen Matlab, chipscope etc). I am using Fedora 7 and face problem with cable drivers and many such things, Is any body working perfectly with this any Linux Distro, ???Article: 129234
On Feb 19, 9:51 am, MikeShepherd...@btinternet.com wrote: > >...I will study...Slave serial mode but I dont understand > >how this can help me choose which program I will load > > I understand fromhttp://www.xilinx.com/support/documentation/application_notes/xapp502... > that Xilinx "slave serial" mode is equivalent to Altera "passive > serial mode". > > In this mode, the microcontroller loads the FPGA, so you have complete > control in the microcontroller program of what data is sent to the > FPGA as its configuration. > > Mike I think I will focus on Multi-Boot PROM , any experience with that?Article: 129235
Check SystemACE. It will configure a set of FPGAs from a compact flash card. You can select one of eight configurations stored on the card either by external signals or by registers that can be accessed by FPGA logic. The CF can also be writte by the FPGA to allow in system updates. Regards, Kolja Sulimma On 19 Feb., 12:26, Alfreeeeed <Alfredo.Tad...@gmail.com> wrote: > Greetings , I am trying to implement a solution for an FPGA that needs > to be configured with two different programs because the whole system > will operate in two different modes. Basically what I need is a device > that contains two programs and depending on the user will program one > of each. The pinout will be the same because it is a digital filter. > One thing that came to my mind is putting a PIC that would emulate a > PROM and would retrieve the corresponding program from a FLASH > memory. > > Do you know how can I optimize this? > Is there any commercial solution around? > > Thanks in advance , and sorry for my bad english. > > AlfredoArticle: 129236
On Feb 19, 8:25 am, Narendra Sisodiya <narendra.sisod...@gmail.com> wrote: > Hi, > I Love Linux, but currently i have to boot in XP because of xilinx > toolset (ISE, EDK, sysgen Matlab, chipscope etc) > May any body tell me , Any Linux Distro (other then commercial , like > redhat, i cann't buy) which will work perfectly with all > components(ISE, EDK, sysgen Matlab, chipscope etc). > I am using Fedora 7 and face problem with cable drivers and many such > things, > Is any body working perfectly with this any Linux Distro, ??? I believe Sysgen is Windows only. So, I don't think there is any way to satisfy your requirement. If this is incorrect, that would be fantastic news to me, as Sysgen is one of the few things still tying me to Windows.Article: 129237
>I think I will focus on Multi-Boot PROM , any experience with that? No.Article: 129238
Alfreeeeed wrote: > Greetings , I am trying to implement a solution for an FPGA that needs > to be configured with two different programs because the whole system > will operate in two different modes. Basically what I need is a device > that contains two programs and depending on the user will program one > of each. The pinout will be the same because it is a digital filter. > One thing that came to my mind is putting a PIC that would emulate a > PROM and would retrieve the corresponding program from a FLASH > memory. > > Do you know how can I optimize this? > Is there any commercial solution around? > > Thanks in advance , and sorry for my bad english. > > Alfredo The keyword to search for in the Spartan3E data sheet is "Multiboot" if you want to have the program in flash and let the FPGA take care of it rather than hooking up an external micro. Both approaches will get you what you want.Article: 129239
On Feb 19, 9:11 am, paragon.j...@gmail.com wrote: > On Feb 19, 8:25 am, Narendra Sisodiya <narendra.sisod...@gmail.com> > wrote: > > > Hi, > > I Love Linux, but currently i have to boot in XP because of xilinx > > toolset (ISE, EDK, sysgen Matlab, chipscope etc) > > May any body tell me , Any Linux Distro (other then commercial , like > > redhat, i cann't buy) which will work perfectly with all > > components(ISE, EDK, sysgen Matlab, chipscope etc). > > I am using Fedora 7 and face problem with cable drivers and many such > > things, > > Is any body working perfectly with this any Linux Distro, ??? I use OpenSUSE 10.3/10.2 at work and have used all of the Xilinx tools successfully under it. For my cable drivers, I use the open-source drivers available at:http://rmdir.de/~michael/xilinx/. I currently have a patch for the driver that allows for a parallel cable to be used by both ChipScope and XMD at the same time. I'm still working on the USB version. I'm also working on an ECP patch for the driver to get the parallel cable running at higher speeds. Four minutes is way too long to wait for an image to program. I have run into a couple of problems with some of the older tools like fpga editor, pace, and floorplanner. To run these, I had to run them using "env DISPLAY=:0 <executable>" otherwise they would complain that they couldn't find X server. Now, I would NOT recommend OpenSUSE. I personally love Ubuntu and have read posts in the Ubuntu forums about people using the same tools under that distro with no problems. I have to use OpenSUSE because of restrictions at work. Also, Xilinx has, on more than one occasion, told me to use Linux for the development because their tools 'work better' under Linux than windows. > I believe Sysgen is Windows only. So, I don't think there is any way > to satisfy your requirement. > > If this is incorrect, that would be fantastic news to me, as Sysgen is > one of the few things still tying me to Windows. I don't know about sysgen, since I don't use it. -- MikeArticle: 129240
Nial Stewart wrote:
> I'll have a look at this but my impression with this is that it
> uses a _lot_ of logic?
It makes a_whole_lotta_luts in one lump.
Requires a slow system clock or a multi-cycle constraint.
Quartus will infer lpm_divide from from int or signed /.
-- Mike Treseler
Article: 129241MikeShepherd564@btinternet.com wrote: > For example, I use hand-optimised PIC assembler to load a compressed > configuration to the smallest Altera Cyclone II. The PIC is clocked > at 32MHz and controls only the clock signals. (The data is connected > directly from the flash memory (an SD card) to the FPGA configuration > data input). > > Even in this "Formula 1" arrangement (with loop unrolling and with the > SD card and FPGA configuration clock signals on the same PIC port to > save one instruction of the loop), it takes about 0.3s to load the > FPGA. With Xilinx FPGAs, the fastest solution with a micro is usually one of the SPI modes. And a fast micro, of course. A little PAL or another FPGA will be at least as fast. Maybe this is also true for Altera.Article: 129242
Frank Buss wrote:
> I've implemented a flash programmer for the EPCS1 serial flash, attached to
> a Cyclone, using the Serial Flash Loader entity. Programming and reading
> the flash works, but how do I create the data for programming it? I've
> programmed it with a Byte Blaster and a JIC file from within Quartus and
> comparing the content which was flashed with a RBF file, it looks like
> every byte is just mirrored (from LSB to MSB instead of MSB to LSB) and
> some bits at the beginning are different. Is it safe to use this RBF file
> for flashing the flash?
Not completely as the RBF format is proprietary and sometimes
those 'bits at the beginning' move around with software
and device versions. It can be made to work, but you must
keep an eye on it.
> Is there a documentation of the RBF file format?
Not in the public domain.
Don't know why.
-- Mike Treseler
Article: 129243>With Xilinx FPGAs, the fastest solution with a micro is usually one of >the SPI modes. And a fast micro, of course. A little PAL or another FPGA >will be at least as fast. Maybe this is also true for Altera. Let's race your SPI solution against my hand-optimised assembler!! :) I have to warn you that my method transfers at a peak rate of one configuration bit every 375ns (three instruction cycles) and an average of about one bit every 420ns over each 512-byte block from the flash device. (There's a delay in requesting each block which would apply to any method). If you use SPI, you'll first need to read the flash data into your processor. With byte-wide flash, you have an advantage there and may overtake me (although you'll use a lot more processor lines). With serial flash, it will take longer to read the data to your processor (unless you use another SPI controller for that) than it takes me to send it on the direct connection between my flash memory and the FPGA by just toggling the clocks. With parallel flash memory, you could still use direct connection. This would waste all but one bit in each flash word, but that may not be significant if the flash memory is much larger than the FPGA configuration. MikeArticle: 129244
On Feb 19, 7:33 pm, morphiend <morphi...@gmail.com> wrote: > On Feb 19, 9:11 am, paragon.j...@gmail.com wrote: > > > On Feb 19, 8:25 am, Narendra Sisodiya <narendra.sisod...@gmail.com> > > wrote: > > > > Hi, > > > I Love Linux, but currently i have to boot in XP because of xilinx > > > toolset (ISE, EDK, sysgen Matlab, chipscope etc) > > > May any body tell me , Any Linux Distro (other then commercial , like > > > redhat, i cann't buy) which will work perfectly with all > > > components(ISE, EDK, sysgen Matlab, chipscope etc). > > > I am using Fedora 7 and face problem with cable drivers and many such > > > things, > > > Is any body working perfectly with this any Linux Distro, ??? > > I use OpenSUSE 10.3/10.2 at work and have used all of the Xilinx tools > successfully under it. For my cable drivers, I use the open-source > drivers available at:http://rmdir.de/~michael/xilinx/. I currently > have a patch for the driver that allows for a parallel cable to be > used by both ChipScope and XMD at the same time. I'm still working on > the USB version. I'm also working on an ECP patch for the driver to > get the parallel cable running at higher speeds. Four minutes is way > too long to wait for an image to program. > > I have run into a couple of problems with some of the older tools like > fpga editor, pace, and floorplanner. To run these, I had to run them > using "env DISPLAY=:0 <executable>" otherwise they would complain that > they couldn't find X server. > > Now, I would NOT recommend OpenSUSE. I personally love Ubuntu and have > read posts in the Ubuntu forums about people using the same tools > under that distro with no problems. I have to use OpenSUSE because of > restrictions at work. > > Also, Xilinx has, on more than one occasion, told me to use Linux for > the development because their tools 'work better' under Linux than > windows. > > > I believe Sysgen is Windows only. So, I don't think there is any way > > to satisfy your requirement. > > > If this is incorrect, that would be fantastic news to me, as Sysgen is > > one of the few things still tying me to Windows. > > I don't know about sysgen, since I don't use it. > > -- Mike Thanks a lot Mike, If, Ubuntu works good for Xilinx, should i go with Debian , otherwise , i can go with SUSE also....Article: 129245
>Frank Buss wrote: >> I've implemented a flash programmer for the EPCS1 serial flash, attached to >> a Cyclone, using the Serial Flash Loader entity. Programming and reading >> the flash works, but how do I create the data for programming it? I've >> programmed it with a Byte Blaster and a JIC file from within Quartus and >> comparing the content which was flashed with a RBF file, it looks like >> every byte is just mirrored (from LSB to MSB instead of MSB to LSB) and >> some bits at the beginning are different. Is it safe to use this RBF file >> for flashing the flash? > >Not completely as the RBF format is proprietary and sometimes >those 'bits at the beginning' move around with software >and device versions. It can be made to work, but you must >keep an eye on it. > >> Is there a documentation of the RBF file format? > >Not in the public domain. >Don't know why. > > -- Mike Treseler The RBF file is the raw data which you need to send to the device. All you need to know about its format is that you send it least significant bit first. This is the opposite way to the usual operation of SPI, so, if you're using SPI to transmit to the FPGA, you need first to reverse the bits of each byte. (You may find it more convenient to do this on your PC). MikeArticle: 129246
On Feb 19, 8:05=A0am, "Nial Stewart" <nial*REMOVE_TH...@nialstewartdevelopments.co.uk> wrote: > > Check into the lpm_divide function that is part of the lpm package. > > It's synchronous and accepts new inputs on every clock. =A0It is a > > standard, although people seem to rail against lpm as being mainly > > 'Altera'. > > I'll have a look at this but my impression with this is that it > uses a _lot_ of logic? > > Nial That of course depends on how much you think is *a lot*. It does let you tradeoff latency for performance though and depending on how you set that parameter it uses different amounts of logic...if I recall correctly, 0 latency (i.e. a combinatorial implementation of division) results in the largest logic usage, a latency equal to the width of the numerator (or denominator, maybe? fuzzy brain neuron currently being accessed) resulted in a good tradeoff in my application where I had three dividers but needed somewhat high performance (75 MHz in a Stratix I). If you need to be able to process full divisions on a system clock cycle, it will do the trick. If your system clock can run much faster so you can take several clocks to do the divide a divider that works on single bits at a time might be more appropriate. Kevin JenningsArticle: 129247
On Feb 19, 9:43=A0am, Mike Treseler <mike_trese...@comcast.net> wrote: > Nial Stewart wrote: > > I'll have a look at this but my impression with this is that it > > uses a _lot_ of logic? > > It makes a_whole_lotta_luts in one lump. > Requires a slow system clock or a multi-cycle constraint. I ran it at 75 MHz on a Stratix I without any multi-cycle constraints. You want to use the pipelining parameter to lpm_divide to tell it how many pipeline stages it can use. That affects how it implements the logic and allows for tradeoffs between the size of the lump of logic, the latency and the clock cycle but does not require specifying of any multi-cycle timing constraints. In any case, it shouldn't require any dramatic system clock sloooowing. > Quartus will infer lpm_divide from from int or signed /. > Doing so though will result in lpm_divide being parameterized with 0 latency which will result in the largest logic lump and the slowest clock cycle performance. Depending on the application it might be better to instantiate the lpm_divide and not have it inferred from "/". Kevin JenningsArticle: 129248
On Feb 19, 8:02=A0am, Mike Treseler <mike_trese...@comcast.net> wrote: > Nial Stewart wrote: > A binary search multiply-subtract is possible with dsp blocks. > That's one that I've always wanted to try just to see how well it does, but haven't had the need to do so of late. One would expect it to get high throughput, low logic usage and probably be the best in today's world of nearly free DSP block multipliers in FPGAs. Any benchmark data? Kevin JenningsArticle: 129249
Jon, OK, I was WRONG. I am not often WRONG, but, I can be WRONG, and I have been WRONG in the past. NC is no connect. We don't use those pins, and they are not connected internally in V4, and V5. Sorry for any confusion. Austin
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