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On Aug 25, 5:29 pm, Jon Elson <el...@wustl.edu> wrote: > John_H wrote: > > You can feed a 500 MHz clock to a Spartan3 style device, use a divide- > > by-2 in the DCM, and clock the output I/O blocks with the 250MHz clock > > in DDR mode. You just need to handle the logic to deal with odd/even > > starts and stops. > > We don't need to distribute a 500 MHz clock, 250 or even 125 with LVDS > would be fine. > > > I don't think you'll have power problems running only 32 channels of > > 13-bit counters but a power analysis will give you an idea of the > > actual need (XPOWER tool?). > > Spartan 3, huh? I'm just a little more comfortable with that, as I just > did a migration to Spartan IIE (always on the trailing edge!) I can > even get those in TQFP's, which I can mount and rework myself. I'm > avoiding BGAs. > > I will have to look into the implications of using Spartan 3E on this. > If the counters are running at 250 MHz, then the granularity of timing > timing settings is 4 ns, which may well be tolerable. If they need > finer resolution, then there are ways to fudge that with the DDR. > So, you think a 13-bit counter feeding a 13-bit identity comparator will > work at 250 MHz? (I've never pushed the speeds on these FPGAs at all, > all of by previous projects were very relaxed by comparison, like 40 MHz.) Remember that you can pipeline the comparator. Each LUT can compare two bits and four (or 8) of those can be combined with another row of LUTs. Heck I haven't looked hard at the Xilinx parts in awhile, but I recall that you can use some of the "extra" logic in a CLB to compare 4 bits in two LUTs with one output, then AND 8 of those in a second level of LUTs. Each level of logic can work with a FF on the output, you just have to account for that in your compare register setting. I expect this will run at 250 MHz, but I can't say for sure. RickArticle: 134676
On Mon, 25 Aug 2008 14:08:20 -0500, Jon Elson <elson@wustl.edu> wrote: >Hello, all, > >I just got a potential project thrown in my lap. I designed an >all-analog delay generator module, with 32 delays that trigger 32 pulse >widths. So, basically, 64 wide-range programmable one-shots on one >board. LVDS in, ECL out (for legacy gear). These one-shots can be >programmed from about 10 ns to 12 us in several ranges. > >Somebody asked, "Gee, couldn't you do that with an FPGA?" Well, a few >years ago, maybe not. So, could anyone suggest some fast FPGAs that can >handle clocks in the 500+ MHz range? I normally work with Xilinx, but >could look at some others, too. I suspect RAM-based FPGAs would be >desirable over one-time programmed. It would not be a problem to use >several smaller FPGAs to keep them from overheating at the high clock >rate. We have forced-air cooling in the equipment, but you lose that >when modules are put on extenders. > >The basic circuit would look like a 13-bit counter with a 13-bit preset >register, and a zero comparator. (It could also be a 13-bit counter >that starts at zero, and a preset register that sets the terminal >count.) So, 432 FFs would do 8 channels of this dual one-shot logic. >Half of the FFs would be clocked at the 500+ MHz rate, the other half >would be essentially static. > >Thanks in advance for any suggestions! > >Jon You can do coarse delays by counting at some modest clock frequency, and get fine delays from a fast-clocked shift register or a simple external analog vernier. The analog thing can take you down to picosecond resolution. You can also double resolution by using both clock edges. But can you tolerate the 1-clock p-p jitter that you'll get from asynchronous trigger inputs slamming into a continuous clock? JohnArticle: 134677
Hi all, I am presently doing a project on "Validation and Verification" of Core control modules. And now i am in writing Test cases for the block modules. Can anyone shares their knowledge on What is Robustness testing what kind of importance is there in writing test cases for the signals and how to judge them whether it performs Robustness test. Hope to look some exposure on it..so tht i can elaborate some of queries? Thanks, Design Engg-FPGA, Moog, IncArticle: 134678
Jon Elson wrote: > Hello, all, > > I just got a potential project thrown in my lap. I designed an > all-analog delay generator module, with 32 delays that trigger 32 pulse > widths. So, basically, 64 wide-range programmable one-shots on one > board. LVDS in, ECL out (for legacy gear). These one-shots can be > programmed from about 10 ns to 12 us in several ranges. > > Somebody asked, "Gee, couldn't you do that with an FPGA?" Well, a few > years ago, maybe not. So, could anyone suggest some fast FPGAs that can > handle clocks in the 500+ MHz range? I normally work with Xilinx, but > could look at some others, too. I suspect RAM-based FPGAs would be > desirable over one-time programmed. It would not be a problem to use > several smaller FPGAs to keep them from overheating at the high clock > rate. We have forced-air cooling in the equipment, but you lose that > when modules are put on extenders. > > The basic circuit would look like a 13-bit counter with a 13-bit preset > register, and a zero comparator. (It could also be a 13-bit counter > that starts at zero, and a preset register that sets the terminal > count.) So, 432 FFs would do 8 channels of this dual one-shot logic. > Half of the FFs would be clocked at the 500+ MHz rate, the other half > would be essentially static. > > Thanks in advance for any suggestions! > > Jon Hej Jon How about AFPGA instead of FPGA?: Achronix-ULTRA: http://www.achronix.com/products.html Achronix preps 2-GHz Asynchronous FPGA for sampling in 2007: http://www.pldesignline.com/news/186700955 Asynchronous VLSI and Architecture, Cornell University: Asynchronous Field-Programmable Gate Arrays (AFPGAs): http://vlsi.cornell.edu/fpga.php Quote: "...integrated pipelining support..." Programmable Asynchronous Pipeline Arrays (2003) John Teifel, Rajit Manohar: http://citeseer.ist.psu.edu/teifel03programmable.html GlennArticle: 134679
Good job...yeah, it's weird and bad that programs get tangled up with each other. I recently installed anti-virus software that told me it couldn't install unless I updated my cd/dvd burner software because there was a bug in that program that affects it...stupid...of course now that I have "updated" the burner software, it doesn't work anymore...Article: 134680
Hey folks , i need ur opinion about something : To implement an AES decryption (CBC mode ) algorithm in ASIC , what would be the best way to do it ? i mean among these architectures which one do you choose and why : * Basic iterative architecture * Partial loop unrolling * full loop unrolling * Partia outer-round pipelining * Full outerround pipelining * Inner-round pipelining * Partial mixed innerand outerroundpipelining * Full mixed inner- and outer-round pipelining * other ...Article: 134681
Has anyone any experience in using Xilinx floating licenses for IP
cores? I have tried to get a bought license to work for several weeks
now with no success! For interested readers I have pasted in some
commands and printouts below.
****** I work in a Linux environment ******
As You can see the lmutil lmstat command finds the rs_encoder_v6 license
on the server but not the xilcmgr tool which is used by coregen. Both
tools are included in the Xilinx installation.
******************************
When running the following command in a shell the license is found but
not from within coregen.
/neti/tools/xilinx/10.1i_sp1/ISE/bin/lin/lmutil lmstat -c 2200@conny -f
rs_encoder_v6
lmutil - Copyright (c) 1989-2006 Macrovision Europe Ltd. and/or
Macrovision Corporation. All Rights Reserved.
Flexible License Manager status on Tue 6/3/2008 13:59
License server status: 2200@conny
License file(s) on conny: /usr/local/flexlm/Xilinx.dir/license.dat:
conny: license server UP (MASTER) v8.4
Vendor daemon status (on conny):
xilinxd: UP v6.1
Feature usage info:
Users of rs_encoder_v6: (Total of 9999 licenses issued; Total of 0
licenses in use)
************************************************************
Below is the debug printouts from xlicmgr (which I expect is the tool
used by coregen). The command is executed on my local machine named
dave, the license server is running on a server named conny. lmhostid
for conny is "8085a19b" and this is th hostid the license is generated
for. lmhostid for dave is "00508dd90ba1". The "Current host ID:" in
the debug information is set to the hostid of the local machine (dave),
is this correct?
10:29 dave:synt > env XILINXD_LICENSE_FILE=2200@conny
/neti/tools/xilinx/10.1i_sp1/ISE/bin/lin/xlicmgr status -c rs_encoder_v6 -v
Release 10.1.01 - Xilinx License Manager (xlicmgr) K.34 (lin)
Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved.
DEBUG[license] - Initialising FLEXlm system...
DEBUG[license] - FLEXlm features will be searched for in the following
order:
DEBUG[license] - XILINXD_LICENSE_FILE environment variable: 2200@conny
DEBUG[license] - HOME environment variable:
/home/pateri/.Xilinx/Coregen/CoreLicenses
DEBUG[license] - XILINX environment variable:
/neti/tools/xilinx/10.1i_sp1/ISE/coregen/core_licenses
DEBUG[license] - Initialisation complete.
DEBUG[license] - Attempting to locate FLEXlm license for feature
<rs_encoder_v6>;
DEBUG[license] - Attempting to checkout <Source> license...
DEBUG[license] - Checkout failed.
DEBUG[license] - Attempting to checkout <Bought> license...
DEBUG[license] - Checkout failed.
DEBUG[license] - Attempting to checkout <Hardware_Evaluation> license...
DEBUG[license] - Checkout failed.
DEBUG[license] - Attempting to checkout <Design_Linking> license...
DEBUG[license] - Checkout failed.
DEBUG[license] - Feature <rs_encoder_v6>; could not be authenticated by
FLEXlm
engine.
DEBUG[license] - Attempting to locate XilLicense license for feature in
rs_encoder_v6.lic in the following directories:
DEBUG[license] - HOME environment variable:
/home/pateri/.Xilinx/Coregen/CoreLicenses
DEBUG[license] - XILINX environment variable:
/neti/tools/xilinx/10.1i_sp1/ISE/coregen/core_licenses
DEBUG[license] - Searching for file
</home/pateri/.Xilinx/Coregen/CoreLicenses/rs_encoder_v6.lic>...
DEBUG[license] - File not found.
DEBUG[license] - Searching for file
</neti/tools/xilinx/10.1i_sp1/ISE/coregen/core_licenses/rs_encoder_v6.lic>...
DEBUG[license] - File not found.
DEBUG[license] - Feature enabled with FLEXlm license.
DEBUG[license] - HOME environment variable:
/home/pateri/.Xilinx/Coregen/CoreLicenses
DEBUG[license] - XILINX environment variable:
/neti/tools/xilinx/10.1i_sp1/ISE/coregen/core_licenses
Feature: rs_encoder_v6
Status: Invalid - FLEXlm Error: No such feature exists. (-5,21)
Expiration date: Unknown
Current host ID: 00508dd90ba1
License type: FLEXlm
Built in search paths:
/home/pateri/.Xilinx/Coregen/CoreLicenses:/neti/tools/xilinx/10.1i_sp1/ISE/coregen/core_licenses
XILINXD_LICENSE_FILE: 2200@conny
************************************************
With license generated for my local machine it looks like this, i.e. it
works.
9:42 dave:synt > env XILINXD_LICENSE_FILE=2200@conny
/neti/tools/xilinx/10.1i_sp1/ISE/bin/lin/xlicmgr status -c rs_encoder_v6 -v
Release 10.1.01 - Xilinx License Manager (xlicmgr) K.34 (lin)
Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved.
DEBUG[license] - Initialising FLEXlm system...
DEBUG[license] - FLEXlm features will be searched for in the following
order:
DEBUG[license] - XILINXD_LICENSE_FILE environment variable: 2200@conny
DEBUG[license] - XILINXD_LICENSE_FILE value in $HOME/.flexlmrc:
/home/pateri/.Xilinx/Coregen/CoreLicenses
DEBUG[license] - HOME environment variable:
/home/pateri/.Xilinx/Coregen/CoreLicenses
DEBUG[license] - XILINX environment variable:
/neti/tools/xilinx/10.1i_sp1/ISE/coregen/core_licenses
DEBUG[license] - Initialisation complete.
DEBUG[license] - Attempting to locate FLEXlm license for feature
<rs_encoder_v6>;
DEBUG[license] - Attempting to checkout <Source> license...
DEBUG[license] - Checkout failed.
DEBUG[license] - Attempting to checkout <Bought> license...
DEBUG[license] - Checkout of feature <rs_encoder_v6>; succeeded.
DEBUG[license] - Attempting to locate XilLicense license for feature in
rs_encoder_v6.lic in the following directories:
DEBUG[license] - HOME environment variable:
/home/pateri/.Xilinx/Coregen/CoreLicenses
DEBUG[license] - XILINX environment variable:
/neti/tools/xilinx/10.1i_sp1/ISE/coregen/core_licenses
DEBUG[license] - Searching for file
</home/pateri/.Xilinx/Coregen/CoreLicenses/rs_encoder_v6.lic>...
DEBUG[license] - Found license file.
DEBUG[license] - License type: bought
DEBUG[license] - Found invalid XilLicense license: The license permits
use only
on hosts with one of the following MAC addresses <00-50-8d-d9-0b-a1>.
DEBUG[license] - Searching for file
</neti/tools/xilinx/10.1i_sp1/ISE/coregen/core_licenses/rs_encoder_v6.lic>...
DEBUG[license] - File not found.
DEBUG[license] - Feature enabled with FLEXlm license.
DEBUG[license] - HOME environment variable:
/home/pateri/.Xilinx/Coregen/CoreLicenses
DEBUG[license] - XILINX environment variable:
/neti/tools/xilinx/10.1i_sp1/ISE/coregen/core_licenses
Feature: rs_encoder_v6
Status: Full - No Source
Expiration date: Does not expire
Current host ID: 00508dd90ba1
License type: FLEXlm
Built in search paths:
/home/pateri/.Xilinx/Coregen/CoreLicenses:/neti/tools/xilinx/10.1i_sp1/ISE/coregen/core_licenses
XILINXD_LICENSE_FILE: 2200@conny
FLEXlm license cache locations: /home/pateri/.Xilinx/Coregen/CoreLicenses
Article: 134682Jon Elson <elson@wustl.edu> wrote in news:48B30324.2000603@wustl.edu: > Hello, all, > > I just got a potential project thrown in my lap. I designed an > all-analog delay generator module, with 32 delays that trigger 32 > pulse widths. So, basically, 64 wide-range programmable one-shots on > one board. LVDS in, ECL out (for legacy gear). These one-shots can > be programmed from about 10 ns to 12 us in several ranges. > > Somebody asked, "Gee, couldn't you do that with an FPGA?" Well, a few > years ago, maybe not. So, could anyone suggest some fast FPGAs that > can handle clocks in the 500+ MHz range? I normally work with Xilinx, > but could look at some others, too. I suspect RAM-based FPGAs would > be desirable over one-time programmed. It would not be a problem to > use several smaller FPGAs to keep them from overheating at the high > clock rate. We have forced-air cooling in the equipment, but you lose > that when modules are put on extenders. > > The basic circuit would look like a 13-bit counter with a 13-bit > preset register, and a zero comparator. (It could also be a 13-bit > counter that starts at zero, and a preset register that sets the > terminal count.) So, 432 FFs would do 8 channels of this dual > one-shot logic. Half of the FFs would be clocked at the 500+ MHz rate, > the other half would be essentially static. > > Thanks in advance for any suggestions! You might also like to consider using a part with a high speed serdes, e.g. Stratix-nGX, or Virtex-nFX, etc. This allows you to sample at some GHz, with a convenient, sensitive differential input. You can synthesise any delay you want in multiples of the sampling period, by rotating the internal parallel bus. The SERDES output will probably be CML, but that is pretty easy to interface to ECL. AFAICT, this will give you close to an order of magnitude better performance than any other FPGA based approach. Regards, AllanArticle: 134683
> Hey folks , i need ur opinion about something =A0: > To implement an AES decryption (CBC mode ) algorithm in ASIC , what > would be the best way to do it ? i mean among these architectures > which one do you choose and why : > > * Basic iterative architecture > * Partial loop =A0unrolling > * full loop unrolling > * Partia outer-round pipelining > * Full outerround pipelining > * Inner-round pipelining > * Partial mixed innerand outerroundpipelining > * Full mixed inner- and outer-round pipelining > * other ... What process are you using and what are your power / area / bandwidth requirements. JonArticle: 134684
On 26 ao=FBt, 11:33, Jon Beniston <j...@beniston.com> wrote: > > Hey folks , i need ur opinion about something =A0: > > To implement an AES decryption (CBC mode ) algorithm in ASIC , what > > would be the best way to do it ? i mean among these architectures > > which one do you choose and why : > > > * Basic iterative architecture > > * Partial loop =A0unrolling > > * full loop unrolling > > * Partia outer-round pipelining > > * Full outerround pipelining > > * Inner-round pipelining > > * Partial mixed innerand outerroundpipelining > > * Full mixed inner- and outer-round pipelining > > * other ... > > What process are you using and what are your power / area / bandwidth > requirements. > > Jon Thank you jon , In fact i need to know the architecture of such algorithm ( AES 256 decryption CBC mode) inside an ASIC that i don't know anything about it (area ,bandwith ...). my question is how many possibilities to implement this algorithm ? could we fix all possibilities ?Article: 134685
> Thank you jon , > =A0In fact i need to know the architecture of such algorithm ( AES 256 > decryption CBC mode) inside an ASIC that i don't know anything about > it (area ,bandwith ...). > my question is how many possibilities to implement this algorithm ? You can implement AES in many different ways. Which is right for you will depend upon what your requirements are. JonArticle: 134686
On Aug 26, 3:51 am, swissiyous...@gmail.com wrote: > Hey folks , i need ur opinion about something : > To implement an AES decryption (CBC mode ) algorithm in ASIC , what > would be the best way to do it ? i mean among these architectures > which one do you choose and why : > > * Basic iterative architecture > * Partial loop unrolling > * full loop unrolling > * Partia outer-round pipelining > * Full outerround pipelining > * Inner-round pipelining > * Partial mixed innerand outerroundpipelining > * Full mixed inner- and outer-round pipelining > * other ... Keep in that you'll only need to do the roundkey expansion once for each chain of CBC operations, so if you can compute that and store it in a register file of some sort. If you already have existing AES encryption IP, be sure to look at 5.3.5 of FIPS-197. You may be able to implement the decryption operation by simply changing the internal blocks to their inverse functions.Article: 134687
swissiyoussef@gmail.com wrote: > Hey folks , i need ur opinion about something : > To implement an AES decryption (CBC mode ) algorithm in ASIC , what > would be the best way to do it ? i mean among these architectures > which one do you choose and why : > > * Basic iterative architecture > * Partial loop unrolling > * full loop unrolling > * Partia outer-round pipelining > * Full outerround pipelining > * Inner-round pipelining > * Partial mixed innerand outerroundpipelining > * Full mixed inner- and outer-round pipelining > * other ... Is this multiple choice or an essay question? Will this be on the test?Article: 134688
Glenn, I have tried hard to get data on the Achronix parts, but have never succeeded in obtaining any useful/detailed information at all, nor have I ever received any kind of a response from the company when requesting information. Have you come across a source of substantive data on these mysterious devices? Robert J ___________________________________________________________________ Glenn Møller-Holst wrote: > Hej Jon > > How about AFPGA instead of FPGA?: > > Achronix-ULTRA: > http://www.achronix.com/products.html > > Achronix preps 2-GHz Asynchronous FPGA for sampling in 2007: > http://www.pldesignline.com/news/186700955 > > Asynchronous VLSI and Architecture, Cornell University: Asynchronous > Field-Programmable Gate Arrays (AFPGAs): > http://vlsi.cornell.edu/fpga.php > Quote: "...integrated pipelining support..." > > Programmable Asynchronous Pipeline Arrays (2003) John Teifel, Rajit > Manohar: > http://citeseer.ist.psu.edu/teifel03programmable.html > > GlennArticle: 134689
A good forum for verification questions is The Verification Guild at http://verificationguild.com/index.phpArticle: 134690
John Larkin wrote: > You can do coarse delays by counting at some modest clock frequency, > and get fine delays from a fast-clocked shift register or a simple > external analog vernier. The analog thing can take you down to > picosecond resolution. > > You can also double resolution by using both clock edges. > > But can you tolerate the 1-clock p-p jitter that you'll get from > asynchronous trigger inputs slamming into a continuous clock? I didn't think so, that's why I designed a hideous analog delay circuit, much like the no-longer-available-at-a-sane-price AD9501. (A current source, integrating cap, comparator and DAC) I ended up with 1200 components on one board for 64 of these delay circuits. And, it uses the difficult to mount AD CMP603 in the 3 mm square CSP that gave me FITS getting a couple boards working. Many, many, many shorts and opens! But, aparently, 2 ns of jitter is NOT a problem. Only the initial delay will suffer the jitter, the width of the second timer will always be synched to the clock, and so the width won't vary. That was the more critical part of it. I'm still researching how you do this with the DDR feature. JonArticle: 134691
I am a complete FPGA newbie. A friend mentioned that the DS-KIT-4VFX12LC-G from Avnet would be a good board for learning about FPGAs so I bought it and installed the ISE 10.1 Webpack. The website tells me that I have already downloaded my 60 day free trial of the EDK, but I don't remember downloading it. I don't even know what the install file would look like if I did download it. I was going to work through the EDK Concepts, Tools, and Techniques and hopefully learn something, but I am completely lost because I don't think I have the EDK. How can I tell if I have the EDK? If I don't have the EDK, is there a way I could get a new 60 day trial of the EDK from Xilinx?Article: 134692
On Aug 25, 4:06=A0pm, wallge <wal...@gmail.com> wrote: > Maybe I just have to experiment with various clock phase shifts until > I get decent looking video through my pixel pipeline...?- Hide quoted tex= t - > > - Show quoted text - Why not, unless you need to change your clock frequency. Btw, 15 Mhz is fairly slow, this would be standard video sensorArticle: 134693
On Aug 26, 12:56=A0pm, Jon Elson <el...@wustl.edu> wrote: > John Larkin wrote: > > You can do coarse delays by counting at some modest clock frequency, > > and get fine delays from a fast-clocked shift register or a simple > > external analog vernier. The analog thing can take you down to > > picosecond resolution. > > > You can also double resolution by using both clock edges. > > > But can you tolerate the 1-clock p-p jitter that you'll get from > > asynchronous trigger inputs slamming into a continuous clock? > > I didn't think so, that's why I designed a hideous analog delay circuit, > much like the no-longer-available-at-a-sane-price AD9501. =A0(A current > source, > integrating cap, comparator and DAC) =A0I ended up with 1200 components o= n > one board for 64 of these delay circuits. =A0And, it uses the difficult t= o > mount AD CMP603 in the 3 mm square CSP that gave me FITS getting a > couple boards working. =A0Many, many, many shorts and opens! > > But, aparently, 2 ns of jitter is NOT a problem. =A0Only the initial dela= y > will suffer the jitter, the width of the second timer will always be > synched to the clock, and so the width won't vary. =A0That was the more > critical part of it. > > I'm still researching how you do this with the DDR feature. > > Jon Hello Jon, The Virtex 4 family has input and output SERDES on their IOs. These are not the MGTs of the FX version, and are on all versions of the Virtex 4s. The SERDES can be used with the DDR registers in the IOB to get even faster performance from them. The SERDES can also be used in pairs to get a larger parallel to serial ratio. What you could do for your application is to use a pair of SERDES to get a 10:1 parallel to serial ratio, and combine that with the DDR registers to get the serial IO running at twice your high speed clock. If you have a high speed clock of say 400 MHz, your serial IO would be running a 800 MHz, and the parallel data path would be running at only 40 MHz. For the output, run your counters at 40 MHz, and scale them to count down by 10. When they are less than ten, use the LSBs to calculate the 10 bit data to give to the output SERDES to put the edge where you want it. Do the same for calculating the duration of the pulse. Since you said you want a pulse as narrow as 10 ns, you might want to use an 8:1 ratio to get rid of the case of two edges within one parallel word. Or run faster with a faster speed grade to get to 500 MHz. For the input, do the inverse. I was not clear if you needed a minimum delay of 10ns, a minimum pulse width or 10 ns, or both. If you need a minimum delay of 10 ns, you would need to run a smaller ratio to get your parallel clock fast enough. Take a look at the Virtex-4 users guide section on the ISERDES and OSERDES for more information about them: http://www.xilinx.com/support/documentation/user_guides/ug070.pdf I also noted that you did not like that they came in BGAs. We have used out side rework shops to place BGAs for us with good results. If I remember correctly, it cost under $100 USD each for just a few boards. I recommend http://www.process-sciences.com/services/default.asp Regards, John McCaskill www.FasterTechnology.comArticle: 134694
"Sepideh Miller" <baghaii@gmail.com> wrote > > How can I tell if I have the EDK? Type xps in Start/Run and click OK. See waht happens... /MikhailArticle: 134695
On Aug 25, 9:00=A0pm, sreenivas.jyo...@gmail.com wrote: > Hi all, > > I am presently doing a project on "Validation and Verification" of > Core control modules. And now i am in writing Test cases for the block > modules. Can anyone shares their knowledge on What is Robustness > testing what kind of importance is there in writing test cases for the > signals and how to judge them whether it performs Robustness test. > Hope to look some exposure on it..so tht i can elaborate some of > queries? > > Thanks, > Design Engg-FPGA, > Moog, Inc The way you phrased your question, it's sort of like saying "I'm going to build a race car. Is it important that it is fast, and how do I tell if it is fast?" If so, I recommend a lot more studying before going to some place like the Verificaiton Guild.Article: 134696
Hi everyone, I've built a small project on the XC3SD1800A kit that receives ethernet frames and displays their content as a 256x256 4-bit greyscale image via its VGA port. This uses 16 BRAMS (inferred) as video-ram. At first the image that got displayed was full of distortions. I also had hold-time violations of more than 8ns to the address lines of some of the BRAMs. After much research I learned that the vga_clk on this particular Xilinx dev-kit is connected to a pin (P26) that goes to a side-bufg (BUFGMUX_X3Y8) at the right-hand side of the die, which can only use the global clock resources of the right-hand side of the chip. So, I've added this constraint to my UCF: INST "Mram_vram*" LOC=RAMB16_X2Y*,RAMB16_X3Y*; And then the other shoe dropped: I'm using the video-ram as dual-port ram: the other clock is the eth_rx_clk which comes from pin P1, which is a left side clock pin. So I end up with error Place:1018 "A clock IOB/clock component pair have been found that are not placed at an optimal clock IOB/clock site pair". I've used the CLOCK_DEDICATED_ROUTE = FALSE setting to get things to compile, but I get a big warning about this being not recommended at all. As this kit comes with a PCB and everything already soldered in place I can't change these pin assignments. Are there any recommended ways to improve timing in such a situation? Regards, Paul Boven.Article: 134697
On Tue, 26 Aug 2008 23:38:00 +0200, Paul Boven <p.boven@xs4all.nl> wrote: >Hi everyone, > >I've built a small project on the XC3SD1800A kit that receives ethernet >frames and displays their content as a 256x256 4-bit greyscale image via >its VGA port. This uses 16 BRAMS (inferred) as video-ram. > >At first the image that got displayed was full of distortions. I also >had hold-time violations of more than 8ns to the address lines of some >of the BRAMs. After much research I learned that the vga_clk on this >particular Xilinx dev-kit is connected to a pin (P26) that goes to a >side-bufg (BUFGMUX_X3Y8) at the right-hand side of the die, which can >only use the global clock resources of the right-hand side of the chip. > >So, I've added this constraint to my UCF: > >INST "Mram_vram*" LOC=RAMB16_X2Y*,RAMB16_X3Y*; > >And then the other shoe dropped: I'm using the video-ram as dual-port >ram: the other clock is the eth_rx_clk which comes from pin P1, which is >a left side clock pin. So I end up with error Place:1018 "A clock >IOB/clock component pair have been found that are not placed at an >optimal clock IOB/clock site pair". >I've used the CLOCK_DEDICATED_ROUTE = FALSE setting to get things to >compile, but I get a big warning about this being not recommended at all. > >As this kit comes with a PCB and everything already soldered in place I >can't change these pin assignments. Are there any recommended ways to >improve timing in such a situation? Derive a third clock from one of these two, in a DCM, which can use globally routable resources? - BrianArticle: 134698
> So, you think a 13-bit counter feeding a 13-bit identity comparator will > work at 250 MHz? Others have said it may be possible but what they fail to acknowledge is the large amount of extra design effort and care required to get there. 250 MHz is really pushing the limits in spartan 3e in my experience. You may have to work very hard to get there: for example I have just finished a distributed arithmetic filter design, that has only 1 LUT level between flops and after a lot of effort I got it to run at 206 MHz in a sp3 1600e. I can see how to get to 220MHz, but beyond that I don't know. The longest carry chain is 10 bits. I had to bypass synthesis and instantiate xilinx primitives directly to gaurantee my logic was implemented in 1 LUT level. Then I had to manually floorplan the design - placing each flop with the corresponding LUT by hand( I uses RLOC's embedded in the VHDL source). The automatic placer didn't always place the LUT with the FLOP so you end up with 2 routes which kills the timing completely. > Yeah, I really don't think we can handle $2000 IC's. =A0This isn't a real > production project, we might build 5 of them at a time, but we are still > cost-sensitive. If its such low volumes just take the unit cost hit and move to a Virtex part. How valuable is your time?Article: 134699
Thank you. I was comparing your code with mine, and I see that the signal DAC_CLR is always high, in your code. In my code I was not setting/using that signal. I see that the DAC manual says: "CLR (Pin 11): Asynchronous Clear Input. A logic low at this level-triggered input clears all registers and causes the DAC voltage outputs to drop to 0V for the LTC2604/LTC2614/ LTC2624." =2E.. Perhaps that can be the problem why the output voltage is always 0.. Second, my code declares the architecture as Behavioral, not as RTL. I still have not checked with the osilloscope, now that I modified. I'll check on this week and post results here. Perhaps someone else 'is having' or 'will have' the same problem. Thank you, m m _____________________________ On Aug 23, 6:47=A0pm, Frank Buss <f...@frank-buss.de> wrote: > I have implemented a simple test for the Spartan 3E starter kit board, > which has the same DAC: > > http://www.frank-buss.de/SignalGenerator/ > > -- > Frank Buss, f...@frank-buss.dehttp://www.frank-buss.de,http://www.it4-sys= tems.de
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