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Messages from 135475

Article: 135475
Subject: synopsys designware components on xilinx fpga
From: "jack.harvard@googlemail.com" <jack.harvard@googlemail.com>
Date: Fri, 3 Oct 2008 06:53:17 -0700 (PDT)
Links: << >>  << T >>  << A >>
Hi,

Just did a bit of search on this newsgroup, basically, what I want to
find out is how I can synthesis my design with synopsys designware
components onto xilinx spartan fpgas. it looks that synplify pro
supports limited designware components (not all the components i've
instantiated), and XST doesn't even support designware, besides, there
is a company offering dw-fpga products http://www.eve-team.com/products/dw-fpga.php.
the info i gathered may not be complete, and may have missed some
obvious ones, i was wondering what the best way is to synthesis my
design to the xilinx spartan fpgas.

thanks a lot,
jack

Article: 135476
Subject: Re: Gee Thanks Altera, I really enjoy having a break waiting on your
From: cs_posting@hotmail.com
Date: Fri, 3 Oct 2008 07:25:04 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Oct 1, 6:28 pm, LittleAlex <alex.lo...@email.com> wrote:

> Note to self:  Next time don't ignore the "your license will expire in
> xx days" messages.

Never saw any such messages.

Given that Quartus is locked with a USB dongle, I maintain that having
to renew the license every year is control-freakism, not reasonable
behavior.

And two days later, still waiting on the file.  Obviously something
broke in the process.



Article: 135477
Subject: Re: Low frequency clock generation - need help
From: "kadhiem_ayob" <kadhiem_ayob@yahoo.co.uk>
Date: Fri, 03 Oct 2008 10:53:25 -0500
Links: << >>  << T >>  << A >>
I know an easier way of generating enable at any rate lower than a master
clock. Use a modulo adder that increments by your required rate and the
modulus to be your master clock. You can even scale the ratio to get power
of 2 modulus. So to get 230400Hz on master clock of 50MHz, your adder can
increment by 230400 and overflow at 50,000,000. Then at overflow generate
an enable pulse. Thats all...

kadhiem



Article: 135478
Subject: Re: Virtex-5 DDR2 DCI termination
From: Barry <barry374@gmail.com>
Date: Fri, 3 Oct 2008 08:56:27 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Oct 3, 1:41=A0am, Rob <BertyBoos...@googlemail.com> wrote:
> Hi all,
>
> I've got a design with that interfaces to a wide (128 bit) DDR2 data
> bus using a V5. I'm currently using the DCI feature to terminate all
> of my signals, however because there are so many the power consumption
> is unacceptably high.
>
> I notice that a new IO standard has recently crept into the
> documentation: SSTL18_II_T_DCI. Although the documentation on this is
> lacking, it looks like this is supposed to remove the termination when
> performing writes. However, when I tried to use it in my design,
> implementation failed because apparently I can't mix
> DIFF_SSTL18_II_DCI and SSTL18_II_T_DCI in the same bank.
> Am I missing something here?? The Xilinx MIG design mandates that data
> strobes and DQ lines must be in the same bank in order to make use of
> the buffio feature. If the two standards can't be mixed then
> SSTL18_II_T_DCI is effectively useless.
>
> Has anyone had any experience with using this new standard?
>
> cheers
> Rob

Hi Rob,
I am using ISE 9.2.04 and it worked successfully for me (just tried it
- no errors).  What version are you using?  I notice that there are
small timing spec differences between the two standards, so some
investigation is warranted there.  Below is an excerpt from my ucf.
Barry



NET  "DDR2_DQ(*)"          IOSTANDARD =3D SSTL18_II_T_DCI;
NET  "DDR2_DM(*)"          IOSTANDARD =3D SSTL18_II_DCI;
NET  "DDR2_DQS(*)"         IOSTANDARD =3D DIFF_SSTL18_II_DCI;
NET  "DDR2_DQS_N(*)"       IOSTANDARD =3D DIFF_SSTL18_II_DCI;

NET  "DDR2_DQ(0)"          LOC =3D "K5" ;       #BANK 12
NET  "DDR2_DQ(1)"          LOC =3D "F5" ;       #BANK 12
NET  "DDR2_DQ(2)"          LOC =3D "J4" ;       #BANK 12
NET  "DDR2_DQ(3)"          LOC =3D "G4" ;       #BANK 12
NET  "DDR2_DQ(4)"          LOC =3D "F4" ;       #BANK 12
NET  "DDR2_DQ(5)"          LOC =3D "M4" ;       #BANK 12
NET  "DDR2_DQ(6)"          LOC =3D "E5" ;       #BANK 12
NET  "DDR2_DQ(7)"          LOC =3D "N6" ;       #BANK 12
NET  "DDR2_DQ(8)"          LOC =3D "K6" ;       #BANK 12
NET  "DDR2_DQ(9)"          LOC =3D "F7" ;       #BANK 12
NET  "DDR2_DQ(10)"         LOC =3D "J6" ;       #BANK 12
NET  "DDR2_DQ(11)"         LOC =3D "G6" ;       #BANK 12
NET  "DDR2_DQ(12)"         LOC =3D "E6" ;       #BANK 12
NET  "DDR2_DQ(13)"         LOC =3D "L5" ;       #BANK 12
NET  "DDR2_DQ(14)"         LOC =3D "E7" ;       #BANK 12
NET  "DDR2_DQ(15)"         LOC =3D "K7" ;       #BANK 12
NET  "DDR2_DM(0)"          LOC =3D "G5" ;       #BANK 12
NET  "DDR2_DM(1)"          LOC =3D "G7" ;       #BANK 12
NET  "DDR2_DQS(0)"         LOC =3D "L4" ;       #BANK 12
NET  "DDR2_DQS_N(0)"       LOC =3D "L3" ;       #BANK 12
NET  "DDR2_DQS(1)"         LOC =3D "L7" ;       #BANK 12
NET  "DDR2_DQS_N(1)"       LOC =3D "M7" ;       #BANK 12

Article: 135479
Subject: Re: Low frequency clock generation - need help
From: thutt <thutt151@comcast.net>
Date: 03 Oct 2008 14:37:52 -0700
Links: << >>  << T >>  << A >>
"kadhiem_ayob" <kadhiem_ayob@yahoo.co.uk> writes:

> I know an easier way of generating enable at any rate lower than a master
> clock. Use a modulo adder that increments by your required rate and the
> modulus to be your master clock. You can even scale the ratio to get power
> of 2 modulus. So to get 230400Hz on master clock of 50MHz, your adder can
> increment by 230400 and overflow at 50,000,000. Then at overflow generate
> an enable pulse. Thats all...
> 
> kadhiem

That's basically what the clkdiv_enable entity is doing.


-- 
Hoegaarden!

Article: 135480
Subject: Re: Low frequency clock generation - need help
From: "kadhiem_ayob" <kadhiem_ayob@yahoo.co.uk>
Date: Fri, 03 Oct 2008 17:38:32 -0500
Links: << >>  << T >>  << A >>
>"kadhiem_ayob" <kadhiem_ayob@yahoo.co.uk> writes:
>
>> I know an easier way of generating enable at any rate lower than a
master
>> clock. Use a modulo adder that increments by your required rate and
the
>> modulus to be your master clock. You can even scale the ratio to get
power
>> of 2 modulus. So to get 230400Hz on master clock of 50MHz, your adder
can
>> increment by 230400 and overflow at 50,000,000. Then at overflow
generate
>> an enable pulse. Thats all...
>> 
>> kadhiem
>
>That's basically what the clkdiv_enable entity is doing.
>
>
>-- 
>Hoegaarden!
>
Hi Hoegaarden
But the code can be just as follows:
---------------------------------------
signal modulo_adder:integer range 0 to 2**26-1

process(reset,clk)
begin
if(reset = '1')then
   modulo_adder <= 0;
   enable <= '0';
elsif(rising_edge(clk))then
   if(modulo_adder < 50000000)then
      modulo_adder <= modulo_adder + 230400;
      enable <= '0';
   else
      modulo_adder <= modulo_adder + 230400 - 50000000; --wrap up
      enable <= '1';
   end if;
end if;
end process;
-------------------------------
for a binary adder, the code reduces to fewer lines but needs scaling of
clk and increment values.


      



Article: 135481
Subject: Re: synopsys designware components on xilinx fpga
From: mike_la_jolla <mdini@dinigroup.com>
Date: Fri, 3 Oct 2008 18:25:15 -0700 (PDT)
Links: << >>  << T >>  << A >>
Jack -- The EVE product should do this and is much, much cheaper than
using Synopsys/Synplicity.  Here in La Jolla we use the EVE product or
replace the DesignWare components with functional descriptions.  Most
DesignWare components are easy to reverse engineer and you shouldn't
be using the ones that aren't.

Article: 135482
Subject: Re: Low frequency clock generation - need help
From: thutt <thutt151@comcast.net>
Date: 04 Oct 2008 08:13:12 -0700
Links: << >>  << T >>  << A >>
"kadhiem_ayob" <kadhiem_ayob@yahoo.co.uk> writes:

> >"kadhiem_ayob" <kadhiem_ayob@yahoo.co.uk> writes:
> >
> >> I know an easier way of generating enable at any rate lower than a
> master
> >> clock. Use a modulo adder that increments by your required rate and

<snip>

> >That's basically what the clkdiv_enable entity is doing.
> >
> >
> >-- 
> >Hoegaarden!
> >
> Hi Hoegaarden
> But the code can be just as follows:
> ---------------------------------------
> signal modulo_adder:integer range 0 to 2**26-1
> 
> process(reset,clk)
> begin
> if(reset = '1')then
>    modulo_adder <= 0;
>    enable <= '0';
> elsif(rising_edge(clk))then
>    if(modulo_adder < 50000000)then
>       modulo_adder <= modulo_adder + 230400;
>       enable <= '0';
>    else
>       modulo_adder <= modulo_adder + 230400 - 50000000; --wrap up
>       enable <= '1';
>    end if;
> end if;
> end process;
> -------------------------------
> for a binary adder, the code reduces to fewer lines but needs scaling of
> clk and increment values.

An entity which can be used as a generalized object is a lot more
convenient, don't you agree?

thutt
-- 
Hoegaarden!

Article: 135483
Subject: Do two clock system blocks with one clock running half of other's
From: Weng Tianxiang <wtxwtx@gmail.com>
Date: Sat, 4 Oct 2008 09:09:13 -0700 (PDT)
Links: << >>  << T >>  << A >>
Hi,
I have no such experiences and ask for the question answers:

is it possible that two clock system blocks with one clock running
half of other's of same clock source don't need asynchronous input/
output buffers in best circuit and logic design?

Especially, for example Intel and AMD CPU chip's, their cache I runs
half frequency of CPU clock and gets almost 1/2 data rate as documents
show.

What is their designs standout? I know Xilinx chip has divided clock
outputs in addition to the main clock output and never have such an
experiences to use the technique.

I need a guidance and direction instructions on the subject. A book or
a paper reference is preferred.

Thank you.

Weng

Article: 135484
Subject: Xilinx PCIE problem
From: "bjzhangwn@gmail.com" <bjzhangwn@gmail.com>
Date: Sat, 4 Oct 2008 09:26:56 -0700 (PDT)
Links: << >>  << T >>  << A >>
Now I use the V5-lx30t as PCIE interface,and the pcb done.When I use
the borad to download a demo for testing,and the board does't work,the
PC can't find new hardware insert,the clock is right,the configuration
as bellow:block plus 1.6 for PCIE 1X synthesis tool :XST,I dont't know
why the pc can't detect the new hardware,if it have something wrong
with the PCB design,Also I want to see the ltssm state but I don't
know how?Some anyone give me some advice.

Article: 135485
Subject: Re: Low frequency clock generation - need help
From: "kadhiem_ayob" <kadhiem_ayob@yahoo.co.uk>
Date: Sat, 04 Oct 2008 11:33:36 -0500
Links: << >>  << T >>  << A >>
>An entity which can be used as a generalized object is a lot more
>convenient, don't you agree?
>
>thutt
>-- 
>Hoegaarden!

>Hi again
I do agree with the reuse idea. There is nothing to stop us making a
reusable module from above simple proven code. In this case, I need to add
the following: 
You need to add one more bit to the modulo adder than I did above to
account for the case when the increment is too large, otherwise the
overflow will go undetected.

Also notice that you can factorise the ratio to smaller values if you
wish.

Kadhiem





Article: 135486
Subject: Re: Do two clock system blocks with one clock running half of other's need asynchronous input/output buffers?
From: "kadhiem_ayob" <kadhiem_ayob@yahoo.co.uk>
Date: Sat, 04 Oct 2008 12:25:35 -0500
Links: << >>  << T >>  << A >>
>Hi,
>I have no such experiences and ask for the question answers:
>
>is it possible that two clock system blocks with one clock running
>half of other's of same clock source don't need asynchronous input/
>output buffers in best circuit and logic design?
>
>Especially, for example Intel and AMD CPU chip's, their cache I runs
>half frequency of CPU clock and gets almost 1/2 data rate as documents
>show.
>
>What is their designs standout? I know Xilinx chip has divided clock
>outputs in addition to the main clock output and never have such an
>experiences to use the technique.
>
>I need a guidance and direction instructions on the subject. A book or
>a paper reference is preferred.
>
>Thank you.
>
>Weng
>


Hi Weng,

I am not sure about your design platform but from FPGA perspective:
If the two clocks are locked(frequency and phase), then you can consider
them synchronised assuming we trust the generating source. In this case
there is no need to make extra efforts to cross domains. The issue you
should be aware of is that they might not always be in phase as assumed and
in this case any phase-sensitive logic may occasionally fail. For example a
pulse generated in the fast domain failing to be seen by the edge of slow
clock, this commonly leads to power-up problems. If the clocks are not in
phase "by design, for some reason" then your compiler should tell you if
there is any setup or hold violations. If there is violation I will
consider them asynchronous.

For asynchronous clocks inside FPGAs, I normally use dual clock fifos for
main crossing areas. Alternatively, you can make your crossing plans based
on double register synchronisation and correct data transfer

If your clocks are external(between chips) - as I understand from your
description - then this is a different matter. Board delay differences are
inevitable. All I can say is that they are asynchronous. So you better
cross domains with care or lock them together(e.g. inside an FPGA but this
requires costly loop design).

Remember a phase lock loop uses phase difference to lock two frequencies
but this doesn't usually mean they are locked with respect to absolute
phase unless extra design effort is added.

Kadhiem   

 

Article: 135487
Subject: Video processing in FPGA
From: Moti <motic.mail@gmail.com>
Date: Sat, 4 Oct 2008 12:17:59 -0700 (PDT)
Links: << >>  << T >>  << A >>
Hi all,
First of all I would like to mention that I'm not familiar with video
processing at all.
I need to have FPGA based board that will in order to perform a demo.
For that reason I would like to buy a (ready-to-use) board that will
get a video signal (preferably by camera but it can also come from PC
or other video sources) as an input to the FPGA than I would like to
do some basic real-time processing on the video stream (Color,2D etc.)
and send the resulting video stream to an external LCD monitor.

I will be happy to learn the following:

1) I saw that there are several types of interfaces (S-video/VGA/DVI
etc.) and also several digital video protocols. What are the most easy
to use digital interfaces that I should use (both for video in/out) ?

2) What type of camera should I use ?

3) is there a proto board that you can recommend on that comply with
the answers to questions 1/2 ?

Thanks in advance, Moti.


Article: 135488
Subject: Re: Video processing in FPGA
From: John_H <newsgroup@johnhandwork.com>
Date: Sat, 04 Oct 2008 13:47:55 -0700
Links: << >>  << T >>  << A >>
Moti wrote:
> Hi all,
> First of all I would like to mention that I'm not familiar with video
> processing at all.
> I need to have FPGA based board that will in order to perform a demo.
<snip>

Why do you want to demo something you know nothing about?

What makes you believe you can demo the processing you suggest?

Article: 135489
Subject: Bitstream configuration question (virtex 5).
From: dajjou <swissiyoussef@gmail.com>
Date: Sat, 4 Oct 2008 14:16:11 -0700 (PDT)
Links: << >>  << T >>  << A >>
Hello,

 I would like to know why for the PROM file (.mcs) there is a bit
swapping and why it's not the case for the bit file (.bit or .rbt) ?!
 Is the bitstream reformatted inside the PROM before to be sent to
FPGA ?
 What is the role of Synchronization word (bitstream composition) ?

Thank you

Article: 135490
Subject: Xilinx PCIE problem
From: "bjzhangwn@gmail.com" <bjzhangwn@gmail.com>
Date: Sat, 4 Oct 2008 18:47:29 -0700 (PDT)
Links: << >>  << T >>  << A >>
Now I use the V5-lx30t as PCIE interface,and the pcb done.When I use
the borad to download a demo for testing,and the board does't work,the
PC can't find new hardware insert,the clock is right,the configuration
as bellow:block plus 1.6 for PCIE 1X synthesis tool :XST,I dont't know
why the pc can't detect the new hardware,if it have something wrong
with the PCB design,Also I want to see the ltssm state but I don't
know how?Some anyone give me some advice.

Article: 135491
Subject: Virtex-5 Integrated Endpoint Block for PCI Express Designs
From: "bjzhangwn@gmail.com" <bjzhangwn@gmail.com>
Date: Sat, 4 Oct 2008 18:59:20 -0700 (PDT)
Links: << >>  << T >>  << A >>
I use virtex-5 lx30T to design a pcie endpoint,I chose 1 lane for test
and all the pin lock is the default,the clock is correct,I download a
demo test and insert the card in the PC slot,but the PC can't detect
the card,can any give me some advice,how can I see the ltssm state?

Article: 135492
Subject: Re: Xilinx PCIE problem
From: "Pete Fraser" <pfraser@covad.net>
Date: Sat, 4 Oct 2008 20:55:39 -0700
Links: << >>  << T >>  << A >>

<bjzhangwn@gmail.com> wrote in message 
news:ed9961ef-f806-499f-9eb8-a097b396491e@x16g2000prn.googlegroups.com...
> Now I use the V5-lx30t as PCIE interface,and the pcb done.When I use
> the borad to download a demo for testing,and the board does't work,the
> PC can't find new hardware insert,the clock is right,the configuration
> as bellow:block plus 1.6 for PCIE 1X synthesis tool :XST,I dont't know
> why the pc can't detect the new hardware,if it have something wrong
> with the PCB design,Also I want to see the ltssm state but I don't
> know how?Some anyone give me some advice.

Have you looked at it with diagnostic software (e.g., PCIscope
or PCITree)? If so, can that see the board? 



Article: 135493
Subject: OTU2 implementation with Virtex 4
From: Ali <ali.arabi@gmail.com>
Date: Sun, 5 Oct 2008 03:20:57 -0700 (PDT)
Links: << >>  << T >>  << A >>
I have a specific query regarding the usage of SelectIO/RocketIO
SERDES features available in Vertex 4. I want to implement OTU2 with
Virtex 4 and I wonder if this possible that use RocketIO .What I have
understood that these features are mainly applicable for high speed
serial communication protocols like PCI express, SATA etc. They also
have some special hardware features like 8B/10B encoding/decoding
logic built into the device for specific high speed serial
communication applications.
In my application, I need to add FEC data to STM64 and generate G.709
OTU2 data format.

Article: 135494
Subject: Xilinx cores with license
From: FP <FPGA.unknown@gmail.com>
Date: Sun, 5 Oct 2008 05:09:29 -0700 (PDT)
Links: << >>  << T >>  << A >>
I dont have a license for Xilinx cores like PCIe, RocketIO, DDR2
controller and Chipscope. Can I use these cores in my project if my
friends can email me the cores generated on their PC with their
license? The tools used are Endpoint Block Plus 1.9, Virtex-5 Aurora,
MIG2.3.

Please help. Thank you for your co-operation.

Article: 135495
Subject: Re: Xilinx device not listed
From: FP <FPGA.unknown@gmail.com>
Date: Sun, 5 Oct 2008 05:12:35 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Oct 2, 8:29=A0am, Gabor <ga...@alacron.com> wrote:
> On Oct 1, 6:59=A0pm, Ed McGettigan <ed.mcgetti...@xilinx.com> wrote:
>
>
>
>
>
> > FP wrote:
> > > On Oct 1, 4:43 pm, Mike Treseler <mtrese...@gmail.com> wrote:
> > >> FP wrote:
> > >>> I have a quick question. I dont see Xilinx Virtex -5 sx95t device i=
n
> > >>> the list of devices in Xilinx ISE and CoreGen. How do I fix this
> > >>> issue? I have unistalled and reinstalled ISE.
> > >> Maybe you are using webpack.
> > >> See:http://www.xilinx.com/ise_eval/index.htm
>
> > > Thank you for your quick reply. I am using Webpack.
>
> > This devices is not supported in the Webpack version. =A0You need the f=
ull
> > software version to use a XC5VSX95T device.
>
> > Ed McGettigan
> > --
> > Xilinx Inc.
>
> This sort of issue pops up a lot on the Xilinx forums. =A0Perhaps the
> WebPack download page should have a more evident link to the device
> support on the Xilinx site. =A0I found the information in the ISE Design
> Suite release notes, but it isn't obvious to the average WebPack
> user (read newbie) that you need to search around for this
> information.
>
> Just my 2 cents,
> Gabor- Hide quoted text -
>
> - Show quoted text -

I agree with Gabor. I wasted 1 day unistalling and installing
everything and then updating Xilinx ISE webpack(which takes forever)
to make sure I had the latest version. Finally after posting here I
found that sx95t was not supported by webpack.

FP

Article: 135496
Subject: A question about the use of FPGA
From: Alex <victous@gmail.com>
Date: Sun, 5 Oct 2008 12:57:38 -0700 (PDT)
Links: << >>  << T >>  << A >>
Hello All,

I am a beginner in FPGA design and interested whether it's possible to
use FPGA after it's being programmed (I have Spartan3E 1600E
Microblaze Development Kit which is equipped with XC3S1600E) somewhere
else - not only on the kit board but with other PCBs as well. For
example, after my design is downloaded on FPGA I may wish to take this
FPGA out of socket and insert it somewhere else, to other PCB, would
it work then? (assuming that all soldering is well done)

I guess that as it's SRAM-based FPGA it can be used only on the board
where it's programmed - is this correct? If so, then my FPGA is
suitable only for use with the kit and I can implement only one design
at a moment of time, isn't it?

Thank you.

Vladimir

Article: 135497
Subject: ISE Question - FPGA Program.jpg (0/1)
From: Eric <ebx56@hotmail.com>
Date: Sun, 05 Oct 2008 13:11:44 -0700
Links: << >>  << T >>  << A >>
I got the Spartan 3A Digilent development kit and I am trying to do a
simple circuit just to get the FPGA design procedure correct under ISE
10.1. I synthesize, implement design and generate programming file.
When I dbl click on 'Configure Target Device' I get a dialog that says
"Warining:A project file exists, but no target device has been
designated. Click OK to open iMPACT..."

 i click OK but nothing happens. "Configure Target Device" now has a
green checkmark next to it, and I see my PROM/ FPGA device chain in a
window called Prom File Formatter. But under my Operations menu item,
everything is grayed out so I cannot program my FPGA.

What am I doing wrong?

A frustrated newbie.

Article: 135498
Subject: Spartan 3E overmapping problem
From: Nicolas Matringe <nicolas.matringe@fre.fre>
Date: Sun, 05 Oct 2008 22:18:00 +0200
Links: << >>  << T >>  << A >>
Hello all
I have a design that occupies 65% of FFS, 85% of LUTs but 110% of slices.
I can't seem to find the right options to force logic packing
I am using ISE Webpack 10.1 SP3

Thanks in advance
Nicolas

Article: 135499
Subject: Re: A question about the use of FPGA
From: Frank Buss <fb@frank-buss.de>
Date: Sun, 5 Oct 2008 22:28:46 +0200
Links: << >>  << T >>  << A >>
Alex wrote:

> I am a beginner in FPGA design and interested whether it's possible to
> use FPGA after it's being programmed (I have Spartan3E 1600E
> Microblaze Development Kit which is equipped with XC3S1600E) somewhere
> else - not only on the kit board but with other PCBs as well. For
> example, after my design is downloaded on FPGA I may wish to take this
> FPGA out of socket and insert it somewhere else, to other PCB, would
> it work then? (assuming that all soldering is well done)
> 
> I guess that as it's SRAM-based FPGA it can be used only on the board
> where it's programmed - is this correct? If so, then my FPGA is
> suitable only for use with the kit and I can implement only one design
> at a moment of time, isn't it?

Another interesting posting from a gmail-account :-) You should read the
documentation for your board carefully again. Most boards have a serial
Flash chip, where you can save your configuration. On power-up the FPGA
reads the content of the Flash in the SRAM.

But you can't insert BGA chips anyway to other boards, it is a complicated
soldering process for good contact of the pins. Nevertheless there are some
people who try it themselves, e.g. with an electric iron:

http://www.lrr.in.tum.de/~acher/bga/index.html

Best idea would be to use a header board, if you want to integrate a FPGA
in your own hobby project circuit, or use a smaller FPGA with QFP pins,
which can be soldered by hand.

-- 
Frank Buss, fb@frank-buss.de
http://www.frank-buss.de, http://www.it4-systems.de



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