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On Thu, 11 Sep 2008 07:57:39 -0700 (PDT), rickman <gnuarm@gmail.com> wrote: |On Sep 11, 7:19 am, aleksa <aleks...@gmail.com> wrote: |> On Sep 10, 10:13 am, aleksa <aleks...@gmail.com> wrote: |> |> > Are PROGRAM, CCLK, CS and DIN 5V tolerant, during configuration? |> |> > The CS pin, according to the docs, should be connected to high logic |> > level. |> |> > I have connected all VCCO to 3.3V. |> |> > Anyone? |> |> Nobody knows? |> |> #%$&@#$*&@, I will place some resistors... | | |I don't understand your question. The subject line asks if the parts |are 5 volt tolerant and then you say you are connecting them to 3.3 |volts. I don't see where the problem is. | |I am pretty sure the data sheet clearly indicates that the parts are |*not* 5 volt tolerant although I have not looked. I am basing this on |the fact that Xilinx left 5 volt tolerance behind many years ago with |the initial Spartan series with the Spartan II not being 5 volt |tolerant, IIRC. But I won't swear to that. Check the maximum DC |levels in the specs. | |Connecting to 3.3 volts should certainly be ok as long as you never |want to drive the pins low again. If the trace and via to power are |under the chip, you won't even be able to cut the trace easily. | |What exactly is your concern? | |Rick | |------------ Rick I believe that the Spartan II is the last FPGA that Xilinx made that has 5 volt tolerant inputs. The Spartan IIe does not. jamesArticle: 135051
You might look at Actel Igloo. AndyArticle: 135052
On Sep 12, 8:37=A0am, michael...@gmx.de (Michael Dreschmann) wrote: > Hi all! > > For an actual project I'm looking for an ultra low power FPGA. The > size is not so important, we probably don't need much more resources > that an CPLD would provide but power is absolutely critical. > I heard already about Siliconblue but does someone of you know of any > other devices playing in the same league to get some overview? > Siliconblue seams to be very new on the market and this means a > certain risk. Some nonvolatile config memory also would be preferable. It would help if you gave more details with your question. From what you said, it seems like a CPLD would do the job. There are several zero-power families out there. Xilinx has the older XPLA (XCR3xxx) devices which are "true" zero power with a very low quiescent current as well as a low Icc vs. Freq curve. I think Altera has come out with something similar recently, but it may not be as low power. Lattice also has the ispMACH 4000 family which is pretty good. A lot of folks are stressing the quiescent current and not mentioning the active current levels. How low power do you need and what is most important, active current or quiescent? What clock rates are you using? Will the part be mostly idle or very active? What size will your design be? RickArticle: 135053
On 12 Sep, 13:27, Patrick Dubois <prdub...@gmail.com> wrote: > On Sep 11, 5:03=A0pm, wallge <wal...@gmail.com> wrote: > > > > > > > I recently built a screaming fast machine for doing my FPGA > > simulations and compiles. > > I just ran a design compile for purposes of comparison on my new Core2 > > Extreme Quad =A0based machine > > and my old dual processor Xeon machine. > > > -----------------------------------------------------------------------= ----=AD------------- > > Here are the system specs for old machine: > > 2 Intel Xeon CPU model 4, stepping 3 at 3.2 GHz > > 4GB DDR PC2700 > > FSB speed 800 MHz. > > The motherboard is a =A0Supermicro X6DAT-G > > -----------------------------------------------------------------------= ----=AD--------------- > > Here are the system specs for the new machine: > > Intel Core2 Extreme CPU QX9770 @3.2 GHz (quad core) > > OCZ Platinum 4GB (2 x 2GB) 240-Pin DDR3 SDRAM DDR3 2000 (PC3 16000) > > Dual Channel > > FSB speed 1600 MHz. > > The motherboard is a =A0ASUS P5E3 PREMIUM/WIFI-AP @n LGA 775 > > > ThebenchmarkI used is a project that I am working on that utilizes > > most > > of the memory and LEs on a stratix I 60K LE device. > > > Quartus took about 33 min to finish the compile on the older machine > > The new machine took 12 min to finish. > > > I was not expecting a 3X speedup! > > I guess main memory speed is the major bottleneck for compilation. > > Wow, that's quite an impressive speed-up. I wish I could convince my > company to buy a beast like that. My current design takes about 45 > minutes for the PAR, on a 3.0 GHz Core 2 Duo. Show them the numbers to illustrate how much more productive you could be. No doubt your time is much more expensive than a new PC. JonArticle: 135054
Hi! Thanks for your suggestions. >It would help if you gave more details with your question. From what >you said, it seems like a CPLD would do the job. It's a research project at a university and at the moment we don't know exactly what we want to include in the CPLD/FPGA. A manchester encoder (100-200 MBit), a manchester decoder (some MBit) and some datasignal conversation from a video camera for shure, but if possible also some further analysing of the videoframes and so on. Hard to say. I would prefer a FPGA because then we porbably won't come to the limit of a familiy so fast. >How low power do you need and what is most important, active current >or quiescent? The active current is important, if we don't need the FPGA it will be completely disconnected from power. There is no limit in "how low power", the more low power the besser because the energy source will last longer ;) >What clock rates are you using? Will the part be >mostly idle or very active? What size will your design be? The clockrates I would guess arround 40 MHz, apppart from the manchester encoder/decoder and as said before everytime it's powered it'll be probably full active. MichaelArticle: 135055
>Here are the system specs for old machine: >2 Intel Xeon CPU model 4, stepping 3 at 3.2 GHz >4GB DDR PC2700 >FSB speed 800 MHz. >The motherboard is a Supermicro X6DAT-G >Here are the system specs for the new machine: >Intel Core2 Extreme CPU QX9770 @3.2 GHz (quad core) >OCZ Platinum 4GB (2 x 2GB) 240-Pin DDR3 SDRAM DDR3 2000 (PC3 16000) >Dual Channel >FSB speed 1600 MHz. >The motherboard is a ASUS P5E3 PREMIUM/WIFI-AP @n LGA 775 Computer "old": 3.2 GHz 2 MB cache 2700 MB/s FSB 800 MHz Processing time: 33 minutes Computer "new": 3.2 GHz 2x6 MB L2 16000 MB/s dual channel => 25600 MB/s FSB 1600 MHz Processing time: 12 minutes Considering the data I think that mainly the onchip cache is responsible and the fact that the cpu<->memory bandwidth is increased by a factor of 3.2x The current software doesn't give any advantage of having multiple cpus asfaik. I think you could possible improve the speed by getting a cpu with even larger onchip cache. And maybe 1 GHz faster clock. An more efficient OS can also help.Article: 135056
>> Wow, that's quite an impressive speed-up. I wish I could convince my >> company to buy a beast like that. My current design takes about 45 >> minutes for the PAR, on a 3.0 GHz Core 2 Duo. >Show them the numbers to illustrate how much more productive you could >be. >No doubt your time is much more expensive than a new PC. Let's not forget that the change->process->upload->test cycle is repeated many times throughout a day. Multiplied by the sallary. And that deadlines may be reached faster it should be a no brainer.Article: 135057
On Sep 12, 10:02=A0am, sky46...@trline4.org wrote: > >Here are the system specs for old machine: > >2 Intel Xeon CPU model 4, stepping 3 at 3.2 GHz > >4GB DDR PC2700 > >FSB speed 800 MHz. > >The motherboard is a =A0Supermicro X6DAT-G > >Here are the system specs for the new machine: > >Intel Core2 Extreme CPU QX9770 @3.2 GHz (quad core) > >OCZ Platinum 4GB (2 x 2GB) 240-Pin DDR3 SDRAM DDR3 2000 (PC3 16000) > >Dual Channel > >FSB speed 1600 MHz. > >The motherboard is a =A0ASUS P5E3 PREMIUM/WIFI-AP @n LGA 775 > > Computer "old": > =A0 3.2 GHz =A0 =A0 =A0 =A0 2 MB cache > =A0 =A02700 MB/s > =A0 FSB 800 MHz > =A0 Processing time: 33 minutes > > Computer "new": > =A0 3.2 GHz =A0 =A0 =A0 =A0 2x6 MB L2 > =A0 16000 MB/s =A0 =A0 dual channel =3D> 25600 MB/s > =A0 FSB 1600 MHz > =A0 Processing time: 12 minutes > > Considering the data I think that mainly the onchip cache is responsible = and > the fact that the cpu<->memory bandwidth is increased by a factor of 3.2x > > The current software doesn't give any advantage of having multiple cpus a= sfaik. > > I think you could possible improve the speed by getting a cpu with even l= arger > onchip cache. And maybe 1 GHz faster clock. An more efficient OS can also= help. Apparently (I think I actually read it on comp.arch.fpga from an Altera Rep.) using additional CPUs adds a 10~15% speedup in Quartus.I guess Altera is gradually parallelizing both synthesis and P&R algorithms. On a separate note, the machine only cost me ~ $2700 to build. The most expensive part was the CPU at around $1500, and next was the mother board and memory both coming in at close to $400 as I recall. Most of the other parts (HDD, DVDR, Graphics card, case, CPU fan) were at or around $100. I didn't spend lots on the GPU since it does not contribute to fast compiles. Also the old machine ran windows XP, the new one runs Vista (I had a free upgrade to it). We don't run linux because the licenses are more expensive and because our other tools are windows based.Article: 135058
On Sep 12, 10:12=A0am, sky46...@trline4.org wrote: > >> Wow, that's quite an impressive speed-up. I wish I could convince my > >> company to buy a beast like that. My current design takes about 45 > >> minutes for the PAR, on a 3.0 GHz Core 2 Duo. > >Show them the numbers to illustrate how much more productive you could > >be. > >No doubt your time is much more expensive than a new PC. > > Let's not forget that the change->process->upload->test cycle is repeated= many > times throughout a day. Multiplied by the sallary. And that deadlines may > be reached faster it should be a no brainer. If that cycle is being repeated many times throughout the day, you could probably benefit much more with a process change that involves more extensive simulation and only a single build...your productivity will likely increase dramatically. KJArticle: 135059
"Pablo" <pbantunez@gmail.com> wrote in message news:6ce4c6db-5411-4fa7-bfcf-e5e1f0be95b6@z72g2000hsb.googlegroups.com... > - >> The simple answer is Impact can't and doesn't do that, and the >> unprogrammed >> device wouldn't be able to read its bitstream even if it did. (Why do we >> bother with MIG and MPMC otherwise?) > > So, there is nothing to do. > >> Is this a Spartan3-AN device? > > It is a Custom Board with a VirtexIIPro and a Micron External Memory. I'd be interested in the details. What does it do when you power up? From where does it read its initial bitstream? If there's no flash or ROM, there's an active agent, either external or onboard, stuffing a bitstream to the device. Is there an MCU onboard? Does it require an external JTAG connection for bootup?Article: 135060
Michael Dreschmann wrote: > The active current is important, if we don't need the FPGA it will be > completely disconnected from power. There is no limit in "how low > power", the more low power the besser because the energy source will > last longer ;) Why not just using a big FET switch for disconnecting it from power? Then it will need (nearly) no power, when disconnected. -- Frank Buss, fb@frank-buss.de http://www.frank-buss.de, http://www.it4-systems.deArticle: 135061
Hi All, I've been trying to interface the M50LW064D to digilent nexys spartan 3 board. The idea is to unprotect the protected blocks and program the flash chip. Has any one done this before or point me in the right direction? My skill level is newbie M58LW064D datasheet: http://www.st.com/stonline/books/pdf/docs/8938.pdf nexys board info http://www.digilentinc.com/Products/Detail.cfm?Prod=NEXYS&Nav1=Products&Nav2=Programmable I have a BGA to DIP adapter and planning on using the FX2-BB boardArticle: 135062
On Sep 12, 9:58=A0am, michael...@gmx.de (Michael Dreschmann) wrote: > Hi! > > Thanks for your suggestions. > > >It would help if you gave more details with your question. =A0From what > >you said, it seems like a CPLD would do the job. > > It's a research project at a university and at the moment we don't > know exactly what we want to include in the CPLD/FPGA. A manchester > encoder (100-200 MBit), a manchester decoder (some MBit) and some > datasignal conversation from a video camera for shure, but if possible > also some further analysing of the videoframes and so on. Hard to say. > I would prefer a FPGA because then we porbably won't come to the limit > of a familiy so fast. > > >How low power do you need and what is most important, active current > >or quiescent? > > The active current is important, if we don't need the FPGA it will be > completely disconnected from power. There is no limit in "how low > power", the more low power the besser because the energy source will > last longer ;) > > >What clock rates are you using? =A0Will the part be > >mostly idle or very active? =A0What size will your design be? > > The clockrates I would guess arround 40 MHz, apppart from the > manchester encoder/decoder and as said before everytime it's powered > it'll be probably full active. Of course lower power is better. That is a given. But you need to quantify a value. Otherwise you have no idea when when you have found a part that is "good enough". You need to set some design goals for battery life and with the size of the battery you can use, spec a max active current. No point in even looking at PLDs until you know what you are looking for. I have not looked hard at the SiBlue parts as they are very new and not mature enough for most projects. Otherwise, Assuming that the design is small enough that the quiescent current dominates, in an FPGA you are likely looking at a minimum of around 100 mA (give or take 50 mA) at the core voltage for a small design running at 40 MHz. BTW, a manchester encoder/decoder is typically a *very* small design, so even at 200 MHz, it won't use much power. The CPLDs can run in the low mA range depending on your design size. They are very linear with speed and the amount of logic used, going to nearly zero when the clock is stopped or the design size approaches zero. In a nutshell this is what you are likely to find. So can you live with around 100 mA active current or do you need to keep looking and/ or consider a CPLD? If you really need to know how low the power is, you need to figure out just how large your design is. I don't know your constraints working at the University, but in a commercial application, if we don't have good info on the FPGA design we want, it would be prototyped in an eval board before we would attempt to spec any hardware. Is there a reason that you need to spec your hardware before you know what it will be hosting? RickArticle: 135063
I am setting up a signal integrity simulation of a Virtex-4 DDR2 memory interface with Agilent's ADS. According to the readme file in the Virtex-4 IBIS distribution, on has to add a "a 50-65 ohm transmission line with 10-200ps of delay" to properly model package parasitics, so I have added a transmission line between the driver output and the PCB load. The IBIS model, however, already has a model for package parasitics (R_pkg, L_pkg, C_pkg) so I am wondering how these will interact. From what I understand, this transmission line models a trace in the "redistribution layer" inside the BGA package, so ideally it should be embedded in the IBIS model before R_pkg, L_pkg, C_pkg, not after, right? Austin, do you have any recommendations? ThanksArticle: 135064
Michael Dreschmann wrote: > Hi! > > Thanks for your suggestions. > > >>It would help if you gave more details with your question. From what >>you said, it seems like a CPLD would do the job. > > > It's a research project at a university and at the moment we don't > know exactly what we want to include in the CPLD/FPGA. If it is a research project, why does power matter so much ? What is powering this, for how long ? > A manchester > encoder (100-200 MBit), a manchester decoder (some MBit) and some > datasignal conversation from a video camera for shure, Up to here it is sounding relatively simple > but if possible > also some further analysing of the videoframes and so on. but that is suddenly very open-ended :) > Hard to say. > I would prefer a FPGA because then we porbably won't come to the limit > of a familiy so fast. > > >>How low power do you need and what is most important, active current >>or quiescent? > > > The active current is important, if we don't need the FPGA it will be > completely disconnected from power. What makes that decison > If you have an external uC, then adjust that for lowest Static/idle power. You could consider both a CPLD and a FPGA, and put the small and sell defined tasks into a CPLD, and then move the higher power/less frequently needed stuff into a FPGA. There is a finitie cold-start time on a FPGA. > There is no limit in "how low > power", the more low power the besser because the energy source will > last longer ;) > > >>What clock rates are you using? Will the part be >>mostly idle or very active? What size will your design be? > > > The clockrates I would guess arround 40 MHz, apppart from the > manchester encoder/decoder and as said before everytime it's powered > it'll be probably full active. Then the uA/MHz numbers will matter most, and if you can push down the MHz, you can start to lower Vcc. Some vendors have more info than others here. -jgArticle: 135065
Hello, I need to replace 12ns SRAMs with equivalent 8ns chips, (256K * 16 bits, 44-pin in TSOP-2 / .8mm pitch) but I can't find them without an excessive price tag. Cypress and Alliance don't go faster than 10ns and I've only found suitable references from ISSI : IS61LV51216-8T and GSI : GS74116TP-8 All I need is aprox. 8 units (6 to 12 is OK) but Farnell has only 3 pc and the others have no stock. Another distributor proposes 30pc but the unit price multiplied by the quantity, plus shipping and customs (I'm in France) completely explode my budget. Can somebody point me to other sources ? Are there other newsgroups likely to use or know how to find these chips ? Thanks, ygArticle: 135066
whygee wrote: > Hello, > > I need to replace 12ns SRAMs with equivalent 8ns chips, > (256K * 16 bits, 44-pin in TSOP-2 / .8mm pitch) > but I can't find them without an excessive price tag. > > Cypress and Alliance don't go faster than 10ns > and I've only found suitable references from > ISSI : IS61LV51216-8T and GSI : GS74116TP-8 > > All I need is aprox. 8 units (6 to 12 is OK) > but Farnell has only 3 pc and the others have no stock. > Another distributor proposes 30pc but the unit price > multiplied by the quantity, plus shipping and customs > (I'm in France) completely explode my budget. > > Can somebody point me to other sources ? > Are there other newsgroups likely to use > or know how to find these chips ? > > Thanks, > yg http://www.findchips.com/ gives two disti hits for IS61LV51216-8T -jgArticle: 135067
Jim Granville wrote: > http://www.findchips.com/ > gives two disti hits for IS61LV51216-8T Thank you very much ! > -jg ygArticle: 135068
dudesinmexico wrote: > > According to the readme file in the Virtex-4 IBIS distribution, on has > to add a "a 50-65 ohm transmission line with 10-200ps of delay" to > properly model package parasitics, so I have added a transmission line > between the driver output and the PCB load. > What version/date are the IBIS files you're looking at? As of a couple years ago(?), Xilinx switched the V4 and V5 IBIS package modeling over to a coupled lumped model using a separate .pkg file. See chapter 4 of UG112 3v0, in particular page 70 onwards: http://www.xilinx.com/support/documentation/user_guides/ug112.pdf I don't think the older TLine modeling advice would be applicable to these newer IBIS files using the package coupling data; e.g. footnote 1 of UG112 table 4-3 reads: "The I/O data reflects the full FC interconnect chain-bump, the vias, traces, and external balls as depicted in Figure 4-3." Which I would interpret as saying that the RLC model in the .pkg files incorporates the delays that were formerly modeled with the TLine. (figures 4-6 and 4-8 are also quite handy) Based on past experiences with IBIS models and simulators, I would advise first running some basic sanity checks to verify that the simulator and vendor models are on the same page with respect to package delays, on chip terminations, etc. BrianArticle: 135069
> Wow, that's quite an impressive speed-up. I wish I could convince my > company to buy a beast like that. My current design takes about 45 > minutes for the PAR, on a 3.0 GHz Core 2 Duo. > > -Patrick Why?1? Your machine is already near the top of the heap. Even if it's the oldest 3 GHz Core 2 Duo (E6850, or X6800), it's only 10-20% slower than the top-of-the-line E8600 (3.33GHz.) Aside from the larger L2-cache (6MB vs 4MB) on the E8xxx series, you're not going to see the leapfrog improvement that the original-poster did -- the Pentium4 architecture suffered pretty badly when executing 'random-code' (compile-tasks.)Article: 135070
Hi I am new to ASIC prototyping approaches. I know it concept wise but want to know more about how popular is it among designers. In other words, is it a commonly taken path for verification or is more of a concpet than having practical applictaions. I also want to know if there are any tools specifically designed for ASIC prototyping and how mature they are about the hanlding of issues that will come up during the interfaces of different FPGA on boards. -- Edwin GobainArticle: 135071
lordsathish wrote:
> Hi all....
> Can Soft microprocessor like microblaze, nios replace DSP
> processors...?
Yes they can, espacially those SoftCore-CPUs, which can easily be
extended in their instruction set, can quite well immitate an DSPs
behaviour.
Depending on the project You are working on also the possibility of
extending the ppc-instruction set of the V4FX and (even more powerful)
V5FXT might be a good alternative (especially as the V{4,5}FX[T]'s PPCs
provide more general purpose processing power than SoftCores, but also
provide a useful interface for adding own accelerating instructions for
DSP-like tasks).
Regards,
Lorenz
Article: 135072<edwin.gobain@gmail.com> wrote in message news:60b74245-542b-4eb5-a859-aa74e152179f@s28g2000prd.googlegroups.com... > Hi > > I am new to ASIC prototyping approaches. I know it concept wise but > want to know more about how popular is it among designers. A Dataquest survey from 2005 showed that 40% of all ASIC's are prototyped on FPGA's. However, given the current cost and size of modern FPGA's I wouldn't be surprised if that number is now doubled. > In other > words, is it a commonly taken path for verification or is more of a > concpet than having practical applictaions. > > I also want to know if there are any tools specifically designed for > ASIC prototyping and how mature they are about the hanlding of issues > that will come up during the interfaces of different FPGA on boards. You need a synthesis tool that can handle an ASIC netlist (gated clocks, Synopsys Design Constraint, Designware support) examples are Mentor's Precision and Synplicity's Synplify. You also need a partitioner that can map your large synthesised netlist onto multiple FPGA's. Examples are ACE from Auspy, Chipit Manager from Prodesign, Certify from Synplicity). To get more info check out the top 3 (?) prototyping vendors Hardi, Prodesign and Dini. http://www.uchipit.com/ce/index.htm http://www.dinigroup.com/DN5000k10.php http://www.synplicity.com/products/haps/ Hans www.ht-lab.com > > -- > Edwin GobainArticle: 135073
On Sep 13, 12:32=A0am, "arko" <a...@winnet.com> wrote: > > Wow, that's quite an impressive speed-up. I wish I could convince my > > company to buy a beast like that. My current design takes about 45 > > minutes for the PAR, on a 3.0 GHz Core 2 Duo. > > > -Patrick > > Why?1? =A0Your machine is already near the top of the heap. > > Even if it's the oldest 3 GHz Core 2 Duo (E6850, or X6800), it's > only 10-20% slower than the top-of-the-line E8600 (3.33GHz.) > > Aside from the larger L2-cache (6MB vs 4MB) on the E8xxx > series, you're not going to see the leapfrog improvement that > the original-poster did -- the Pentium4 architecture suffered > pretty badly when executing 'random-code' (compile-tasks.) You're probably right. I can't really complain, after many years I finally was able to convince them that FPGA design really is computer intensive and requires a powerful machine (this was already known for mechanical CAD but FPGA design is new at my company). I got my current computer about a year ago and I got the most powerful processor back then. I wish I could get a 3X speed-up but that's probably many years away, unless the PAR process starts taking advantage of multi-CPU cores. KJ is right however that more simulation should be done upfront instead of many build cycles. -PatrickArticle: 135074
On Sep 12, 10:54=A0am, wallge <wal...@gmail.com> wrote: > On Sep 12, 10:02=A0am, sky46...@trline4.org wrote: > > > > > >Here are the system specs for old machine: > > >2 Intel Xeon CPU model 4, stepping 3 at 3.2 GHz > > >4GB DDR PC2700 > > >FSB speed 800 MHz. > > >The motherboard is a =A0Supermicro X6DAT-G > > >Here are the system specs for the new machine: > > >Intel Core2 Extreme CPU QX9770 @3.2 GHz (quad core) > > >OCZ Platinum 4GB (2 x 2GB) 240-Pin DDR3 SDRAM DDR3 2000 (PC3 16000) > > >Dual Channel > > >FSB speed 1600 MHz. > > >The motherboard is a =A0ASUS P5E3 PREMIUM/WIFI-AP @n LGA 775 > > > Computer "old": > > =A0 3.2 GHz =A0 =A0 =A0 =A0 2 MB cache > > =A0 =A02700 MB/s > > =A0 FSB 800 MHz > > =A0 Processing time: 33 minutes > > > Computer "new": > > =A0 3.2 GHz =A0 =A0 =A0 =A0 2x6 MB L2 > > =A0 16000 MB/s =A0 =A0 dual channel =3D> 25600 MB/s > > =A0 FSB 1600 MHz > > =A0 Processing time: 12 minutes > > > Considering the data I think that mainly the onchip cache is responsibl= e and > > the fact that the cpu<->memory bandwidth is increased by a factor of 3.= 2x > > > The current software doesn't give any advantage of having multiple cpus= asfaik. > > > I think you could possible improve the speed by getting a cpu with even= larger > > onchip cache. And maybe 1 GHz faster clock. An more efficient OS can al= so help. > > Apparently (I think I actually read it on comp.arch.fpga from an > Altera Rep.) using additional CPUs adds > a 10~15% speedup in Quartus.I guess Altera is gradually parallelizing > both synthesis and P&R > algorithms. > > On a separate note, the machine only cost me ~ $2700 to build. > The most expensive part was the CPU at around $1500, and next was the > mother board > and memory both coming in at close to $400 as I recall. Most of the > other parts > (HDD, DVDR, Graphics card, case, CPU fan) were at or around $100. > I didn't spend lots on the GPU since it does not contribute to fast > compiles. > > Also the old machine ran windows XP, the new one runs Vista (I had a > free upgrade to it). > We don't run linux because the licenses are more expensive and because > our other tools > are windows based. There are any number of reports that Vista will make your software run significantly slower than XP... or better yet, Win2k. If you could manage it, I would love to see this measured for FPGA work. Rick
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