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Messages from 136525

Article: 136525
Subject: Announce: HSMC General Purpose Interface Board for Altera Dev kits
From: "Nial Stewart" <nial*REMOVE_THIS*@nialstewartdevelopments.co.uk>
Date: Thu, 20 Nov 2008 11:25:35 -0000
Links: << >>  << T >>  << A >>
Fellow Altera Dev kit users and other interested parties....

Due to the lack of useful IO on the CycloneIII Starter kit we have
we have developed a general purpose expansion board for Altera's
new HSMC connector.

This provides...

8 * 10 bit ADC Inputs
8 * 10 bit DAC Outputs
2 * General Purpose 8 bit Digital IO ports
3 * RS232 Interfaces
2 * RS484 Interfaces
3 * One Wire Interfaces (2 of these can be combined for 5V I2C communications, all 3 can be used as 
jumper selection inputs)
Micro SD card socket (SPI lines connected)
Header for an FTDI Vinculum VDIP1 or pin compatible NSD FT245R USB slave board, this can also be 
used as a 16 bit general purpose digital IO header.
8 * LEDs
2 * SPI Interfaces

The SPI headers allow functionality such as the following to be easily added ...
LCD Screen
Zigbee Interface
GPS Interface
CAN Interface
LIN Interface
EEPROM memory
Stepper motor control.


Further details here...

http://www.nialstewartdevelopments.co.uk/products.htm

The board has only been tested on the CIII starter kit but should be compatible
with any eval board with an HSMC connector, I'm trying to get my hands on a
Stratix dev kit to test it.

I'll be updating the user guide and posting the example application in the next
week or so.

I'll also post an example Excel spreadsheet with VBA driving the serial or USB
interface so anyone with Excel should be able to drive it.

Constructive comments and feedback are welcome.


Nial


----------------------------------------------------------
Nial Stewart Developments Ltd        Tel: +44 131 516 8883
32/12 Hardengreen Business Park      Fax: +44 131 663 8771
Dalkeith, Midlothian
EH22 3NX
www.nialstewartdevelopments.co.uk



Article: 136526
Subject: Re: Spartan3 SRL16 + SliceFF, LUT stability
From: "Jan Bruns" <testzugang_janbruns@arcor.de>
Date: Thu, 20 Nov 2008 12:48:07 +0100
Links: << >>  << T >>  << A >>

"Gabor":
> "Jan Bruns"
>> "Gabor":

>> > Your original code with only non-blocking assignments in the
>> > clocked block is easier to fit because there is no combinatorial
>> > logic implied after the clock.
>>
>> I think the non-blocking version would ideally sample data exactly
>> when it per definition changes, effectively making no choice about
>> the data sampled beeing the older or the newer version.


> Non-blocking assignment is designed specifically to PREVENT
> this behavior.  i.e.  if all of your clocked processes use
> non-blocking assigns, then none of your values will be sampled
> after they change.  The clock edge forces all of the evaluations
> to occur, and then a delta later (0 real time, but sequentially
> for simulation) all of the assignments are performed.  So by
> all means use non-blocking assignments in clocked blocks to
> model actual flip-flop behavior when you don't want to REQUIRE
> hold time in the simulation model.


True. However, assume that the actual hardware implementation is clocked
faster than the right-hand side of the assignment can be calculated.

Then, the implementation still does what defined in verilog:
The right-hand side term is still calculated as fast as actually possible,
and the register is still loaded on the specified event.

In some situations, this might still lead to a fully functional design.
Also, there might be external logic having inputs synchroneous to
the clock, but out of control of the synthesis tool.

>> I wouldn't expect it to produce "@clk(SRL+FF) within a slice" for
>> any of the two blocking versions, if none of the blocking versions
>> could be implmented that way.

> Except that your first blocking version was essentially the same
> as the non-blocking because there were no sequential assignments
> to data which changed during one pass through the block.  You
> can confirm this with a simulator.

From my point of view, the difference is that the blocking version 
explicitly defined what to implement, whereas the non-blocking
version only implied contraints derived from practical requirements.

I agree in that a synthesis tool should collect all clocked assignments,
and automatically build constraints to decide about blocking behaviour
(specially a synthesis tool that forced users to write non-blocking 
assignments where they wished blocking should do that). So you're right 
in that my own opinion is, that both versions should be the same.

However, this is an additional opinion of lower priority, given that
we have a synthesis tool that is far away from supporting any weird
possible verilog construct.
But thanks for making your point of view clear.

Gruss

Jan Bruns





Article: 136527
Subject: Re: [SOLVED]Digilent Spartan3e starter kit, Not working.
From: laserbeak43 <laserbeak43@gmail.com>
Date: Thu, 20 Nov 2008 04:10:55 -0800 (PST)
Links: << >>  << T >>  << A >>
!!!!!!!!!!!!!!!
i was about to reply to everyone just to say that i've tried every
step mentioned when after re-reading most of the thread and getting to
Michael Brown's reply, I see that jumper 7 is open!!. looking at the
board and schems and pictures for days, i didn't notice this!!. fired
up ISE and it worked!!. I guess pictures aren't enough sometimes. you
need a list!!
thanks everybody and thanks to you Michael!!

Article: 136528
Subject: Re: how to implement an application with external memory in ISE?
From: Brian Drummond <brian_drummond@btconnect.com>
Date: Thu, 20 Nov 2008 14:46:01 +0000
Links: << >>  << T >>  << A >>
On Wed, 19 Nov 2008 18:27:24 -0800 (PST), KJ <lkjrsy@gmail.com> wrote:

>On Nov 19, 5:29 am, Enes Erdin <eneser...@gmail.com> wrote:
>> On 18 Kasým, 18:37, KJ <lkj...@gmail.com> wrote:
>>
>> > Hi everyone.
>>
>> > For shortage of memory in FPGA, I need an exteranl memory.
>> > In this case, is it possible to implement my application in ISE?
>>
>> > I means how to initiate the external memory in ISE tool.
>> > If possible, I want to do simulation in PC without configuring it to
>> > real board.
>>
>> You can download simulation models for the ram that you will use.
>> Afterwards you should write a controller for it and you can use the
>> model in your testbench.
>
>Thanks for reply. I'm wondering where to download the simulation
>models for the ram?

From the RAM manufacturer.
For example, www.cypress.com or www.micron.com

- Brian


Article: 136529
Subject: Re: Spartan3 SRL16 + SliceFF, LUT stability
From: John_H <newsgroup@johnhandwork.com>
Date: Thu, 20 Nov 2008 09:54:17 -0800 (PST)
Links: << >>  << T >>  << A >>
Jan Bruns wrote:
> "Jan Bruns":
> > I am using that module to implement a byte-stream buffer. Using
> > an up/down-counter, I can store 0..16 bytes in just 2 Spartan3 CLBs,
> > allowing 2-sided, fully sequential access (and avoiding the need for
> > doubled SliceM consumption for DualPort distributed ram).
> > It was a bit long-winded to make xst use the SliceL carry chain
> > for the counter, so with my posting here, I intended to minimize
> > things to think about, just in case some kind of debug should become
> > necessary.
>
> Here's the design file. Maybe someone is interested in and(or may find bugs
> (I haven't yet tested it at all, so I'm almost sure there's something
> that doesn't already work als expected):
>
<snip>

I'm a little confused about what I see.  The blocking operators
suggest software.  The RLOCs and MAPs suggest you're trying to design
each transistor.

What is your end goal?  If you're going for absolute top-end
frequency, there may be benefit to the extreme placement control but
for almost all cases, the tool should be able to provide most of what
you need.

Do you want your shift register output the clock after "a" or the same
cycle?

- John_H

Article: 136530
Subject: Re: Spartan3 SRL16 + SliceFF, LUT stability
From: "Jan Bruns" <testzugang_janbruns@arcor.de>
Date: Thu, 20 Nov 2008 21:46:44 +0100
Links: << >>  << T >>  << A >>

"John_H":

>> Here's the design file. Maybe someone is interested in and(or may find bugs
>> (I haven't yet tested it at all, so I'm almost sure there's something
>> that doesn't already work als expected):

> I'm a little confused about what I see.  The blocking operators
> suggest software.  The RLOCs and MAPs suggest you're trying to design
> each transistor.
 
> What is your end goal?  If you're going for absolute top-end
> frequency, there may be benefit to the extreme placement control but
> for almost all cases, the tool should be able to provide most of what
> you need.

I plan to use many (some ten, or maybe even a hundred) instances of this module,
so I want it to be as area-optimized as possible. The controller module
really looks complicated, but I didn't manage to make xst produce what
I wanted to see in the FPGA-Editor. It always automatically gernerated 
12,16 or even more slices. Manually building the carry chain was
the only way I found to fit the 16 Byte buffer into 2 CLBs (8 slices). 
 
> Do you want your shift register output the clock after "a" or the same
> cycle?

Hm. Say we're starting with an empty buffer (a=1111). 
This means, "down" isn't allowed to be high on clk.

If the senderside signals "up=true" on clk, 
"a" should become "0000", and "empty" become false.

Now that "empty=false", the receiver may request a data-item
by setting "down=true", and will should see the data shortly 
after clk.

Gruss

Jan Bruns

Article: 136531
Subject: Re: vga interfacing for image display
From: Tommy Thorn <tommy.thorn@gmail.com>
Date: Thu, 20 Nov 2008 14:17:53 -0800 (PST)
Links: << >>  << T >>  << A >>
On Nov 19, 2:31=A0pm, Glen Herrmannsfeldt <g...@ugcs.caltech.edu> wrote:
> Mark McDougall wrote:
> > Glen Herrmannsfeldt wrote:
> >>Not the only option, but it is the best one.
> > I've also heard of using PWM output on the RGB
> > lines to produce more colours...
>
> That is pretty much what my second suggestion was, though
> with only three widths. =A0(0, 0.5, 1.0)
>
> If you have a fast enough clock, you can generate more
> different widths.

The PWM option has been discussed before on other threads, but
apparently it doesn't work well with modern LCD panels. The best
option remains a soldering iron, or buying a board that has the
support. (The Altera based kit I use has 10-bits pr color channel).

Tommy

Article: 136532
Subject: Re: vga interfacing for image display
From: Glen Herrmannsfeldt <gah@ugcs.caltech.edu>
Date: Thu, 20 Nov 2008 15:33:16 -0700
Links: << >>  << T >>  << A >>
Tommy Thorn wrote:
> On Nov 19, 2:31 pm, Glen Herrmannsfeldt <g...@ugcs.caltech.edu> wrote:
>>Mark McDougall wrote:
>>>Glen Herrmannsfeldt wrote:

>>>>Not the only option, but it is the best one.

>>>I've also heard of using PWM output on the RGB
>>>lines to produce more colours...

>>If you have a fast enough clock, you can generate more
>>different widths.

> The PWM option has been discussed before on other threads, but
> apparently it doesn't work well with modern LCD panels. The best
> option remains a soldering iron, or buying a board that has the
> support. (The Altera based kit I use has 10-bits pr color channel).

Depending on how fast you do it and various stray
capacitances the signal will look pretty much like a normal
signal by the time it gets to the display.

It might be that LCD panels try to lock onto the bit clock,
which will be a little harder, and some patterns might
confuse the phase lock circuit.

-- glen


Article: 136533
Subject: Re: Altera DE3 - USB Bulk Transfer
From: Mark McDougall <markm@vl.com.au>
Date: Fri, 21 Nov 2008 12:01:39 +1100
Links: << >>  << T >>  << A >>
Guy_FPGA wrote:

> Do you know how to create a windows GUI project that
> communicate with the USB?... I couldn't compile the rwbulk from DDK in
> windows I needed the special make file of DDK and the special BUILD
> that comes with the DDK as well.

Can't help you with your NIOS-II transfer problems but I have written GUI
USB transfer software. IIRC it was actually HID-based, but I have also
played with the console-mode bulk transfer sample in the DDK as well.

The problem is that the DDK contains headers and (IIRC) libraries that
aren't available with the standard visual studio distro. Even for the HID
stuff, I had to use headers and link against some DDK library(ies?) under
Visual C/C++. I'm sure you could manage the same with your bulk transfer
stuff?!?

Regards,

-- 
Mark McDougall, Engineer
Virtual Logic Pty Ltd, <http://www.vl.com.au>
21-25 King St, Rockdale, 2216
Ph: +612-9599-3255 Fax: +612-9599-3266

Article: 136534
Subject: how to display on LCD of FPGA board?
From: "500milesaway" <500milesaway@gmail.com>
Date: Thu, 20 Nov 2008 21:57:24 -0600
Links: << >>  << T >>  << A >>
Hello
Good Day.

I want to display a bit-stream (for example: 01001101) in the LCD of
Xilinx® Virtex™-4 LX MB Development Kit. Can anyone tell me how can I get
example VHDL code to display bits on LCD?

Best regards and thanks in advance

pantho

Article: 136535
Subject: Picochip Wimax designs available to public?
From: mentari <StephanusR@gmail.com>
Date: Thu, 20 Nov 2008 22:13:28 -0800 (PST)
Links: << >>  << T >>  << A >>
South Africa's has a banana republic legal system, it is one of the
few countries in the world where a telecoms regulator like the FCC
doesn't have the powers to fine only our prosecutors and courts can do
this. The NPA from SA fully supports the illegal deployment of wimax
on illegal frequencies but can't openly state so.  See
http://scratchpad.wikia.com/wiki/Sasecurity

Now my question is why can't I just get hold of these design tools
such as by http://www.picochip.com - are Vodacom bribing Picochip so
that they don't sell these design tools to the general public in South
AFrica?  Thus the only root to seems to be FPGA which has a very long
design cycle, is more expensive that a Tileramulticore and DSP based
Picochip sollution. Any ideas on what to do?

Picochip
"... Femtocells-in-a-box enable rapid development and testing
picoChip is offering a number of kitted demo or "femtocell-in-a-box"
products that enable OEMs, operators, research laboratories and
software vendors to develop and test WiMAX, WCDMA and TD-SCDMA
products. Available as laboratory standard products in ruggedized
metal chassis, or as configurable demo kits, they integrate baseband
software, demonstration radio, gateway and core network functionality,
terminals, PC-based software and Linux board support packages...."

Article: 136536
Subject: Re: Student FPGAs
From: Andreas Ehliar <ehliar-nospam@isy.liu.se>
Date: Fri, 21 Nov 2008 13:58:35 +0000 (UTC)
Links: << >>  << T >>  << A >>
On 2008-11-21, Philipp <Philipp@gmx.at> wrote:
> Hi
>
> I am just wondering if there are any other companies out there that 
> provide like Xilinx a univerity programm where a student can get a board
> for free or for very low cost? Especially a Virtex V board would be 
> interesting to explore.

Digilent Inc has some quite cheap FPGA boards. (Although the Virtex 5
board is $750 with university program pricing, not sure if you would
consider that cheap or not...)

/Andreas

Article: 136537
Subject: Re: how to display on LCD of FPGA board?
From: Bryan <bryan.fletcher@avnet.com>
Date: Fri, 21 Nov 2008 07:52:46 -0800 (PST)
Links: << >>  << T >>  << A >>
pantho,

Go to www.em.avnet.com/virtex4lx-sx-mb-dev then click on Support Files
& Downloads.  Select one of the 10.1 Interrupt Examples (for example,
V4MB LX25 Rev1 Interrupt Example Design).  This is a MicroBlaze design
that uses the LCD.  If you are only interested in the underlying code,
then dig down into the project's /pcore directory.

Bryan


On Nov 20, 8:57=A0pm, "500milesaway" <500milesa...@gmail.com> wrote:
> Hello
> Good Day.
>
> I want to display a bit-stream (for example: 01001101) in the LCD of
> Xilinx=AE Virtex=99-4 LX MB Development Kit. Can anyone tell me how can I=
 get
> example VHDL code to display bits on LCD?
>
> Best regards and thanks in advance
>
> pantho


Article: 136538
Subject: Student FPGAs
From: Philipp <Philipp@gmx.at>
Date: Fri, 21 Nov 2008 16:05:47 +0000
Links: << >>  << T >>  << A >>
Hi

I am just wondering if there are any other companies out there that 
provide like Xilinx a univerity programm where a student can get a board
for free or for very low cost? Especially a Virtex V board would be 
interesting to explore.

Cheers,
Philipp

Article: 136539
Subject: Re: Announce: HSMC General Purpose Interface Board for Altera Dev
From: nial@nialstewartdevelopments.co.uk
Date: Fri, 21 Nov 2008 08:06:13 -0800 (PST)
Links: << >>  << T >>  << A >>
On 20 Nov, 11:25, "Nial Stewart"
<nial*REMOVE_TH...@nialstewartdevelopments.co.uk> wrote:
> Fellow Altera Dev kit users and other interested parties....
>
> Due to the lack of useful IO on the CycloneIII Starter kit we have
> we have developed a general purpose expansion board for Altera's
> new HSMC connector.
>
> Further details here...
>
> http://www.nialstewartdevelopments.co.uk/products.htm


I know it's bad form to reply to yourself but I've just realised the
link to the User Guide
for the board was incorrect, I've fixed this now.


Nial.

Article: 136540
Subject: Altera FPGA development board for high speed Video processing
From: "rush2sami" <rush2sami@yahoo.com>
Date: Fri, 21 Nov 2008 10:41:14 -0600
Links: << >>  << T >>  << A >>
Hi Guys,
I am looking for an Altera FPGA development board for high speed Video
processing/Live video streaming/high speed data transfer to CPU with  min
300MBps  using PCI/PCI-Express . The FPGA should be from Altera. .Please
let me know the right Altera development board for my Implemetation.

Regards,
Swaminathan



Article: 136541
Subject: Xilinx Spartan Logic Cell/Slice vs. Xilinx CPLD Macrocell
From: "Eric" <ca9@gmx.de>
Date: Fri, 21 Nov 2008 10:41:24 -0600
Links: << >>  << T >>  << A >>
Hello all,

knowing that one Spartan-3-FPGA-Slice stands for 2.25 Logic Cells, how can
I convert this into a Xilinx CPLD Macrocell? 

Example: Using an i2c-module with 150 Slices in a Spartan-3, which CPLD
Device (number of Macrocells) would be sufficient?
Haven't found any reference at xilinx or google.

Thanks for any feedback,
Richard



Article: 136542
Subject: Re: Student FPGAs
From: Mike Treseler <mtreseler@gmail.com>
Date: Fri, 21 Nov 2008 09:29:52 -0800
Links: << >>  << T >>  << A >>
Philipp wrote:

> I am just wondering if there are any other companies out there that
> provide like Xilinx a univerity programm where a student can get a board
> for free or for very low cost? Especially a Virtex V board would be
> interesting to explore.

Unlikely.
That's a thousand dollar bill at least.
If you are interested in learning,
download some vendor tools and
university lectures and get busy.

         -- Mike Treseler


Article: 136543
Subject: Re: Xilinx Spartan Logic Cell/Slice vs. Xilinx CPLD Macrocell
From: "HT-Lab" <hans64@ht-lab.com>
Date: Fri, 21 Nov 2008 17:32:32 -0000
Links: << >>  << T >>  << A >>

"Eric" <ca9@gmx.de> wrote in message 
news:LeCdnY3PC6QpebvUnZ2dnUVZ_uidnZ2d@giganews.com...
> Hello all,
>
> knowing that one Spartan-3-FPGA-Slice stands for 2.25 Logic Cells, how can
> I convert this into a Xilinx CPLD Macrocell?
>
> Example: Using an i2c-module with 150 Slices in a Spartan-3, which CPLD
> Device (number of Macrocells) would be sufficient?
> Haven't found any reference at xilinx or google.
>
> Thanks for any feedback,
> Richard
>
I assume you don't have access to the i2c RTL, so in that case I would 
download a number of RTL designs from the web and synthesise for both types. 
You can then use the area results to work out a rough conversion factor.

Hans
www.ht-lab.com



Article: 136544
Subject: Re: Student FPGAs
From: Rob Gaddi <rgaddi@technologyhighland.com>
Date: Fri, 21 Nov 2008 09:38:15 -0800
Links: << >>  << T >>  << A >>
On Fri, 21 Nov 2008 16:05:47 +0000
Philipp <Philipp@gmx.at> wrote:

> Hi
> 
> I am just wondering if there are any other companies out there that 
> provide like Xilinx a univerity programm where a student can get a
> board for free or for very low cost? Especially a Virtex V board
> would be interesting to explore.
> 
> Cheers,
> Philipp

The AvNet $39 Spartan 3A board (mentioned also in another thread right
now), is really tough to beat bang for the buck wise.

-- 
Rob Gaddi, Highland Technology
Email address is currently out of order

Article: 136545
Subject: Re: Student FPGAs
From: John_H <newsgroup@johnhandwork.com>
Date: Fri, 21 Nov 2008 09:39:01 -0800 (PST)
Links: << >>  << T >>  << A >>
Philipp wrote:
> Hi
>
> I am just wondering if there are any other companies out there that
> provide like Xilinx a univerity programm where a student can get a board
> for free or for very low cost? Especially a Virtex V board would be
> interesting to explore.
>
> Cheers,
> Philipp

I believe digilentinc.com has student pricing.  Working with Xilinx,
the devices are provided by Xilinx free of charge (if I recall
correctly) to help introduce the technology to students.

You might get better information on board vendors Xilinx works with in
this manner if you contact someone involved with the Xilinx University
Program.

Article: 136546
Subject: Re: Xilinx Spartan Logic Cell/Slice vs. Xilinx CPLD Macrocell
From: John_H <newsgroup@johnhandwork.com>
Date: Fri, 21 Nov 2008 09:45:40 -0800 (PST)
Links: << >>  << T >>  << A >>
Eric wrote:
> Hello all,
>
> knowing that one Spartan-3-FPGA-Slice stands for 2.25 Logic Cells, how can
> I convert this into a Xilinx CPLD Macrocell?
>
> Example: Using an i2c-module with 150 Slices in a Spartan-3, which CPLD
> Device (number of Macrocells) would be sufficient?
> Haven't found any reference at xilinx or google.
>
> Thanks for any feedback,
> Richard

A similar question might be that I know it takes 12 truck loads to
move my cargo from point A to B in the time I need but I can't find a
conversion for going by boat.

The nature of a LUT and a macrocell are rather different.  A design
optimized for one is probably not optimized for the other.  If you
synthesize your code to the target architecture, you'll get a better
estimate by easily a factor of 2 than trying to use a fudge factor.
You may also find code out there optimized for CPLDs.

Article: 136547
Subject: Re: Student FPGAs
From: "beky4kr@gmail.com" <beky4kr@gmail.com>
Date: Fri, 21 Nov 2008 11:18:51 -0800 (PST)
Links: << >>  << T >>  << A >>
On 21 =D7=A0=D7=95=D7=91=D7=9E=D7=91=D7=A8, 18:05, Philipp <Phil...@gmx.at>=
 wrote:
> Hi
>
> I am just wondering if there are any other companies out there that
> provide like Xilinx a univerity programm where a student can get a board
> for free or for very low cost? Especially a Virtex V board would be
> interesting to explore.
>
> Cheers,
> Philipp

If you like you may want to take a look at:
h--p://bknpk.no-ip.biz.
Some verilog and vhdl free projects as well as other nice stuff.

Article: 136548
Subject: Re: Xilinx Spartan Logic Cell/Slice vs. Xilinx CPLD Macrocell
From: Gabor <gabor@alacron.com>
Date: Fri, 21 Nov 2008 11:28:05 -0800 (PST)
Links: << >>  << T >>  << A >>
On Nov 21, 11:41=A0am, "Eric" <c...@gmx.de> wrote:
> Hello all,
>
> knowing that one Spartan-3-FPGA-Slice stands for 2.25 Logic Cells, how ca=
n
> I convert this into a Xilinx CPLD Macrocell?
>
> Example: Using an i2c-module with 150 Slices in a Spartan-3, which CPLD
> Device (number of Macrocells) would be sufficient?
> Haven't found any reference at xilinx or google.
>
> Thanks for any feedback,
> Richard

Usually a CPLD macrocell has more combinatorial logic per
flip-flop than a "logic element" from an FPGA.  So a rough way
to look at porting from FPGA to CPLD (macrocell-type, not
the "CPLD" that is really a small non-volatile FPGA like machXO)
is to count the flip-flops in the design and know that you
will need at least that many macrocells.

Remember to count LUTs used as RAM or shift-register as the
appropriate number of flip-flops (usually 16).

By the way 2.25 is an inflated marketing number.  2.0 is the number
of 4-input LUT's and flip-flops in the slice.

Article: 136549
Subject: Quartus error
From: FP <FPGA.unknown@gmail.com>
Date: Fri, 21 Nov 2008 11:56:50 -0800 (PST)
Links: << >>  << T >>  << A >>
Hello,

I am getting the following error in Quartus
Error (10054): Verilog HDL File I/O error at crc.v(26): can't open
Verilog Design File "../source/parameters.vh"

How do I resolve this error. This is a .vh file that the synthesizer
is complaining about.
Please help.



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