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On Dec 6, 5:22=A0am, LittleAlex <alex.lo...@email.com> wrote: > On Dec 4, 5:41 pm, Venkat <venkat.ja...@gmail.com> wrote: > > > Hello all, > > > Is there a way (even a rough approach) of finding an equivalent > > estimate of ASIC Gates for the design implemented in Xilinx FPGAs > > considering their definitions of Slices, DSPs and BRAMs? I know the > > approximate conversion ratio between ASIC and FPGA gates is 1:5, but > > way of identifying gates used in FPGA implementation is unknown > > (at least for the latest families to be implemented on ISE 10.1). > > > I am sure some of you would have had this practical experience and I > > will be glad if someone throws some light on my query. > > > Thanks in advance. > > > Venkat. > > Only one way that will give you usable numbers: =A0Send your files to > your ASIC vendor and ask "About how many gates does this synthesize > to?" Thank you all for the patient responses. It was very helpful to learn more on this. I personally did some analysis on the gate count equivalent by running varieties of designs on the Xilinx FPGA and would like to share the results here. 1 LUT approximates to 10 FPGA Gates 1 FF approximates to 4 FPGA Gates Usage of BRAM utilizes 16Kb RAM by default irrespective of the size of memory used and each bit of memory utilizes 4 FPGA Gates and hence if the in-built Block RAM is used, it ends up with 65,536 Gates. DSP resources are more tricky as they do not show up as added gates in the Post-Map Result in earlier ISE Versions. To make the multipliers using the Logic shows some idea of the gate count. A 16x16 Multiplier uses about 4000 Gates which is halved for a 12x12 multiplier. So the rough way to approximate the gate count is to use the FF, LUTs, BRAMs and DSPs as reference and work out the sum. Thanks again for the responses. Venkat.Article: 136826
On 2008-12-08, Venkat <venkat.japan@gmail.com> wrote: > 1 FF approximates to 4 FPGA Gates Have you considered the fact that a commercial ASIC would probably need some sort scan-chain that almost all flip-flops in the chip will be connected to? (For chip testing purposes.) If so, 4 gates sounds quite small for an estimate of the gate cost in an ASIC. > > Usage of BRAM utilizes 16Kb RAM by default irrespective of the size > of memory used and each bit of memory utilizes 4 FPGA Gates and > hence if the in-built Block RAM is used, it ends up with 65,536 Gates. I assume you are calculating the gate count to figure out the area cost. If so, does your calculation for these values consider the fact that the storage elements in a block-ram is usually very optimized when compared to normal flip-flops? /AndreasArticle: 136827
Hi all, I am working with a couple of different pre-built modules, and one of them expects to receive its data LSB first. I can't figure out for the life of me how to connect it to my other modules. That is to say: I need to connect x[7:0] to y[7:0] so that y[7] = x[0], y[6] = x[1], y [5] = x[2], etc. I need to do this for a few different 64-bit connections, so I would really like avoid manually doing each individual wire assignment. There must be some command in Verilog to select from low-to-high, but I can't figure it out for the life of me : ( Thanks in advance, NickArticle: 136828
NRClark wrote: > Hi all, > > I am working with a couple of different pre-built modules, and one of > them expects to receive its data LSB first. I can't figure out for the > life of me how to connect it to my other modules. > > That is to say: > > I need to connect x[7:0] to y[7:0] so that y[7] = x[0], y[6] = x[1], y > [5] = x[2], etc. I need to do this for a few different 64-bit > connections, so I would really like avoid manually doing each > individual wire assignment. There must be some command in Verilog to > select from low-to-high, but I can't figure it out for the life of me : > ( > Just do a for loop in Verilog. The synthesizer will expand the loop for you. -hpaArticle: 136829
Sebastien Bourdeauducq schrieb: > Hi, > >> If you use the Early Access Parial Reconfiguration (EAPR Flow), static >> signals can be routed through your reconfigurable area. The tools will take >> care that the static signal is included in ALL partial bitstreams. > > Thanks for the answer. But aren't the static signals routed through a > reconfigurable reguion going to be interrupted and/or glitched when > the area is reconfigured ? Or are the tools clever enough to see that > the signal was only going to the busmacro and therefore only affects > the reconfigurable region ? The statement from Xilinx is that for Virtex class of devices, reconfiguration does not produce glitches if the signal routing is overwritten by identical configuration data. (I hope that is allway correct ;-)) > > SebastienArticle: 136830
On Dec 7, 11:11=A0pm, Oscar <o.al...@gmail.com> wrote: > On Dec 6, 9:46=A0am, "freesp...@gmail.com" <freesp...@gmail.com> wrote: > > > > > On Dec 6, 8:27=A0pm, Glen Herrmannsfeldt <g...@ugcs.caltech.edu> wrote:= > freesp...@gmail.com wrote: > > > > (snip) > > > > > I get the following log: > > > > Found Device. =A0IDCODE: =A0f5046093 > > > > Found Device. =A0IDCODE: =A021c2e093 > > > > Found Device. =A0IDCODE: =A0invalid > > > > Found Device. =A0IDCODE: =A0invalid > > > > Found Device. =A0IDCODE: =A0invalid > > > > I don't have this board so I might be just guessing, > > > but is there any reason that Xilinx software should recognize > > > non-Xilinx devices? > > > Are you referring to IDs f5046093 and 21c2e093? Those appear to be > > Xilinx devices. I don't expect Xilinx to recognise non-Xilinx devices > > either, but that is not what is causing the invalid IDCODE messages: > > there are _only_ 2 devices on the board connected to the JTAG chain. > > My problem is there appears to be 29 other devices which aren't there, > > but is detected. This is causing Digilent's ExPort program to fail and > > thus preventing me from doing anything with the Nexys2. > > Its almost like something is broken in the JTAG interface. > IIRC, this can happen if the host fails to find the end of the IDCODE > register when doing an initialization scan. > It looks like it reads in an extra 29 devices (likely all 1's) and > then stops because of a software 'timeout' (a neat 31 devices in an > array); it then cant find the device description files for the > spurious 29, and tells you that. I seem to remember that the way it's > supposed to detect the end of the scan chain is the lack of a '1' as a > first bit in the n+1 IDCODE out. If TDO is stuck high after the two > first devices, youd get something very much like what you sre seeing. > > I'd try another JTAG scan tool to see what *that* reports. > > Of course, I could also be dead wrong and its due to something > entirely different. > > //Oscar Interesting, I will keep it in mind Oscar, thank you.Article: 136831
On Dec 8, 7:52=A0am, Sean Durkin <news_MO...@tuxroot.de> wrote: > freesp...@gmail.com wrote: > > there are _only_ 2 devices on the board connected to the JTAG chain. > > My problem is there appears to be 29 other devices which aren't there, > > but is detected. > > Have you tried setting a slower cable speed? I've had things like this > happened when I used a too fast clock for JTAG. You can set the speed in > the iMPACT cable settings. The default is rather high, there have been > times when it wouldn't work unless I selected a slower speed. > > HTH, > Sean I will ask the Digilent people. I have to use their ExPort program to communicate with my Nexys2 since it uses some usb-jtag magic. I might just by the Xilinx cable though if this continues to be a problem. Thank you for your advice.Article: 136832
On Sun, 7 Dec 2008 18:15:36 -0800 (PST), NRClark
<nicholas.clark@gmail.com> wrote:
>Hi all,
>
>I am working with a couple of different pre-built modules, and one of
>them expects to receive its data LSB first. I can't figure out for the
>life of me how to connect it to my other modules.
>
>That is to say:
>
>I need to connect x[7:0] to y[7:0] so that y[7] = x[0], y[6] = x[1], y
>[5] = x[2], etc. I need to do this for a few different 64-bit
>connections, so I would really like avoid manually doing each
>individual wire assignment. There must be some command in Verilog to
>select from low-to-high, but I can't figure it out for the life of me :
There isn't in traditional Verilog; you simply can't select
a slice (part-select) of a vector in the "wrong" direction.
SystemVerilog has its "streaming operators", which can do the
job easily:
reg [63:0] forward, reverse;
...
reverse = {<<{forward}};
but synthesis tool support for them is [searches desperately
for polite word] patchy.
As someone else said, you need to write a 'for' loop that will
unroll in synthesis. But if you need to do it several times,
consider writing a function to do it:
function [63:0] reverse (input [63:0] forward);
integer i;
for (i=0; i<=63; i=i+1)
reverse[63-i] = forward[i];
endfunction
Or you could write the same code as a module, which
can be parameterized for bit width, and then you have a
general-purpose reverse-any-vector block:
module endianness_swapper
#(parameter width = 64)
(input [width-1:0] forward, output reg [width-1:0] reverse);
always @(forward) begin: swapper
integer i;
for (i=0; i<width; i=i+1)
reverse[(width-1)-i] = forward[i];
end
endmodule
Note that this will not work for bidirectional (inout) ports of
your wrong-endian module. For simulation that could be solved
by writing a generate loop instancing a bunch of "tran" primitives,
but that won't work for synthesis. I'm not quite sure what the
best way would be to handle that - probably, reverse the bus values
at a point in the code where they are not bidirectional, so that
you don't need to solve the harder problem.
--
Jonathan Bromley, Consultant
DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services
Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com
The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
Article: 136833Hi there, I'm wondering whether it's possible to put both an encrypted design and an unencrypted design into the same FPGA device (Virtex 5), and they should work together side by side and interact with each other .Article: 136834
Mike Treseler wrote: > Nemesis wrote: > >> Of course the process is synthesizable with ise8.2. > > Except for the fact that the OS crashes. It's not the OS, it's ISE. And now it doesn't crash anymore, but it refuses to open the projects. It is like ISE damaged itself. > >> I should investigate but I >> have little time, right now the better solution is to bring ise8.2 back to >> work. > > It may take a little time. > I would make new projects for each submodule, > until I found the bad source. > > Next time I would write my own code. OK, but I use IP cores for FFT, FIFO, Dual Port Memory, it would require a loooot of time for me to write code for such things > Good luck. Thanks. I think I'm going to format and reinstall everything ... it's a shame that Xilinx software is so unstable and unpredictable. -- Know how to listen, and you will profit even from those who talk badly. _ _ _ | \| |___ _ __ ___ __(_)___ | .` / -_) ' \/ -_|_-< (_-< |_|\_\___|_|_|_\___/__/_/__/ http://xpn.altervista.orgArticle: 136835
<xiaoling.li@fme.fujitsu.com> wrote in message news:87f6c423-ccbf-4f46-82bd-732353e532ab@v38g2000yqb.googlegroups.com... > Hi there, > I'm wondering whether it's possible to put both an encrypted design > and an unencrypted design into the same FPGA device (Virtex 5), and > they should work together side by side and interact with each other . Have a look in Virtex-5 Configuration Guide (section 'Loading encrypted bitstream'). It is possible, but encrypted bitstream has to be loaded first and configure entire device. Then, you can use Partial Reconfiguration (PR) flow and ICAP to add unencrypted sub-designs afterwards. In this scenario, beside playing with busmacros, you have to implemet some on-line verification procedures that would enforce spatial isolation betwen the designs. Otherwise your encryption would be pointless... Some references: 1) Huffmire, T.; Brotherton, B.; Wang, G.; Sherwood, T.; Kastner, R.; Levin, T.; Nguyen, T. & Irvine, C.; Moats and drawbridges: An isolation primitive for reconfigurable hardware based systems IEEE Symposium on Security and Privacy, 2007 2) McLean, M.; Moore, J.; FPGA-based single chip cryptographic solution, Military Embedded Systems, 2007 3) Drimer, S.; Moore, J.; Lesea, A;Circuit for and method of implementing a plurality of circuits on a programmable logic device, US Patent no.7408381, issued 8/2008 (filed 2/2006), 2006 Regards, KrzysztofArticle: 136836
Not sure if it's what you are looking for, but Avnet has an XIIC
example with interrupts connected to a TI Temp Sensor.
www.em.avnet.com/spartan3a-evl --> Support Files & Downloads -->
MicroBlaze IIC Temperature Sensor
Bryan
On Dec 6, 8:06=A0am, simax <opitz.fr...@googlemail.com> wrote:
> Hello everybody ...
>
> Im trying to code an isr for the xiic Ip from Xilinx EDK.
> I did everything like tht documentation says but it wont work.
>
> i get an interrupt when the modul is adressed as slave and its the AAS
> irq.
> After i get it, ill reset the interrupt that it is acknowledged but it
> wont work ..
>
> thats how my isr looks like ...
>
> void iic_1_handler(void * baseaddr_p) {
>
> =A0XGpio_mSetDataReg(XPAR_LEDS_8BIT_BASEADDR, XGPIO_IR_CH1_MASK, 0x03);
>
> =A0 =A0if(XIIC_READ_IISR(XPAR_XPS_IIC_1_BASEADDR) & XIIC_INTR_AAS_MASK){
> =A0 =A0 =A0XIIC_GINTR_DISABLE(XPAR_XPS_IIC_1_BASEADDR);
> =A0 =A0 =A0XIic_mWriteReg
> (XPAR_XPS_IIC_1_BASEADDR,XIIC_IIER_OFFSET,XIIC_READ_IISR
> (XPAR_XPS_IIC_1_BASEADDR));
> =A0 =A0 =A0XIIC_GINTR_ENABLE(XPAR_XPS_IIC_1_BASEADDR);
> =A0 =A0 =A0XGpio_mSetDataReg(XPAR_LEDS_8BIT_BASEADDR, XGPIO_IR_CH1_MASK,
> XIIC_READ_IISR(XPAR_XPS_IIC_1_BASEADDR));
>
> =A0 =A0}
>
> }
>
> does anyone have an working controll flow?
>
> thx for help
Article: 136837> Mike Treseler wrote: >> I would make new projects for each submodule, >> until I found the bad source. >> Next time I would write my own code. Nemesis wrote: > OK, but I use IP cores for FFT, FIFO, Dual Port Memory, it would require a > loooot of time for me to write code for such things For the purposes of debugging, you can can make separate projects for each submodule without rewriting anything but ports and instances. One of your input files is killing ise. Find it. Divide and conquer. -- Mike TreselerArticle: 136838
On Dec 8, 5:56=A0am, Nemesis <neme...@nowhere.invalid> wrote: > Mike Treseler wrote: > > Nemesis wrote: > > It may take a little time. > > I would make new projects for each submodule, > > until I found the bad source. > > > Next time I would write my own code. > > OK, but I use IP cores for FFT, FIFO, Dual Port Memory, it would require = a > loooot of time for me to write code for such things See, if you write those cores yourself, you won't get boned every time Xilinx updates their tools and breaks their old code. > I think I'm going to format and reinstall everything ... it's a shame tha= t > Xilinx software is so unstable and unpredictable. You must be new to xilinx. -aArticle: 136839
Andy Peters wrote: >> I think I'm going to format and reinstall everything ... it's a shame that >> Xilinx software is so unstable and unpredictable. > You must be new to xilinx. I've been using xilinx tools for 4 years, but I'm still amused by the low quality of their software. -- A jury consists of twelve persons chosen to decide who has the better lawyer. _ _ _ | \| |___ _ __ ___ __(_)___ | .` / -_) ' \/ -_|_-< (_-< |_|\_\___|_|_|_\___/__/_/__/ http://xpn.altervista.orgArticle: 136840
Mike Treseler wrote: > Nemesis wrote: >> OK, but I use IP cores for FFT, FIFO, Dual Port Memory, it would require a >> loooot of time for me to write code for such things > > For the purposes of debugging, > you can can make separate projects > for each submodule without rewriting anything > but ports and instances. > > One of your input files is killing ise. > Find it. > Divide and conquer. .... Are you talking about the ISE8.2 problem or ISE10.1 problem? With all these problems I'm a little confused :-) I used this source files with ISE8.2 until it decided to commit suicide, so they should be good. -- Some memories are best forgotten _ _ _ | \| |___ _ __ ___ __(_)___ | .` / -_) ' \/ -_|_-< (_-< |_|\_\___|_|_|_\___/__/_/__/ http://xpn.altervista.orgArticle: 136841
On Dec 8, 2:02=A0pm, Nemesis <neme...@nowhere.invalid> wrote: > Mike Treseler wrote: > > Nemesis wrote: > >> OK, but I use IP cores for FFT, FIFO, Dual Port Memory, it would requi= re a > >> loooot of time for me to write code for such things > > > For the purposes of debugging, > > you can can make separate projects > > for each submodule without rewriting anything > > but ports and instances. > > > One of your input files is killing ise. > > Find it. > > Divide and conquer. > > .... Are you talking about the ISE8.2 problem or ISE10.1 problem? > With all these problems I'm a little confused :-) > > I used this source files with ISE8.2 until it decided to commit suicide, = so > they should be good. > -- > Some memories are best forgotten > =A0_ =A0_ =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0_ > | \| |___ _ __ =A0___ __(_)___ > | .` / -_) ' =A0\/ -_|_-< (_-< > |_|\_\___|_|_|_\___/__/_/__/http://xpn.altervista.org It sounds like Mike means the 10.1 problems. It would be good to have your project synthesizable in the better tool version. Maybe you can try 10.1 again and post some of the error messages here... By the way, I've been using Xilinx tools for a very long time, and I think the real shoddy software start at the release of version 7. In my opinion it continued on a downward spiral through 9.2 and now it's getting a bit better again. I still have version 6.1i which I use for any device old enough to be supported by it. It rarely crashes and the project file is editable text. Those were the days... Regards, GaborArticle: 136842
On Dec 8, 4:31=A0am, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com>
wrote:
> On Sun, 7 Dec 2008 18:15:36 -0800 (PST), NRClark
>
> <nicholas.cl...@gmail.com> wrote:
> >Hi all,
>
> >I am working with a couple of different pre-built modules, and one of
> >them expects to receive its data LSB first. I can't figure out for the
> >life of me how to connect it to my other modules.
>
> >That is to say:
>
> >I need to connect x[7:0] to y[7:0] so that y[7] =3D x[0], y[6] =3D x[1],=
y
> >[5] =3D x[2], etc. I need to do this for a few different 64-bit
> >connections, so I would really like avoid manually doing each
> >individual wire assignment. There must be some command in Verilog to
> >select from low-to-high, but I can't figure it out for the life of me :
>
> There isn't in traditional Verilog; you simply can't select
> a slice (part-select) of a vector in the "wrong" direction.
>
> SystemVerilog has its "streaming operators", which can do the
> job easily:
>
> =A0 reg [63:0] forward, reverse;
> =A0 ...
> =A0 reverse =3D {<<{forward}}; =A0
>
> but synthesis tool support for them is [searches desperately
> for polite word] patchy.
>
> As someone else said, you need to write a 'for' loop that will
> unroll in synthesis. =A0But if you need to do it several times,
> consider writing a function to do it:
>
> =A0 function [63:0] reverse (input [63:0] forward);
> =A0 =A0 integer i;
> =A0 =A0 for (i=3D0; i<=3D63; i=3Di+1)
> =A0 =A0 =A0 reverse[63-i] =3D forward[i];
> =A0 endfunction
>
> Or you could write the same code as a module, which
> can be parameterized for bit width, and then you have a
> general-purpose reverse-any-vector block:
>
> =A0 module endianness_swapper
> =A0 =A0 #(parameter width =3D 64)
> =A0 =A0 (input [width-1:0] forward, output reg [width-1:0] reverse);
>
> =A0 =A0 always @(forward) begin: swapper
> =A0 =A0 =A0 integer i;
> =A0 =A0 =A0 =A0 for (i=3D0; i<width; i=3Di+1)
> =A0 =A0 =A0 =A0 =A0 reverse[(width-1)-i] =3D forward[i];
> =A0 =A0 end
> =A0 endmodule
>
> Note that this will not work for bidirectional (inout) ports of
> your wrong-endian module. =A0For simulation that could be solved
> by writing a generate loop instancing a bunch of "tran" primitives,
> but that won't work for synthesis. =A0I'm not quite sure what the
> best way would be to handle that - probably, reverse the bus values
> at a point in the code where they are not bidirectional, so that
> you don't need to solve the harder problem.
> --
> Jonathan Bromley, Consultant
>
> DOULOS - Developing Design Know-how
> VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services
>
> Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
> jonathan.brom...@MYCOMPANY.comhttp://www.MYCOMPANY.com
>
> The contents of this message may contain personal views which
> are not the views of Doulos Ltd., unless specifically stated.
The bidirectional case is interesting in that it crops up
in VHDL as well. I had to fix such an issue where a generate
loop used an array of vectors, but then the array was assigned
(unidirectionally) to a number of individual vectors. That
of course didn't work for the bidirs, so I ended up unrolling
the generate loop.
You would think that synthesis would have some sort of bidirectional
connection (alias comes to mind, but it didn't solve my problem),
like a real wire? It's a good thing that FPGA's only have real
bidirectional signals at the pins, or I'd probably pull my hair
out over this...
Regards,
Gabor
Article: 136843Hi, I am trying to do post-translate simulation on Xilinx ISE 10.1 on a PC (Win XP). When I try to compile the UNISIM/SIMPRIM libraries, the system asks for 3rd party simulators. So I installed Model Sim PE student edition. I am again stuck because my design is bigger than ModelSim Student Edition would handle. My school has NC-Verilog on UNIX machines. Is there any way that I can compile, UNISIM/SIMPRIM libraries on PC for NC-Verilog simulator(NC- Verilog is on UNIX). When I try to compile, I get a message ncsim executable is not found because there is no NC-Verilog installed on PC. Can any one please suggest how can I get through this phase? Thanks.Article: 136844
On Dec 8, 3:24=A0pm, Digi Suji <digis...@gmail.com> wrote: > Hi, > > I am trying to do post-translate simulation on Xilinx ISE 10.1 on a PC > (Win XP). When I try to compile the UNISIM/SIMPRIM libraries, the > system asks for 3rd party simulators. So I installed Model Sim PE > student edition. I am again stuck because my design is bigger than > ModelSim Student Edition would handle. > > My school has NC-Verilog on UNIX machines. Is there any way that I can > compile, UNISIM/SIMPRIM libraries on PC for NC-Verilog simulator(NC- > Verilog is on UNIX). When I try to compile, I get a message ncsim > executable is not found because there is no NC-Verilog installed on > PC. > > Can any one please suggest how can I get through this phase? > > Thanks. The "compxlib" process in ISE actually calls ModelSim (or other third party software) to do the compilation. The library sources are in the Xilinx ISE installation tree, though. So you could compile them directly on your UNIX box. If you have a log from compiling the libraries for ModelSim PE Student edition, you can see where the source files are. It is also possible that ISE created a script for ncsim that you can directly use on the UNIX box.Article: 136845
Hi, I read reports that DDR3 can work at 400 MHz with FPGAs. Can DDR do the same? Thanks,Article: 136846
I have this happen all the time with ISE. The problem seems to be something with their database. You can reload a known good project and ISE can't build it. The other problem you may run into is that even though ISE will give a message that it built the project just fine, the actual output files will not get updated. Solution, blow away all the temp files. The files are stored under: C:\Documents and Settings\YOURUSERNAME\Local Settings\Temp Get rid of all the Xil files and any sub directories for Xilinx. If it looks like its related to ISE, get rid of it. Reload the project and run the clean function. Then it should build again, until the next crash. Version 10 still has this same problem. I started seeing it after I moved away from version 6. We asked Xilinx about it last spring and they promised it was all fixed in version 10. Hope this helps. > I have this problem, yesterday Project Navigator (ISE8.2) crashed while > opening a project, a serious crash, the system was restarted automatically. I > tried to open the project again, and PN crashed again, this time without > restarting the computer, but I got messages like "The memory cannot be read > ..." etc. etc. I tried again to open the project, this time no errors, but it > seems that the project file is damaged, the project is not loaded, I get only > some strange characters in the Sources Pane. Now this happens also with other > projects. Of course I'm sure that the projects are good, I tested them on a > different computer. In few words, ISE is not working anymore on this computer. > > I got this problem in the past with ISE7.1, the solution was to format the > PC, even removing and reinstalling ISE didn't solve the problem. I really > would like to evitate formatting the computer this time, any hints?Article: 136847
Hi,
Try looking at Gidel @ www.gidel.com. They have some PCIe cards based
on StratixII and III chips. Their documentation isn't great and they're a
bit stingy with example code and they also encrypt their IP totally, but the
cards and development system, ProcWizard seem promising.
I just started working with one of their Proce cards a few weeks ago.
CTW.
"rush2sami" <rush2sami@yahoo.com> wrote in message
news:kZ6dnePvhqQ3ebvUnZ2dnUVZ_q3inZ2d@giganews.com...
> Hi Guys,
> I am looking for an Altera FPGA development board for high speed Video
> processing/Live video streaming/high speed data transfer to CPU with min
> 300MBps using PCI/PCI-Express . The FPGA should be from Altera. .Please
> let me know the right Altera development board for my Implemetation.
>
> Regards,
> Swaminathan
>
>
Article: 136848On Dec 8, 5:14=A0pm, "lecroy7...@chek.com" <lecroy7...@chek.com> wrote: > I have this happen all the time with ISE. =A0The problem seems to be > something with their database. =A0You can reload a known good project > and ISE can't build it. =A0 =A0The other problem you may run into is that > even though ISE will give a message that it built the project just > fine, the actual output files will not get updated. > > Solution, blow away all the temp files. > > The files are stored under: > > C:\Documents and Settings\YOURUSERNAME\Local Settings\Temp > > Get rid of all the Xil files and any sub directories for Xilinx. =A0 If > it looks like its related to ISE, get rid of it. > > Reload the project and run the clean function. =A0Then it should build > again, until the next crash. =A0 Version 10 still has this same > problem. =A0I started seeing it after I moved away from version 6. =A0We > asked Xilinx about it last spring and they promised it was all fixed > in version 10. > > Hope this helps. > > > I have this problem, yesterday Project Navigator (ISE8.2) crashed while > > opening a project, a serious crash, the system was restarted automatica= lly. I > > tried to open the project again, and PN crashed again, this time withou= t > > restarting the computer, but I got messages like "The memory cannot be = read > > ..." etc. etc. I tried again to open the project, this time no errors, = but it > > seems that the project file is damaged, the project is not loaded, I ge= t only > > some strange characters in the Sources Pane. Now this happens also with= other > > projects. Of course I'm sure that the projects are good, I tested them = on a > > different computer. In few words, ISE is not working anymore on this co= mputer. > > > I got this problem in the past with ISE7.1, the solution was to format = the > > PC, even removing and reinstalling ISE didn't solve the problem. I real= ly > > would like to evitate formatting the computer this time, any hints? > > Version 10.1 also stores some temporary files under your project directory. Take a look at this thread on the Xilinx forums: http://forums.xilinx.com/xlnx/board/message?board.id=3DISE&message.id=3D338= 8&query.id=3D305458#M3388 Regards, GaborArticle: 136849
Hello all, I have a question regarding migration of design from Xilinx FPGA to ASIC. There are lot of Xilinx IP Cores(I am sure even Altera will have too) which are commonly used for Arithmetic Purposes. For instance my design uses the Xilinx FFT/IFFT IP Cores and if the design has to be moved to the ASIC at later stages, can Xilinx Provide the netlist for ASIC technology as well? I hope I put down my query clearly and will be glad to receive responses. Thanks in advance, Venkat.
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