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On 2009-03-04, oktem@su.sabanciuniv.edu <oktem@su.sabanciuniv.edu> wrote: > I want to automatically put the current date (year,month,day maybe > hour) in a 32 bit register during the synthesis stage. I am using > Modelsim as a simulator and Xilinx Xst as a synthesis tool. My target > fpga is Spartan 3. Can someone explain me is there an easy way to > implement? I don't think there is an easy way to do this from inside ISE (although perhaps some TCL hacking could solve this?). What I do is that I use a Makefile based approach for synthesis and simulation. In this case it is fairly easy to automatically generate a file with the current date (or revision number in my case) in it which is then included at an appropriate place in the design. Otherwise you may be able to postprocess either the NCD file or the bitstream. For example, if it is enough to put the current date into a blockram you can do this using a script which uses data2mem to modify the content of the blockram. /AndreasArticle: 138676
I want to automatically put the current date (year,month,day maybe hour) in a 32 bit register during the synthesis stage. I am using Modelsim as a simulator and Xilinx Xst as a synthesis tool. My target fpga is Spartan 3. Can someone explain me is there an easy way to implement?Article: 138677
On Mar 4, 3:42=A0am, ok...@su.sabanciuniv.edu wrote: > I want to automatically put the current date (year,month,day maybe > hour) in a 32 bit register during the synthesis stage. I am using > Modelsim as a simulator and Xilinx Xst as a synthesis tool. My target > fpga is Spartan 3. Can someone explain me is there an easy way to > implement? In many of my designs, I create a parameter in an include file like parameter BUILD_EPOCH =3D 32'd0; I have Perl script I can then run then modifies the parameter line to have the current Unix style epoch value. In my design, I have a rd-only status register that returns BUILD_EPOCH to the host processor. There are lots of routines in the standard C libraries to convert the epoch value in month/day/year. I hope this helps. John ProvidenzaArticle: 138678
It appears that search engines are associating bad links to searches on our company name and products and I advise no one at present to click on such links. Our website does not appear to be compromised but do hand type the URL for the moment if you need anything off the website. I don't know if this a general attack or just on our company. John Adair Enterpoint Ltd.Article: 138679
I have worked for Lattice until lat year. It looks like only the first two devices are available. I know that Lattice has done at least one respin on the silicon. So I assume it might be a good idea to first ask for samples. If they let you sign an acknoledgement paper, I wouldn't start a board with ECP3, but ECP2M is a good alternative. You can try to let them drop the price to ECP3 level. Regards, Luc On Tue, 3 Mar 2009 10:07:06 -0800 (PST), Jecel <jecel@merlintec.com> wrote: >On Feb 27, 4:59 pm, Antti wrote: >> it seems they even have working silicon :) >> well PCIe was already offered in ECP2 > >I am not familiar with the Lattice world. Would it be reasonable to >design a board with the ECP3 at this point if I want to be selling >them in two months or so? For other vendors I would wait at least a >year before doing something like this. Though the Lattice site already >has a "buy samples" link on the ECP3 page, it doesn't return any >results. > >-- JecelArticle: 138680
David, I know from experience that - at least in Europe - disti's suck. They will say of course that the silicon is available. But when it comes to production, then you might have a problem. Luc On Wed, 04 Mar 2009 09:32:49 +0100, David Brown <david@westcontrol.removethisbit.com> wrote: >Kim Enkovaara wrote: >> rickman wrote: >> >>> I don't have any experience with Lattice new introductions, but I >>> think Xilinx is the only FPGA maker that has introductions and won't >>> sell to small companies for 6 months or more. Altera seems to pride >>> themselves on being more conservative with introductions, waiting >>> until the product is nearly ready to ship to distributors before they >>> announce. I think Lattice is like that too. I know nothing about >> >> I think that the introductions are more market driven. For example >> Stratix IV was announced long before there were any chips available, >> quite probably due to the V5 pressure. >> >> On the other hand some Xilinx chips have been available for big >> customers before the official introduction. I think on the long run all >> the vendors are quite equal in their introductions. If the situation >> is tight they announce early, and if they are comfortable it is enough >> to announce the chips to big customers and test with them the samples. >> > >My impression is that Altera says they introducing a new device when >they have internal test samples, then give a timetable for rolling out >the devices. When Xilinx says a device is "available", they really mean >that the marketing brochures are available (assuming you are a very >large customer)... > >Either way, it's always best to check with your distributor - they >should know the real situation.Article: 138681
On Mar 3, 11:59=A0pm, Muzaffer Kal <k...@dspia.com> wrote: > Hi, > I'm porting an ASIC design to virtex-5. In the design there is a > 32x32->64 bit signed multiplier and I can't seem to do any better than > synthesis at this point (tried two different synthesis tools which > give the same results also). What would be the fastest way to do a > 32x32 multiplier in Virtex-5? I'm trying to get it to run at 125 MHz > on a xc5vlx50-1. Area is no problem and I'm currently using 4 DSP48E > blocks. I haven't tried a fabric only implementation but I can't > imagine that being faster. Alas adding pipelining to the existing > design is out of the question. > > -- > Muzaffer Kal > > DSPIA INC. > ASIC/FPGA Design Serviceshttp://www.dspia.com Four 16x16 multiplies and then added give 64 bits. Perhaps the additions can be register balanced further down stream within existing pipeline stages.Article: 138682
John Adair <g1@enterpoint.co.uk> wrote: > It appears that search engines are associating bad links to searches > on our company name and products and I advise no one at present to > click on such links. Our website does not appear to be compromised but > do hand type the URL for the moment if you need anything off the > website. I don't know if this a general attack or just on our company. I saw a similar problem on a user's PC the other day which I attributed to a local compromise of that system. The behavior was that we would go to www.google.com and search for something (a video driver for the system in question) and the first google result was for a URL at intel.com (unlikely to have been taken over as a phishing site one would hope), and mousing over the url showed it to indeed be going to intel.com/... If we clicked the google result link however, we got navigated to some other site (may have had shopping in the url) and an immediate AVG popup warning about an attack from the site being visited. Copying and pasting the link into the address bar worked correctly, so again my assumption is that the local machine was compromised as I could not see any other way this behavior could be caused. Do you have an exmaple of a search that causes this problem for you? I'm rather curious now. G.Article: 138683
oktem@su.sabanciuniv.edu wrote:
>I want to automatically put the current date (year,month,day maybe
>hour) in a 32 bit register during the synthesis stage. I am using
>Modelsim as a simulator and Xilinx Xst as a synthesis tool. My target
>fpga is Spartan 3. Can someone explain me is there an easy way to
>implement?
I don't think there is a way to do this. Perhaps someone should create
a plugin for Eclipsen that generates a makefile for use with the
Xilinx tools. That would make these sort of things much easier since
Eclipse offers support for running pre and post programs/batch files
(whatever can be run). The editor would also be less crappy.
--
Failure does not prove something is impossible, failure simply
indicates you are not using the right tools...
"If it doesn't fit, use a bigger hammer!"
--------------------------------------------------------------
Article: 138684Gavin Using "enterpoint" in google is enough although it is happening to pile of different, unrelated, people. It appears to be going to other search engines as well. We had a number of customers that telephoned us to say they had the problem so it doesn't appear to be a single infection. John Adair Enterpoint Ltd. On 4 Mar, 19:34, ga...@allegro.com (Gavin Scott) wrote: > John Adair <g...@enterpoint.co.uk> wrote: > > It appears that search engines are associating bad links to searches > > on our company name and products and I advise no one at present to > > click on such links. Our website does not appear to be compromised but > > do hand type the URL for the moment if you need anything off the > > website. I don't know if this a general attack or just on our company. > > I saw a similar problem on a user's PC the other day which I attributed > to a local compromise of that system. The behavior was that we would go > towww.google.comand search for something (a video driver for the > system in question) and the first google result was for a URL at > intel.com (unlikely to have been taken over as a phishing site one > would hope), and mousing over the url showed it to indeed be going to > intel.com/... > > If we clicked the google result link however, we got navigated to some > other site (may have had shopping in the url) and an immediate AVG > popup warning about an attack from the site being visited. > > Copying and pasting the link into the address bar worked correctly, so > again my assumption is that the local machine was compromised as I > could not see any other way this behavior could be caused. > > Do you have an exmaple of a search that causes this problem for you? > I'm rather curious now. > > G.Article: 138685
newman5382@yahoo.com wrote: > On Mar 3, 11:59 pm, Muzaffer Kal <k...@dspia.com> wrote: >>I'm porting an ASIC design to virtex-5. In the design there is a >>32x32->64 bit signed multiplier and I can't seem to do any better than >>synthesis at this point (snip) > Four 16x16 multiplies and then added give 64 bits. Perhaps the > additions can be register balanced further down stream within existing > pipeline stages. Well, 16x16 unsigned multiply, 16x16 signed multiply, and two 16x16 unsigned times signed multiply. That isn't hard using the Xilinx 18x18 signed multiply though. The correction needed to convert between them isn't that hard, and could be pipelined along with the additions of partial products, if the wider multiply wasn't available. -- glenArticle: 138686
On Mar 4, 3:11=A0pm, Glen Herrmannsfeldt <g...@ugcs.caltech.edu> wrote: > newman5...@yahoo.com wrote: > > On Mar 3, 11:59 pm, Muzaffer Kal <k...@dspia.com> wrote: > >>I'm porting an ASIC design to virtex-5. In the design there is a > >>32x32->64 bit signed multiplier and I can't seem to do any better than > >>synthesis at this point > > (snip) > > > Four 16x16 multiplies and then added give 64 bits. =A0Perhaps the > > additions can be register balanced further down stream within existing > > pipeline stages. > > Well, 16x16 unsigned multiply, 16x16 signed multiply, and two > 16x16 unsigned times signed multiply. > > That isn't hard using the Xilinx 18x18 signed multiply though. > > The correction needed to convert between them isn't that hard, > and could be pipelined along with the additions of partial products, > if the wider multiply wasn't available. > > -- glen I forgot about the signed part after I posted. Thx.Article: 138687
On Wed, 04 Mar 2009 13:11:25 -0700, Glen Herrmannsfeldt <gah@ugcs.caltech.edu> wrote: >newman5382@yahoo.com wrote: > >> On Mar 3, 11:59 pm, Muzaffer Kal <k...@dspia.com> wrote: > >>>I'm porting an ASIC design to virtex-5. In the design there is a >>>32x32->64 bit signed multiplier and I can't seem to do any better than >>>synthesis at this point >(snip) > >> Four 16x16 multiplies and then added give 64 bits. Perhaps the >> additions can be register balanced further down stream within existing >> pipeline stages. > >Well, 16x16 unsigned multiply, 16x16 signed multiply, and two >16x16 unsigned times signed multiply. > >That isn't hard using the Xilinx 18x18 signed multiply though. > >The correction needed to convert between them isn't that hard, >and could be pipelined along with the additions of partial products, >if the wider multiply wasn't available. Which is what I and synthesis are doing at the moment. The problem is that TDSPCKO_PCOUTA_M in the part I'm using is is 4.23ns already so I need to find another way. As I have mentioned in my initial post, changing the existing pipeline is not an option as it would trigger a huge verification task. Luckily there seems to be a way by going to an internally faster clock and adding the pipeline there without changing the interface. -- Muzaffer Kal DSPIA INC. ASIC/FPGA Design Services http://www.dspia.comArticle: 138688
On Mar 4, 3:26=A0pm, Muzaffer Kal <k...@dspia.com> wrote: > On Wed, 04 Mar 2009 13:11:25 -0700, Glen Herrmannsfeldt > > > > > > <g...@ugcs.caltech.edu> wrote: > >newman5...@yahoo.com wrote: > > >> On Mar 3, 11:59 pm, Muzaffer Kal <k...@dspia.com> wrote: > > >>>I'm porting an ASIC design to virtex-5. In the design there is a > >>>32x32->64 bit signed multiplier and I can't seem to do any better than > >>>synthesis at this point > >(snip) > > >> Four 16x16 multiplies and then added give 64 bits. =A0Perhaps the > >> additions can be register balanced further down stream within existing > >> pipeline stages. > > >Well, 16x16 unsigned multiply, 16x16 signed multiply, and two > >16x16 unsigned times signed multiply. > > >That isn't hard using the Xilinx 18x18 signed multiply though. > > >The correction needed to convert between them isn't that hard, > >and could be pipelined along with the additions of partial products, > >if the wider multiply wasn't available. > > Which is what I and synthesis are doing at the moment. The problem is > that TDSPCKO_PCOUTA_M in the part I'm using is is 4.23ns already so I > need to find another way. As I have mentioned in my initial post, > changing the existing pipeline is not an option as it would trigger a > huge verification task. Luckily there seems to be a way by going to an > internally faster clock and adding the pipeline there without changing > the interface. > -- > Muzaffer Kal > > DSPIA INC. > ASIC/FPGA Design Serviceshttp://www.dspia.com- Hide quoted text - > > - Show quoted text - You actually did not say changing the pipeline was not an option, you said adding a pipeline was not an option. I don't really know what you are up against. That is why I said perhaps. Good luck!Article: 138689
In article <1d0d2eaf-7edb-4553-831c-0323cb101da7@r16g2000vbp.googlegroups.com>, John Adair <g1@enterpoint.co.uk> writes: >Gavin > >Using "enterpoint" in google is enough although it is happening to >pile of different, unrelated, people. It appears to be going to other >search engines as well. We had a number of customers that telephoned >us to say they had the problem so it doesn't appear to be a single >infection. > >John Adair >Enterpoint Ltd. Your web server has been hacked. I did a google search, then watched the network traffic while I poked the link to your site. Your site is redirecting me off to various spammers. -- These are my opinions, not necessarily my employer's. I hate spam.Article: 138690
Hal Murray <hal-usenet@ip-64-139-1-69.sjc.megapath.net> wrote: > Your web server has been hacked. > I did a google search, then watched the network traffic while > I poked the link to your site. Your site is redirecting me > off to various spammers. That would explain it, though I have to say I have not yet seen any strange behavior from John's site. No redirects, no adds, no popups, nothing. A packet trace is completely clean here. So it may still be something more interesting than just that his server has been hacked. G.Article: 138691
On Mar 3, 1:14=A0pm, Sean Durkin <news_MO...@tuxroot.de> wrote: > Essy wrote: > > The constants should be set all at the power-up, so using block rams > > won't be a good idea since each block ram will be used for only one of > > them. I was thinking of saving these constants as initial values of > > the FFs. In this case, the resources and routing won't be affected. > > But, the problem is how to change the initial value of FFs. Are they > > accessible through the bitstream? What really happens when we assign > > the initial values of the registers in the VHDL or Verilog code? > > When you use XST, at least in version 10.1 (haven't tried any others), > it does evaluate and apply the initial values of signals. So when you > declare a signal in your VHDL that is later used as a register and > assign an inital value to it, that's the register's value after > power-up. These initial values could be set using changing generics, and > at least theoretically in this case a guided par should work OK and save > some time. But this has some downsides: > > 1. Doesn't work with every synthesis tool. I know that Precision > Synthesis ignores initial values (at least it did the last time I > checked), don't remember if Synplify does, don't know if Quartus does. > So if there's a chance you're going to work with any other synthesis > tool besides XST sometime, you'll have to find yet another solution > then. Some, but again not all tools, use the reset values assigned to > FFs as the power-up value. You could use the reset value and then make > sure the design is actually reset. > > 2. When you're working with generics, you can usually forget any guided > modes. The reason is that tools tend to use the generics for their > internally generated instance names. E.g. Precision generates names like > instancename_genericvalue1_genericvalue2_genericvalue3 and so on in its > netlists. So, if one of the generics changes, the instance names change, > and any guided mode won't find the proper instances the second time > around, hence re-implementing almost everything. I suppose in these > cases changing constants declared in a package work better. But then > again, if a package changes, all the modules using it will probably be > re-implemented by default... > > So, basically, I feel your pain. :) Usually, what I do in these cases is: > > 1. Do what KJ suggested, if feasible in that case, or > 2. Use an external (or maybe internal) microcontroller to set the > register values via software. I usually have the luxury of actually > having an external uC hooked up to the FPGA, so this works well. Lets me > =A0peek and poke at the regs on-the-fly as well, which is always nice. > > Of course this only works if the changing stuff doesn't modify bus > widths and such, things that actually have bigger impact on the logic > that is created. Synthesis tools are funny beasts. They *love* to "optimize" logic. So even if these constants are values for comparisons or whatever, the resulting logic may be optimized to a point that changing a bit won't do the job. In fact, I am pretty sure the FF can be optmized away since the tool should recognize that its state never changes. So to be able to change the "constants" they need to be put in FFs that will not be optimized away. I've never thought about this, so I can't give any advice. Using a KEEP on the output net of the FF won't do the job. But if, instead of using an "initial" value, you set the D input to the FFs with a constant and apply a KEEP to this input signal, this may just do the job. Still, to change the FF after synthesis will require changing the routing of the inputs to the FFs, so that still does not buy you what you want. Maybe if you instantiate FFs, then you can drive the clock and D inputs to zero and use the configuration setting to establish the output value. Those initial values set by the GSR on configuration should be modifiable by one of the methods described earlier. You might still need to use KEEP attributes to prevent the optimization of the FFs. RickArticle: 138692
On Mar 3, 4:12=A0pm, Sean Durkin <news_MO...@tuxroot.de> wrote: > S. Bernstein schrieb:> Hi, > > > we are using a Virtex4 fx200 on our own board design. Now we plan to up= grade > > to Virtex6 with 10 Gbit/s MGTs. Do we need to develop a complete new bo= ard > > or are the two families compatible so that we can replace the Virtex4 w= ith a > > Virtex6 with faster IOs and the board design remains the same? > > Virtex6 and Virtex4 are not pin-compatible, as far as I know, so the > board will have to change. Plus, core voltage is different for the two > families, so the power supply will have to be adjusted. Plus, as another > poster noted, there is no more 3.3V-IO, which might be a problem for you > as well if you need it. I'm sure there's a lot more subtle differences... > > cu, > Sean Anyone know if 3.3 volt I/O is still with us in the new Spartan 6 devices? RickArticle: 138693
rickman <gnuarm@gmail.com> writes: > Anyone know if 3.3 volt I/O is still with us in the new Spartan 6 > devices? http://www.xilinx.com/publications/prod_mktg/Spartan6_Overview.pdf says : > Multi-voltage, multi-standard SelectIO banks > ... > − 3.3V to 1.2V I/O standards and protocols So yes - hurrah! Any bets on whether the next Spartan family will still have it? Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.net/electronics.htmlArticle: 138694
oktem@su.sabanciuniv.edu writes: > I want to automatically put the current date (year,month,day maybe > hour) in a 32 bit register during the synthesis stage. I am using > Modelsim as a simulator and Xilinx Xst as a synthesis tool. My target > fpga is Spartan 3. Can someone explain me is there an easy way to > implement? Another thought - you can pass an extra param to bitgen to put the date into the USERCODE field where it can be read over JTAG by, for example, Impact. As with the others, not sure if you can do this through ISE, but I use a scripted PAR flow which makes it easy to add in. Does ISE allow "user scripts" to run during, before, or after any of its processes? C-based IDEs have had pre and post build scripts for years! Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.net/electronics.htmlArticle: 138695
Now i have a tcl script which takes current date and convert it to a binary I can run this tcl script from the tcl shell menu of xilinx project navigator I added a generic current_date variable on my top module I added this varible to generics, parameters part of Synthesis Options menu of Xilinx. So everythime i want to synthesize, I need to run the tcl script, get the output of the function, copy and paste it to the current_date at the generics tab of synthesis options and run. Actually I was not able to do it with the makefile approach since it seems harder for me. I need a little more explanation. best regardsArticle: 138696
I believe we are back to normal now touching the preverbial wood. We have looked at the website and as yet not found a hack. Various organisations are now trying to trace it's source and the morons behind it. It anyone sees this again can you let us know. John Adair Enterpoint On 5 Mar, 01:26, ga...@allegro.com (Gavin Scott) wrote: > Hal Murray <hal-use...@ip-64-139-1-69.sjc.megapath.net> wrote: > > Your web server has been hacked. > > I did a google search, then watched the network traffic while > > I poked the link to your site. =A0Your site is redirecting me > > off to various spammers. > > That would explain it, though I have to say I have not yet seen any > strange behavior from John's site. No redirects, no adds, no popups, > nothing. A packet trace is completely clean here. > > So it may still be something more interesting than just that his > server has been hacked. > > G.Article: 138697
I'm using a deserializer 7 to 1 core (from xapp265) in Spartan 3AN. After power up it is not functional until I'm retriggering prog_b or loading the bit file from JTAG. It's impossible to debug this problem with Chipscope because in order to do that I need to load the bit file and after that it's working. What might be the problem?Article: 138698
hi everyone, tool : xilinx spartan 3a dsp system overview : image taken form digital camera (c3038) connected to fpga needs to be stored in simple dual port BRAM (written in one port and read from other)and displayed on vga monitor. problem statement : digital data given by camera (c3038) written on RAM at 17Mhz,but for VGA monitor display these data needs to be read at 25Mhz, .i want to take the advantage of two independent clocks of dual port bram,but the data should neither be overwritten nor be lost. any idea regarding the problems are appreciated.Article: 138699
On 5 Mrz., 14:10, deep <infoparaj...@gmail.com> wrote: > hi everyone, > tool : xilinx spartan 3a dsp > system overview : image taken form digital camera (c3038) connected to > fpga needs to be stored in simple dual port BRAM (written in one port > and read from other)and displayed on vga monitor. > problem statement : digital data given by camera (c3038) written on > RAM at 17Mhz,but for VGA monitor display these data needs to be read > at 25Mhz, .i want to take the advantage of two independent clocks of > dual port bram,but the data should neither be overwritten nor be lost. > any idea regarding the problems are appreciated. hi, your read clock is about 3 times faster than necessary so there will be gaps during the data transfer that can be used for synchronisation of input and output data. Draw a time scheme of incoming data und outgoing data. Check how it can be matched without overlapping. Use two memory banks for storing the incoming pics. (Thats just one more adress line that toggles on every new picture) Hope that was helpful. Regards Eilert
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