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I just wonder ;) the FREE is not so free actually... all infos say the ColdFire core is free, and no royalties but the free license is only for Cyclone III, for all other devices the license is 10k + 0.02 royalty also what is strange there seems to be no download for the free version :( AnttiArticle: 139201
On Mar 23, 3:28=A0pm, Stephen Craven <stephen.cra...@gmail.com> wrote: > Antti and others, > > This may be covered by another thread, in which case I would > appreciate a link. > > What are your thoughts on the Silicon Blue devices? =A0How is it to use > their tools? > > Sephen OK, here it is 1) new project 2) add vhdl, verilog files 3) click constraints 4) select signals and IO locs from dropdown 5) close constraints window 6) click run flow 7) start SB backend tools 8) click programmer 9) click program the tools are not as sophiscated as the bigones, but they do generate bit files.. for me that all that matters. there are some small news that are maybe not so known 1) all devices are now offered with nonvolatile storage (no more -V parts) 2) the current numbers are reduces down, the smallest part at 32khz 8uA (was 25 i think) sure as everything is pretty new still there are some problems, like the hex files generated use lower case ascii and Keil's hex2bin chokes on that :) so i had to write another conversion well actually i didnt, i added support for ascii-bin format to my portable SPI flash programmer http://www.microfpga.com/ i just got the LED blinking on the Silicon Blue stamp, not that it is big achievement but it is possible first public photo of an SB FPGA based product ever :) I am doing the factory boot image for the SB stamp, that should allow user configurations to be downloaded over UART/SPI or then loaded from SD card there is still some confusion with the warmboot what i hope to solve soon as well. besides the warmboot most other functions of the FPGA are tested, that is block ram init, etc Antti PS I will write some more in March issue of the Brain...Article: 139202
On Mar 23, 7:03=A0am, "Antti.Luk...@googlemail.com" <Antti.Luk...@googlemail.com> wrote: > On Mar 23, 12:43=A0pm, "colin_toog...@yahoo.com" > > <colin_toog...@yahoo.com> wrote: > > Hopefully I'm not throwing a big spanner in the works but.. > > > Have you considered using an ALTERA MAXII. They market it as a CPLD > > but is is really a very small (but bigger that your coolrunner) FPGA. > > > They only need 3v3 and while not a drop in replacement it will replace > > your coolrunner very easily. All FPGAs need several supplies. > > > Some time ago I designed a 40 pin DIL which just has a MAXII on it so > > if you only need 36 IO it would only take a short time to install the > > ALTERA dev tools and see if it fits. I have several bare PCBs so I > > could easily sort you something out. > > > Colin > > Lattice XP FPGA's are TRUE single supply FPGA's > also much better price/performance ratio then maxII or machXO > > Antti How is that different from the MAXII parts? Are you saying that the MAXII parts are not true single supply, or not true FPGAs? They use 4LUTs and have routing based on individual cells rather than blocks, so why wouldn't they be FPGAs? The only reason they aren't called FPGAs that I can tell is because they use Flash. But Flash doesn't really make it a CPLD in my mind. RickArticle: 139203
On Mar 23, 4:47=A0pm, rickman <gnu...@gmail.com> wrote: > On Mar 23, 7:03=A0am, "Antti.Luk...@googlemail.com" > > > > <Antti.Luk...@googlemail.com> wrote: > > On Mar 23, 12:43=A0pm, "colin_toog...@yahoo.com" > > > <colin_toog...@yahoo.com> wrote: > > > Hopefully I'm not throwing a big spanner in the works but.. > > > > Have you considered using an ALTERA MAXII. They market it as a CPLD > > > but is is really a very small (but bigger that your coolrunner) FPGA. > > > > They only need 3v3 and while not a drop in replacement it will replac= e > > > your coolrunner very easily. All FPGAs need several supplies. > > > > Some time ago I designed a 40 pin DIL which just has a MAXII on it so > > > if you only need 36 IO it would only take a short time to install the > > > ALTERA dev tools and see if it fits. I have several bare PCBs so I > > > could easily sort you something out. > > > > Colin > > > Lattice XP FPGA's are TRUE single supply FPGA's > > also much better price/performance ratio then maxII or machXO > > > Antti > > How is that different from the MAXII parts? =A0Are you saying that the > MAXII parts are not true single supply, or not true FPGAs? =A0They use > 4LUTs and have routing based on individual cells rather than blocks, > so why wouldn't they be FPGAs? =A0The only reason they aren't called > FPGAs that I can tell is because they use Flash. =A0But Flash doesn't > really make it a CPLD in my mind. > > Rick eh ok, its the NAMING issue :) MAX II is marketed as PLD machXO is markted as "crossover device" XP is marketed as FPGA so while we may think of the maxii and machxo as FPGA, they arent marketed as FPGA, and being so tiny, not classifying as FPGAs (too small), similarly i would not call IGLOO10 an FPGA as it too small (it still marketed as FPGA) so if all confused named not taken into account, then XP is the only FPGA (also marketed as FPGA) that is true single chip and single supply AnttiArticle: 139204
On Mar 23, 3:45=A0pm, Antti <Antti.Luk...@googlemail.com> wrote: > I just wonder ;) > > the FREE is not so free actually... all infos say the ColdFire core is > free, and no royalties > but the free license is only for Cyclone III, for all other devices > the license is 10k + 0.02 royalty > > also what is strange there seems to be no download for the free > version :( > > Antti Ok, it maybe possible to obtain the free version but not completly free you have to actually place an ORDER with total of 0.0 after that i got notification that i will soon receive EULA and QUATATION i need sign the EULA and PO and send to the headquarters.. so the price maybe 0.0, but i still need pay for the delivery of the signed documents.. curious, what price will be quoted for a free product? AnttiArticle: 139205
I was reading the data sheet the other day and I noticed that these parts have 5 volt compatible I/Os on three of the four banks. I'm pretty impressed with that... until I read that the fourth bank is not even 3.3 volt tolerant!!! What's up with that? Can do 5 volts on three banks and fourth can only do 2.5 just seems like a very strange combination. I can't for the life of me understand why or how this was done. Obviously there was some compelling reason to do this and I can only speculate that it was because of the additional I/O types in bank 3. Still, taking away from the number of 3.3 volt I/Os is a *very* poor marketing decision in my opinion. Now I would have to use a larger package to get the same number of *usable* I/O pins. The other oddity I found was the lack of parity bits in the RAM blocks. There are a lot of designs that use the extra bits, including mine, that won't fit on these parts at all. One other thing I noticed, they seem to be changing the planned packaging, which is not surprising I suppose. In the package list, they flag compatible pinouts using the same package. But I don't see the 04 and 08 as being compatible in the 196 pin package. This package was added since rev 1.1 of the data sheet, so it is surprising to me that these would not be compatible. The CS132 package looks pretty interesting. The main reason that I avoid BGAs is the PCB requirements to provide routing from the inner pins. This package looks like it might be routable without running traces between the pads or even vias within the pads. But the innermost 16 pads seem to mess this up. Anyone have a good routing layout for this package? What PCB design rules are required to use this package? Rick On Mar 23, 10:12 am, "Antti.Luk...@googlemail.com" <Antti.Luk...@googlemail.com> wrote: > On Mar 23, 3:28 pm, Stephen Craven <stephen.cra...@gmail.com> wrote: > > > Antti and others, > > > This may be covered by another thread, in which case I would > > appreciate a link. > > > What are your thoughts on the Silicon Blue devices? How is it to use > > their tools? > > > Sephen > > OK, here it is > > 1) new project > 2) add vhdl, verilog files > 3) click constraints > 4) select signals and IO locs from dropdown > 5) close constraints window > 6) click run flow > 7) start SB backend tools > 8) click programmer > 9) click program > > the tools are not as sophiscated as the bigones, > but they do generate bit files.. for me that all that matters. > > there are some small news that are maybe not so known > 1) all devices are now offered with nonvolatile storage (no more -V > parts) > 2) the current numbers are reduces down, the smallest part at 32khz > 8uA (was 25 i think) > > sure as everything is pretty new still there are some problems, like > the hex files generated > use lower case ascii and Keil's hex2bin chokes on that :) so i had to > write another conversion > well actually i didnt, i added support for ascii-bin format to my > portable SPI flash programmer > > http://www.microfpga.com/ > > i just got the LED blinking on the Silicon Blue stamp, not that it is > big achievement > but it is possible first public photo of an SB FPGA based product > ever :) > > I am doing the factory boot image for the SB stamp, that should allow > user > configurations to be downloaded over UART/SPI or then loaded from SD > card > > there is still some confusion with the warmboot what i hope to solve > soon > as well. besides the warmboot most other functions of the FPGA are > tested, that is block ram init, etc > > Antti > PS I will write some more in March issue of the Brain...Article: 139206
On Mar 22, 6:32=A0am, Antti <Antti.Luk...@googlemail.com> wrote: > Hi > > the datasheet has been updated 18 march but the download link doesnt > work from SBT web, > correct URL is > > http://www.siliconbluetech.com/media/iCE65Datasheet.pdf > > Antti BTW, when I downloaded this file, I noticed that this is version 1.4.3 data March 9, while there is a 1.4.4 dated March 18. RickArticle: 139207
On Mar 23, 6:01=A0pm, rickman <gnu...@gmail.com> wrote: > I was reading the data sheet the other day and I noticed that these > parts have 5 volt compatible I/Os on three of the four banks. =A0I'm > pretty impressed with that... until I read that the fourth bank is not > even 3.3 volt tolerant!!! =A0What's up with that? =A0Can do 5 volts on > three banks and fourth can only do 2.5 just seems like a very strange > combination. =A0I can't for the life of me understand why or how this > was done. =A0Obviously there was some compelling reason to do this and I > can only speculate that it was because of the additional I/O types in > bank 3. =A0Still, taking away from the number of 3.3 volt I/Os is a > *very* poor marketing decision in my opinion. =A0Now I would have to use > a larger package to get the same number of *usable* I/O pins. > > The other oddity I found was the lack of parity bits in the RAM > blocks. =A0There are a lot of designs that use the extra bits, including > mine, that won't fit on these parts at all. > > One other thing I noticed, they seem to be changing the planned > packaging, which is not surprising I suppose. =A0In the package list, > they flag compatible pinouts using the same package. =A0But I don't see > the 04 and 08 as being compatible in the 196 pin package. =A0This > package was added since rev 1.1 of the data sheet, so it is surprising > to me that these would not be compatible. > > The CS132 package looks pretty interesting. =A0The main reason that I > avoid BGAs is the PCB requirements to provide routing from the inner > pins. =A0This package looks like it might be routable without running > traces between the pads or even vias within the pads. =A0But the > innermost 16 pads seem to mess this up. =A0Anyone have a good routing > layout for this package? =A0What PCB design rules are required to use > this package? > > Rick Hi yes 5V tolerant !! yipiie jee, and bank-3 unusuable unless 2.5V supply is available its not only that it is not 3.3V tolerant, you need 2.5V if you want to use this bank at all, so in both my current design bank-3 is unused and VCCIO3 is open i bet that bank 3 uses completly different IO cell, hence the voltage requirements http://www.microfpga.com/ both PCBs are 2 layer, no microvia, no trace between pads, no via in pad, no via between pads (but vias below the package where spacing areas available) smallest drilled hole 0.3mm but the number of IOs routable on 2 layers is limited, for both those FPGA's in 132 8x8 package the number of ios routable out in 2 layers is something between 40 and 50 AnttiArticle: 139208
Hi, I get these errors when trying to build a dual data rate bidirectionnal IO bus. ERROR:Pack:1564 - The dual data rate register <signal name> failed to join the OLOGIC component as required. The OLOGIC SR signal does not match the ILOGIC SR signal, or the ILOGIC SR signal is absent. My design looks like this: - output signals goes through an ODDR macro, then to the IOBUF. - input signals goes from the IOBUF to an IDDR macro. If I clock the ODDR and IDDR modules with the same clock, then I dont get these errors. For timing reasons, I wish I could clock the IDDR module with a different clock, for example the negedge of the ODDR clock, but then I got the errors. Could anyone explain me this error, or maybe suggest another design? thanksArticle: 139209
Johnson Can you elaborate on your I/O requirements as this may affect what is best for your application. Most of the board vendors in the FPGA world like ourselves don't supply boards as bundled software kits as such. The software aspect tends to come from whichever processor core is being used. However there are one or two Xilinx and Altera kits that include some sort of tools version with the boards for MicroBlaze and Nios respectively but they don't tend to be in hobby engineer price area. For the lowest cost you may have to think about seperate solution for a microprocessor and board. There various microprocessor cores on Opencores that are based on popular things like Z80 and so on and there are lots of tools out there for that common processor. There also things like 8086/8 cores available from third party vendors http://www.ht-lab.com/hardware/drigmorn1/drigmorn1.html but these do cost. John Adair Enterpoint Ltd. On 23 Mar, 05:08, "Johnson L" <gpsab...@yahoo.com> wrote: > For my hobby work, I am looking for a low-cost development kit to > develope a simple embedded system. This system will measure the temperature > and heart beat rate, compare them with a predefined table which implements > some health-care knowledge, then provide some useful information. This > development kit should be low-cost, support C programming, debugging, better > with JTAG or other on-site debugging. It should support at least one type of > popular microprocessors, or a mainstream FPGA, > and easy to use. Could anybody recommend me some? Thank you in advance. > > JohnsonArticle: 139210
rickman <gnuarm@gmail.com> wrote: > I was reading the data sheet the other day and I noticed that these > parts have 5 volt compatible I/Os on three of the four banks. I'm > pretty impressed with that... until I read that the fourth bank is not > even 3.3 volt tolerant!!! What's up with that? Can do 5 volts on > three banks and fourth can only do 2.5 just seems like a very strange > combination. I don't know about this one specifically, but there is a well known tradeoff between voltage and speed. It might be that those are used when speed is important. -- glenArticle: 139211
Hey I am trying to implement Haar discrete wavelet transformation for image compression on Virtex 2 Pro device. I am using Xilinx Platform Studio (XPS) for reading image from SYS ACE Flash card embedded on device and also for processing. I need to have floating point calculation for wavelet transformation. Please guide me how to add floating point unit using XPS. Also what changes should I make in the C code which I wrote in XPS, for reading and processing image, for implementing it. Regards, Mohit PrakashArticle: 139212
mopra <mohitprakas@gmail.com> wrote: > I need to have floating point calculation for wavelet transformation. There are various implementations of floating point around, or you can do your own. > Please guide me how to add floating point unit using XPS. Also what > changes should I make in the C code which I wrote in XPS, for reading > and processing image, for implementing it. You should not implement C code in an FPGA. Well, what is your goal? Why are you using an FPGA instead of, say, an Athlon64? If you want throughput then I would recommend a systolic array, which will look very different from the C code. If you just want to run compiled C code on an FPGA that is different, but why? -- glenArticle: 139213
"John Adair" <g1@enterpoint.co.uk> wrote in message news:a38658ca-69a3-4af4-bfde-1c4abf7f7264@37g2000yqp.googlegroups.com... > Johnson > > Can you elaborate on your I/O requirements as this may affect what is > best for your application. > > Most of the board vendors in the FPGA world like ourselves don't > supply boards as bundled software kits as such. The software aspect > tends to come from whichever processor core is being used. However > there are one or two Xilinx and Altera kits that include some sort of > tools version with the boards for MicroBlaze and Nios respectively but > they don't tend to be in hobby engineer price area. > > For the lowest cost you may have to think about seperate solution for > a microprocessor and board. There various microprocessor cores on > Opencores that are based on popular things like Z80 and so on and > there are lots of tools out there for that common processor. There > also things like 8086/8 cores available from third party vendors > http://www.ht-lab.com/hardware/drigmorn1/drigmorn1.html but these do > cost. > > John Adair > Enterpoint Ltd. > > On 23 Mar, 05:08, "Johnson L" <gpsab...@yahoo.com> wrote: >> For my hobby work, I am looking for a low-cost development kit to >> develope a simple embedded system. This system will measure the >> temperature >> and heart beat rate, compare them with a predefined table which >> implements >> some health-care knowledge, then provide some useful information. This >> development kit should be low-cost, support C programming, debugging, >> better >> with JTAG or other on-site debugging. It should support at least one type >> of >> popular microprocessors, or a mainstream FPGA, >> and easy to use. Could anybody recommend me some? Thank you in advance. >> >> Johnson > Thanks, John, your answer is very informative and helpful. However, as a hobby engineer I don't know how to elaborate the I/O requirements. Could you please give me a simple example? As for now, I would like the sensors being connected to the microprocessor in a simple way, such as I2C or UART. I possibly also need a port for BLUETOOTH or ZIGBEE to send out the commands to a wireless peripheral. BTW, if I understand it correct, there is no free or low-cost development kit for FPGA, right? JohnsonArticle: 139214
Johnson It's not quite true that there are not free tools for FPGAs. Both the 2 biggest vendors Xilinx and Altera have free tools for building the hardware side for the smaller end FPGAs themselves. Processor support tools specifically Xilinx has 2 soft core processors that they support - PicoBlaze and MicroBlaze. Altera have Nios. Picoblaze I believe a third party has done a C compiler and the group probably has more details that I do. MicroBlaze (EDK) and Nios toolsets are essentially paid for tools although there are sometimes evaluation versions around that are good for short term use. On I/O things like acceptable voltage levels e.g. 3.3V or 5V signalling requirements are important. Many modern FPGAs cannot tolerate 5V signalling levels directly without some protection, or level shift, circuits. Particular protocols like I2C will need to be driven and controlled by some logic function within the FPGA user design. If you are using external modules for bluetooth etc. then again you need to use whatever signalling levels and protocols are required to transfer data and setup to the external modules. John Adair Enterpoint Ltd. On 23 Mar, 21:36, "Johnson L" <gpsab...@yahoo.com> wrote: > "John Adair" <g...@enterpoint.co.uk> wrote in message > > news:a38658ca-69a3-4af4-bfde-1c4abf7f7264@37g2000yqp.googlegroups.com... > > > > > > > Johnson > > > Can you elaborate on your I/O requirements as this may affect what is > > best for your application. > > > Most of the board vendors in the FPGA world like ourselves don't > > supply boards as bundled software kits as such. The software aspect > > tends to come from whichever processor core is being used. However > > there are one or two Xilinx and Altera kits that include some sort of > > tools version with the boards for MicroBlaze and Nios respectively but > > they don't tend to be in hobby engineer price area. > > > For the lowest cost you may have to think about seperate solution for > > a microprocessor and board. There various microprocessor cores on > > Opencores that are based on popular things like Z80 and so on and > > there are lots of tools out there for that common processor. There > > also things like 8086/8 cores available from third party vendors > >http://www.ht-lab.com/hardware/drigmorn1/drigmorn1.htmlbut these do > > cost. > > > John Adair > > Enterpoint Ltd. > > > On 23 Mar, 05:08, "Johnson L" <gpsab...@yahoo.com> wrote: > >> For my hobby work, I am looking for a low-cost development kit to > >> develope a simple embedded system. This system will measure the > >> temperature > >> and heart beat rate, compare them with a predefined table which > >> implements > >> some health-care knowledge, then provide some useful information. This > >> development kit should be low-cost, support C programming, debugging, > >> better > >> with JTAG or other on-site debugging. It should support at least one type > >> of > >> popular microprocessors, or a mainstream FPGA, > >> and easy to use. Could anybody recommend me some? Thank you in advance. > > >> Johnson > > Thanks, John, your answer is very informative and helpful. However, as a > hobby engineer I don't know how to elaborate the I/O requirements. Could you > please give me a simple example? > As for now, I would like the sensors being connected to the microprocessor > in a simple way, such as I2C or UART. I possibly also need a port for > BLUETOOTH or ZIGBEE to send out the commands to a wireless peripheral. > BTW, if I understand it correct, there is no free or low-cost development > kit for FPGA, right? > Johnson- Hide quoted text - > > - Show quoted text -Article: 139215
So I have to design a low-power data queuing system. I've never done a low power design, so I though I'd come to this newsgroup to solicit a few ideas. I'm going to be continuously receiving data at 55KBps. I have to store a whole days worth of data before I offload the data to another device which ends up being ~4.8GB. The offload rate is going to be ~6.5MBps. My initial thinking is to build Cool-Runner or a Spartan-3E to control an SD-Card. But it's totally open, so I could use Compact Flash, USB flash key, or even some SDRAM. So with the main constraints being low- power and ease of implementation, what would you guys suggest. Thanks in advance.Article: 139216
On Mon, 23 Mar 2009 15:28:32 -0700 (PDT) ed.agunos@gmail.com wrote: > So I have to design a low-power data queuing system. I've never done a > low power design, so I though I'd come to this newsgroup to solicit a > few ideas. > > I'm going to be continuously receiving data at 55KBps. I have to store > a whole days worth of data before I offload the data to another device > which ends up being ~4.8GB. The offload rate is going to be ~6.5MBps. > > My initial thinking is to build Cool-Runner or a Spartan-3E to control > an SD-Card. But it's totally open, so I could use Compact Flash, USB > flash key, or even some SDRAM. So with the main constraints being low- > power and ease of implementation, what would you guys suggest. > > Thanks in advance. That's a huge amount of data to be holding onto. Neither writing to flash nor refreshing that much DRAM is going to be particularly power cheap. What kind (read how compressable) of data are you going to be dealing with? Also, as an initial thought, for these sorts of data rates my mind goes to a microcontroller long before it goes to any kind of PLD. You might want to ping comp.arch.embedded with this one, too. -- Rob Gaddi, Highland Technology Email address is currently out of orderArticle: 139217
"Rob Gaddi" <rgaddi@technologyhighland.com> wrote in message news:20090323155627.000011fd@unknown... > Also, as an initial thought, for these sorts of data rates my mind > goes to a microcontroller long before it goes to any kind of PLD. What he ^^ said!Article: 139218
Just to clarify what power budget do you have? John Adair Enterpoint Ltd. On 23 Mar, 22:28, ed.agu...@gmail.com wrote: > So I have to design a low-power data queuing system. I've never done a > low power design, so I though I'd come to this newsgroup to solicit a > few ideas. > > I'm going to be continuously receiving data at 55KBps. I have to store > a whole days worth of data before I offload the data to another device > which ends up being ~4.8GB. The offload rate is going to be ~6.5MBps. > > My initial thinking is to build Cool-Runner or a Spartan-3E to control > an SD-Card. But it's totally open, so I could use Compact Flash, USB > flash key, or even some SDRAM. So with the main constraints being low- > power and ease of implementation, what would you guys suggest. > > Thanks in advance.Article: 139219
On Mar 24, 4:01=A0am, rickman <gnu...@gmail.com> wrote: > I was reading the data sheet the other day and I noticed that these > parts have 5 volt compatible I/Os on three of the four banks. =A0I'm > pretty impressed with that... until I read that the fourth bank is not > even 3.3 volt tolerant!!! =A0What's up with that? =A0Can do 5 volts on > three banks and fourth can only do 2.5 just seems like a very strange > combination. =A0I can't for the life of me understand why or how this > was done. =A0Obviously there was some compelling reason to do this and I > can only speculate that it was because of the additional I/O types in > bank 3. =A0Still, taking away from the number of 3.3 volt I/Os is a > *very* poor marketing decision in my opinion. =A0Now I would have to use > a larger package to get the same number of *usable* I/O pins. The newest Xilinx parts drop 3.3V I believe ? - but yes, on a small part that includes 5V, missing 3.3V on a bank, looks more like a mistake, than a design-decision!. 5V IO is nice, especially on smaller parts. 5V is making something of a comeback, more uC are now 5V too :) Dropping 5V on small parts is never a good decision.... Power MOSFETS are lousy driven from 3.3V ! -jg .Article: 139220
> yes 5V tolerant !! yipiie jee, and bank-3 unusuable unless 2.5V supply > is available > its not only that it is not 3.3V tolerant, you need 2.5V if you want > to use this bank at all, > so in both my current design bank-3 is unused and VCCIO3 is open > i bet that bank 3 uses completly different IO cell, hence the voltage > requirements But isn't 2.5V always available ? "VPP_2V5 must always be connected to a valid voltage." I see it tolerates 2.3-3.0V, and B3 is 2.63V (abs Max 3.0) so perhaps a new standard of 2.65V could power the part ? :) The Bank3 does support MDDR, so that seems to be what chopped the 3.3V -jgArticle: 139221
On Mar 24, 2:05=A0am, -jg <Jim.Granvi...@gmail.com> wrote: > > yes 5V tolerant !! yipiie jee, and bank-3 unusuable unless 2.5V supply > > is available > > its not only that it is not 3.3V tolerant, you need 2.5V if you want > > to use this bank at all, > > so in both my current design bank-3 is unused and VCCIO3 is open > > i bet that bank 3 uses completly different IO cell, hence the voltage > > requirements > > But isn't 2.5V always available ? > "VPP_2V5 must always be connected to a valid voltage." > > I see it tolerates 2.3-3.0V, and B3 is 2.63V (abs Max 3.0) so perhaps > a new standard > of 2.65V could power the part ? :) > > The Bank3 does support MDDR, so that seems to be what chopped the 3.3V > > -jg Jim VPP_2V5 tolerated 3.3V so just happily connect 3.3V no need for 2.5 to be always present AnttiArticle: 139222
On Mar 23, 8:05=A0pm, -jg <Jim.Granvi...@gmail.com> wrote: > > yes 5V tolerant !! yipiie jee, and bank-3 unusuable unless 2.5V supply > > is available > > its not only that it is not 3.3V tolerant, you need 2.5V if you want > > to use this bank at all, > > so in both my current design bank-3 is unused and VCCIO3 is open > > i bet that bank 3 uses completly different IO cell, hence the voltage > > requirements > > But isn't 2.5V always available ? > "VPP_2V5 must always be connected to a valid voltage." > > I see it tolerates 2.3-3.0V, and B3 is 2.63V (abs Max 3.0) so perhaps > a new standard > of 2.65V could power the part ? :) > > The Bank3 does support MDDR, so that seems to be what chopped the 3.3V I did a search, but I didn't find many details on MDDR; or is it mDDR? The supply voltage seems to be 1.8V and I believe it is differential. Banks 0, 1 and 2 support 1.8V LVCMOS voltages. I guess I wonder why MDDR can't be supported with hardware that is 3.3V tolerant? RickArticle: 139223
On Mar 23, 7:52=A0pm, -jg <Jim.Granvi...@gmail.com> wrote: > On Mar 24, 4:01=A0am, rickman <gnu...@gmail.com> wrote: > > > I was reading the data sheet the other day and I noticed that these > > parts have 5 volt compatible I/Os on three of the four banks. =A0I'm > > pretty impressed with that... until I read that the fourth bank is not > > even 3.3 volt tolerant!!! =A0What's up with that? =A0Can do 5 volts on > > three banks and fourth can only do 2.5 just seems like a very strange > > combination. =A0I can't for the life of me understand why or how this > > was done. =A0Obviously there was some compelling reason to do this and = I > > can only speculate that it was because of the additional I/O types in > > bank 3. =A0Still, taking away from the number of 3.3 volt I/Os is a > > *very* poor marketing decision in my opinion. =A0Now I would have to us= e > > a larger package to get the same number of *usable* I/O pins. > > The newest Xilinx parts drop 3.3V I believe ? > - but yes, on a small part that includes 5V, missing 3.3V on a bank, > looks more like a mistake, than a design-decision!. I wouldn't say it was a mistake, unless you mean from a marketing decision. However, their target market seems very clear, "iCE Low Power FPGA for Handhelds". I expect they realized that loosing 3.3 volt on a portion of the I/Os is not such a big deal and being compatible with mobile memory is very important. I would hazard it is all about the power! > 5V IO is nice, especially on smaller parts. To tell you the truth, if they are looking for handset sockets, I would say 5 volt tolerance is not a requirement. I assume that it was not hard to include. To keep power low, I believe thicker oxides are important, especially for quiescent power. Thicker oxides permit higher voltages. So maybe the 5 volt tolerance came for free. > 5V is making something of a comeback, =A0more uC are now 5V too :) When you say "more", I never found many that dropped 5 volt tolerance, even the newer, low core voltage parts. > Dropping 5V on small parts is never a good decision.... > > Power MOSFETS are lousy driven from 3.3V ! It all depends on the market. The big FPGA companies live and die with telecoms and we're not talking about handsets. I wonder if they will respond with their own parts for handsets? Intel seems to be very protective of any market that has a chance of being sizable and open to more complex processors. I wonder if X, A or L will go for what could be a really *huge* market in terms of quantity. I have been told that even with profits approaching zero, a large volume product can keep a company going through downturns and make good money in upturns. RickArticle: 139224
I just got an FPGA development kit from Lattice - 2200 CLB's, USB (FX2) Interface, a software starter kit, and an 8-bit embedded processor. $75 including tax & Shipping. Software license expires every 6 months; I'm guessing that they will renew it. Software is reminiscent of Xilinx back in the ISE-4.2 days (clumsy, but functional). The embedded processor (Mico8) looks -very- interesting: if I'm seeing things correctly, they chose 'wishbone' for their on-chip bus. AL On Mar 23, 3:14 pm, John Adair <g...@enterpoint.co.uk> wrote: > Johnson > > It's not quite true that there are not free tools for FPGAs. Both the > 2 biggest vendors Xilinx and Altera have free tools for building the > hardware side for the smaller end FPGAs themselves. Processor support > tools specifically Xilinx has 2 soft core processors that they support > - PicoBlaze and MicroBlaze. Altera have Nios. Picoblaze I believe a > third party has done a C compiler and the group probably has more > details that I do. MicroBlaze (EDK) and Nios toolsets are essentially > paid for tools although there are sometimes evaluation versions around > that are good for short term use. > > On I/O things like acceptable voltage levels e.g. 3.3V or 5V > signalling requirements are important. Many modern FPGAs cannot > tolerate 5V signalling levels directly without some protection, or > level shift, circuits. Particular protocols like I2C will need to be > driven and controlled by some logic function within the FPGA user > design. If you are using external modules for bluetooth etc. then > again you need to use whatever signalling levels and protocols are > required to transfer data and setup to the external modules. > > John Adair > Enterpoint Ltd. > > On 23 Mar, 21:36, "Johnson L" <gpsab...@yahoo.com> wrote: > > > "John Adair" <g...@enterpoint.co.uk> wrote in message > > >news:a38658ca-69a3-4af4-bfde-1c4abf7f7264@37g2000yqp.googlegroups.com... > > > > Johnson > > > > Can you elaborate on your I/O requirements as this may affect what is > > > best for your application. > > > > Most of the board vendors in the FPGA world like ourselves don't > > > supply boards as bundled software kits as such. The software aspect > > > tends to come from whichever processor core is being used. However > > > there are one or two Xilinx and Altera kits that include some sort of > > > tools version with the boards for MicroBlaze and Nios respectively but > > > they don't tend to be in hobby engineer price area. > > > > For the lowest cost you may have to think about seperate solution for > > > a microprocessor and board. There various microprocessor cores on > > > Opencores that are based on popular things like Z80 and so on and > > > there are lots of tools out there for that common processor. There > > > also things like 8086/8 cores available from third party vendors > > >http://www.ht-lab.com/hardware/drigmorn1/drigmorn1.htmlbutthese do > > > cost. > > > > John Adair > > > Enterpoint Ltd. > > > > On 23 Mar, 05:08, "Johnson L" <gpsab...@yahoo.com> wrote: > > >> For my hobby work, I am looking for a low-cost development kit to > > >> develope a simple embedded system. This system will measure the > > >> temperature > > >> and heart beat rate, compare them with a predefined table which > > >> implements > > >> some health-care knowledge, then provide some useful information. This > > >> development kit should be low-cost, support C programming, debugging, > > >> better > > >> with JTAG or other on-site debugging. It should support at least one type > > >> of > > >> popular microprocessors, or a mainstream FPGA, > > >> and easy to use. Could anybody recommend me some? Thank you in advance. > > > >> Johnson > > > Thanks, John, your answer is very informative and helpful. However, as a > > hobby engineer I don't know how to elaborate the I/O requirements. Could you > > please give me a simple example? > > As for now, I would like the sensors being connected to the microprocessor > > in a simple way, such as I2C or UART. I possibly also need a port for > > BLUETOOTH or ZIGBEE to send out the commands to a wireless peripheral. > > BTW, if I understand it correct, there is no free or low-cost development > > kit for FPGA, right? > > Johnson- Hide quoted text - > > > - Show quoted text -
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