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Messages from 143475

Article: 143475
Subject: Re: How to enter lower boundary character pair within Microsoft
From: Weng Tianxiang <wtxwtx@gmail.com>
Date: Mon, 12 Oct 2009 11:14:12 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Oct 12, 11:08=A0am, Weng Tianxiang <wtx...@gmail.com> wrote:
> On Oct 12, 9:07=A0am, rickman <gnu...@gmail.com> wrote:
>
>
>
>
>
> > On Oct 11, 8:34=A0pm, Weng Tianxiang <wtx...@gmail.com> wrote:
>
> > > Hi,
> > > Please help.
>
> > > I want to enclose the following equation data n/2**j with a lower
> > > boundary character pair within Microsoft Office Word 2007.
>
> > > 0 <=3D i <=3D low_boundary(n/2**j) ;
>
> > > Thank you.
>
> > > Weng
>
> > Have you checked the insert symbol table? =A0If what you need is not
> > there, try inserting a Microsoft Equation object. =A0Insert, Object,
> > Create New, Microsoft Equations 3.0 is the process in Word 2003.
>
> > Rick
>
> Hi Rick,
> Thank you. I will try your method. The character pair is not within
> the insert symbol table.
>
> Weng- Hide quoted text -
>
> - Show quoted text -

Hi Rick,
Sorry. Your method fails. The reason is when to insert a object, it
needs you entering the characters which I don't know. If I know it, I
don't have to use the Microsoft Equation.

I think the pair is in some font which I need to know.

Weng

Article: 143476
Subject: Re: integrating chipscope pro in EDK
From: austin <austin@xilinx.com>
Date: Mon, 12 Oct 2009 11:49:09 -0700 (PDT)
Links: << >>  << T >>  << A >>
Prashant,

I suggest first you learn how to insert Chipscope using ISE.  Then,
once you have mastered that, you may then "graduate" to inserting
Chipscope using EDK (XPS).

Chipscope provides the ability to monitor internal (specified)
signals, and as such, is a very hardware-centric debug tool.  EDK is a
software-centric platform, so it is a bit like asking the programmer
to use the logic analyzer (usually the programmer has no clue how to
do this -- "not my job.").

Which version are you using?  There are some small differences between
9.x, 10.x, and the new 11.x.  In general, if this is a new project, I
always suggest using the latest tools.  But, if this is a student
project, you are probably told which tools to use.

There are a number of helpful links online, the UC Berkeley EECS 150
lab is just one of many.

Article: 143477
Subject: Re: Win a Dev Kit--Join Us on Twitter & Facebook
From: gabor <gabor@alacron.com>
Date: Mon, 12 Oct 2009 13:01:21 -0700 (PDT)
Links: << >>  << T >>  << A >>
T24gT2N0IDEyLCAxMjoxN6BwbSwgIkFudHRpLkx1ay4uLkBnb29nbGVtYWlsLmNvbSIKPGFudHRp
Lmx1ay4uLkBnb29nbGVtYWlsLmNvbT4gd3JvdGU6Cj4gT24gT2N0IDEyLCA3OjU5oHBtLCBDb2xp
biBQYXVsIEdsb3N0ZXIgPENvbGluX1BhdWxfR2xvcy4uLkBBQ00ub3JnPgo+IHdyb3RlOgo+Cj4K
Pgo+ID4gT24gT2N0b2JlciAxMnRoLCAyMDA5LCBBbHRlcmEgQW5ub3VuY2VtZW50cyBhcHBhcmVu
dGx5IG1pc2xlYWRpbmdseQo+ID4gZW1haWxlZDoKPgo+ID4gfC0tLS0tLS0tLS0tLS0tLS0tLS0t
LS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0t
LS0tLS0tLS0tLS0tLS0tLS0tfAo+ID4gfCJJZiB5b3UgY2Fubm90IHJlYWQgdGhpcyBtZXNzYWdl
LCBwbGVhc2UgY2xpY2sgaGVyZSCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCg
IKAgoCCgfAo+ID4gfEpvaW4gdXMgb24gVHdpdHRlciBhbmQgRmFjZWJvb2sgoCCgIKAgoCCgIKAg
oCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgfAo+ID4g
fFtzcGFjZXIuZ2lmXSCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCg
IKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgfAo+ID4gfFtzcGFjZXIuZ2lm
XSCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCg
IKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgfAo+ID4gfEpvaW4gdXMgb24gVHdpdHRlciAmIEZh
Y2Vib29rIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAg
oCCgIKAgoCCgIKAgoCCgfAo+ID4gfEVudGVyIHRvIFdpbiBhIERldmVsb3BtZW50IEtpdCCgIKAg
oCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCg
IKAgfAo+ID4gfCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAg
oCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgfAo+ID4gfExv
b2tpbmcgZm9yIG5ldyB3YXlzIHRvIGNvbm5lY3Qgd2l0aCBBbHRlcmE/IEpvaW4gdXMgb24gVHdp
dHRlciCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgfAo+ID4gfGFuZCBGYWNlYm9vayB0
bzogoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAg
oCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgfAo+ID4gfCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCg
IKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAg
oCCgIKAgoCCgIKAgfAo+ID4gfCAqIKBTdGF5IG9uIHRvcCBvZiB3aGF0P3MgZ29pbmcgb24gaW4g
QWx0ZXJhIGFuZCBvdXIgaW5kdXN0cnkgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCg
fAo+ID4gfCAqIKBTaGFyZSB5b3VyIHRob3VnaHRzIGFuZCBpZGVhcyB3aXRoIHVzIGRpcmVjdGx5
IKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgfAo+ID4gfCAqIKBH
ZXQgeW91ciBjaGFuY2UgdG8gd2luIGEgQmVNaWNybyBvciBOaW9zIElJIEVtYmVkZGVkIKAgoCCg
IKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgfAo+ID4gfCCgIKBFdmFsdWF0aW9uIEtp
dCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCg
IKAgoCCgIKAgoCCgIKAgoCCgIKAgfAo+ID4gfEpvaW4gVXMgVG9kYXkgoCCgIKAgoCCgIKAgoCCg
IKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAg
oCCgIKAgoCCgfAo+ID4gfEpvaW4gdXMgb24gVHdpdHRlciBhbmQgRmFjZWJvb2sgoCCgIKAgoCCg
IKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgfAo+
ID4gfFtmb290ZXJfbGluZS5qcGddIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCg
IKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgfAo+ID4gfCCgIKAgoCCg
IKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAg
oCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgfAo+ID4gfKAgoCCgIKAgoCCgIKAgoCCgIKAg
oCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCg
IKAgoCCgIKAgoCCgIKAgoCCgfAo+ID4gfEFzIGEgc3Vic2NyaWJlciB0byB0aGUgIlByb2R1Y3Qg
QW5ub3VuY2VtZW50cyBhbmQgVXBkYXRlcyIgZW1haWwgbGlzdCwgd2Ugd2lsbCBub3RpZnkgeW91
IGFib3V0fAo+ID4gfG5ldyBwcm9kdWN0cywgZXZlbnRzIGFuZCBvdGhlciB1cGRhdGVzVG8gc3Vi
c2NyaWJlIG9yIHVuc3Vic2NyaWJlIGZyb20gQWx0ZXJhIGVtYWlsIHVwZGF0ZXMgYW5kfAo+ID4g
fGVuZXdzbGV0dGVycyBwbGVhc2UgdmlzaXQgb3VyIEVtYWlsIFN1YnNjcmlwdGlvbiBDZW50ZXIu
IKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgfAo+ID4gfCCgIKAgoCCgIKAg
oCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCg
IKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgfAo+ID4gfKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCg
IKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAg
oCCgIKAgoCCgIKAgoCCgfAo+ID4gfEFsdGVyYSBGb3J1bSCgoKCgoFR3aXR0ZXIgoKCgoKAgRmFj
ZWJvb2sgoKCgoKBGbGlja2VyIKCgoKCgWW91VHViZSCgoKCgoFlvdVR1YmUgoCCgIKAgoCCgIKAg
oCCgfAo+ID4gfKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCg
IKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgfAo+ID4gfCCg
IKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAg
oCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgfAo+ID4gfCCgIKAgoCCgIKAgoCCg
IKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAg
oCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgfAo+ID4gfENvcHlyaWdodCCpIDE5OTUtMjAwOSBBbHRl
cmEgQ29ycG9yYXRpb24sIDEwMSBJbm5vdmF0aW9uIERyaXZlLCBTYW4gSm9zZSwgQ2FsaWZvcm5p
YSA5NTEzNCwgVVNBfAo+ID4gfCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCg
IKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAg
fAo+ID4gfEFMVEVSQSwgQVJSSUEsIENZQ0xPTkUsIEhBUkRDT1BZLCBNQVgsIE1FR0FDT1JFLCBO
SU9TLCBRVUFSVFVTICYgU1RSQVRJWCBhcmUgUmVnLiBVLlMuIFBhdC4gJiCgfAo+ID4gfFRtLiBP
ZmYuIGFuZCBBbHRlcmEgbWFya3MgaW4gYW5kIG91dHNpZGUgdGhlIFUuUy4goCCgIKAgoCCgIKAg
oCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgfAo+ID4gfCCgIKAgoCCgIKAgoCCgIKAg
oCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCg
IKAgoCCgIKAgoCCgIKAgoCCgIKAgfAo+ID4gfFs/VjdBRkRYQkhDVz1zc0lEOjUyNjQ2OTczNV0i
IKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAg
oCCgIKAgoCCgfAo+ID4gfC0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0t
LS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tfAo+
Cj4gPiBEZWFyIFNpci9NYWRhbSwKPgo+ID4gQWZ0ZXIgZm9sbG93aW5nIGEgbnVtYmVyIG9mIGh5
cGVybGlua3MsIEkgd2FzIGV2ZW50dWFsbHkgaW5mb3JtZWQgb24KPiA+IFdXVy5BbHRlcmEuY29t
L2IvdHdpdHRlci1mYWNlYm9vay1naXZlYXdheS1ydWxlcy5odG1sCj4gPiA6IlsuLl0KPgo+ID4g
MS4gRWxpZ2liaWxpdHk6IE9ubHkgbGVnYWwgcGVyc29ucywgKGkpIHdobyBhcmUgcGh5c2ljYWxs
eSBsb2NhdGVkIGFuZAo+ID4gcmVzaWRpbmcgaW4gdGhlIENvbnRpbmVudGFsIFUuUy4gb3Igb3Ro
ZXJ3aXNlIGVsaWdpYmxlIHVuZGVyCj4gPiBhcHBsaWNhYmxlIGxvY2FsIGxhd3MsIFsuLl0KPgo+
ID4gWy4uXSIKPgo+ID4gSSBoYXZlIG5ldmVyIGJlZW4gaW4gdGhlIENvbnRpbmVudGFsIFUuUy46
IHNvIGFtIEkgZWxpZ2libGUgdG8gd2luIG9uZQo+ID4gb2YgdGhvc2Uga2l0cyBvciBkaWQgeW91
IHdhc3RlIG15IHRpbWU/Cj4KPiA+IFlvdXJzIGZhaXRoZnVsbHksCj4gPiBDb2xpbiBQYXVsIEds
b3N0ZXIKPgo+IHdhc3RlIG9mIHRpbWUKPiBtb3N0IHN1Y2ggdGhpbmdzIGFyZSBmb3IgVVMgcmVz
aWRlbnRzIG9ubHkKPgo+IEFudHRpCgpUaGV5IG9ubHkgd2FzdGUgYSBsaXR0bGUgb2YgeW91ciB0
aW1lLiAgVHdpdHRlciBhbmQgRmFjZWJvb2sKYXJlIGNvbG9zc2FsIHdhc3RlcyBvZiB0aW1lLiAg
SSB3b3VsZCBub3QgaGF2ZSBldmVuIGZvbGxvd2VkCnRoZSBmaXJzdCBsaW5rIGluIHRoYXQgbWFp
bC4KCkp1c3QgbXkgMiBjZW50cywKR2Fib3I=

Article: 143478
Subject: Re: problem while receiving negative integer in microblaze
From: rickman <gnuarm@gmail.com>
Date: Mon, 12 Oct 2009 13:04:27 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Oct 12, 1:08 pm, GrIsH <grishkun...@gmail.com> wrote:
> On Oct 12, 9:02 am, rickman <gnu...@gmail.com> wrote:
>
> > On Oct 11, 9:05 am, GrIsH <grishkun...@gmail.com> wrote:
>
> > > I got the problem while receiving the value of "count" (i.e. of
> > > integer type with value positive as well as negative) in MICROBLAZE
> > > that was send from custom IP  named as encoder module using "User
> > > Logic Software Register"  IPIF. Encoder module counts the value of
> > > encoder pulses ranges from -5000 to +5000.
>
> > > I assigned value of   "count"  to  IP2Bus_Data by converting it to
> > > std_logic_vector type and receive this value in microblaze software
> > > application using variable "Data_receive" of int type. and
> > > "Data_received" was displayed into Hyper Terminal But data received
> > > was not as expecting mainly the negative numbers.....so how this
> > > problem is resolved to get exact data, positive as well as negative.
>
> > > Can i receive the data in Microblaze application in std_logic_vector
> > > form?? i mean std_logic_vector equivalent form....
>
> > > OR is there any easier method of transferring negative data ...??
>
> > > Another problem is...... i found SIGNED(N downto 0) is same as
> > > std_logic_vector except it represents +ve as well as -ve
> > > numbers....But it didn't work in my program...why??
>
> > > my code written in "user_logic".vhd template is given below.....
> > > ------------------------------------------------------------------------------------------------------------------------------
> > > signal cnt:                                     integer range -5000 to 5000:=0;
>
> > >  my_uut1:process(channel_A) is
> > >     begin
> > >         if(channel_A 'event and channel_A='1') then
> > >             direction<= '1' and channel_B;
> > >         end if;
> > >     end process;
>
> > >     my_uut2:process(channel_A) is
> > >     begin
> > >         if(channel_A 'event and channel_A='1') then
> > >             if(direction='0') then
> > >                 cnt<=cnt+1;
> > >             else
> > >                 cnt<=cnt-1;
> > >             end if;
> > >         end if;
> > >     end process;
>
> > > IP2Bus_Data(0 to 15)  <= (others=>'0');
> > > IP2Bus_Data(16 to 31) <= conv_std_logic_vector(cnt,16);
> > > -----------------------------------------------------------------------------------------------------------------------------
> > > SOFTWARE APPLICATION IN MICROBLAZE
>
> > > Xint DataRead;
>
> > > encoder_module_p = (Xuint32 *)XPAR_ENCODER_MODULE_0_BASEADDR;
> > > XASSERT_NONVOID(encoder_module_p != XNULL);
> > > encoder_module = (Xuint32 *)encoder_module_p;
>
> > >         while(1){
>
> > >                 DataRead = ENCODER_MODULE_mReadSlaveReg0(encoder_module, 0);
> > >                 xil_printf("Received data: %d\r\n", DataRead);
>
> > >         }
>
> > You only included part of your code, I don't see your library
> > declarations and the other signal declarations.  I guess IP2Bus_Data
> > is an output maybe?
>
> > Your problem likely is in the numbering of your bus.  How was it
> > declared, 31 downto 0 (the most common convention) or 0 to 31 (not so
> > common)?  You are assigning the msb of the integer to bit 16 of your
> > SLV which is in the middle of the vector.  I can see why uBlaze is
> > confused.
>
> > I also recommend that you not use std_logic_arith.  This has been
> > covered many, many times here and elsewhere.  There are some sticky
> > issues with using this package.  It is highly recommended to use
> > ieee.std_logic_1164 and ieee.numeric_std.  I won't go into the details
> > of why this is better, but if you continue to use std_logic_arith
> > don't say you weren't warned.
>
> > Rick
>
> Here is my complete code:
>
> library ieee;
> use ieee.std_logic_1164.all;
> use ieee.std_logic_arith.all;
> use ieee.std_logic_unsigned.all;
>
> library proc_common_v2_00_a;
> use proc_common_v2_00_a.proc_common_pkg.all;
>
> -- DO NOT EDIT ABOVE THIS LINE --------------------
>
> --USER libraries added here
>
> ------------------------------------------------------------------------------
> -- Entity section
> ------------------------------------------------------------------------------
> -- Definition of Generics:
> --   C_SLV_DWIDTH                 -- Slave interface data bus width
> --   C_NUM_REG                    -- Number of software accessible
> registers
> --
> -- Definition of Ports:
> --   Bus2IP_Clk                   -- Bus to IP clock
> --   Bus2IP_Reset                 -- Bus to IP reset
> --   Bus2IP_Data                  -- Bus to IP data bus
> --   Bus2IP_BE                    -- Bus to IP byte enables
> --   Bus2IP_RdCE                  -- Bus to IP read chip enable
> --   Bus2IP_WrCE                  -- Bus to IP write chip enable
> --   IP2Bus_Data                  -- IP to Bus data bus
> --   IP2Bus_RdAck                 -- IP to Bus read transfer
> acknowledgement
> --   IP2Bus_WrAck                 -- IP to Bus write transfer
> acknowledgement
> --   IP2Bus_Error                 -- IP to Bus error response
> ------------------------------------------------------------------------------
>
> entity user_logic is
>   generic
>   (
>     -- ADD USER GENERICS BELOW THIS LINE ---------------
>     --USER generics added here
>     -- ADD USER GENERICS ABOVE THIS LINE ---------------
>
>     -- DO NOT EDIT BELOW THIS LINE ---------------------
>     -- Bus protocol parameters, do not add to or delete
>     C_SLV_DWIDTH                   : integer              := 32;
>     C_NUM_REG                      : integer              := 1
>     -- DO NOT EDIT ABOVE THIS LINE ---------------------
>   );
>   port
>   (
>     -- ADD USER PORTS BELOW THIS LINE ------------------
>     channel_A:          in std_logic;
>          channel_B:             in std_logic;
>     -- ADD USER PORTS ABOVE THIS LINE ------------------
>
>     -- DO NOT EDIT BELOW THIS LINE ---------------------
>     -- Bus protocol ports, do not add to or delete
>     Bus2IP_Clk                     : in  std_logic;
>     Bus2IP_Reset                   : in  std_logic;
>     Bus2IP_Data                    : in  std_logic_vector(0 to
> C_SLV_DWIDTH-1);
>     Bus2IP_BE                      : in  std_logic_vector(0 to
> C_SLV_DWIDTH/8-1);
>     Bus2IP_RdCE                    : in  std_logic_vector(0 to
> C_NUM_REG-1);
>     Bus2IP_WrCE                    : in  std_logic_vector(0 to
> C_NUM_REG-1);
>     IP2Bus_Data                    : out std_logic_vector(0 to
> C_SLV_DWIDTH-1);
>     IP2Bus_RdAck                   : out std_logic;
>     IP2Bus_WrAck                   : out std_logic;
>     IP2Bus_Error                   : out std_logic
>     -- DO NOT EDIT ABOVE THIS LINE ---------------------
>   );
>
>   attribute SIGIS : string;
>   attribute SIGIS of Bus2IP_Clk    : signal is "CLK";
>   attribute SIGIS of Bus2IP_Reset  : signal is "RST";
>
> end entity user_logic;
>
> ------------------------------------------------------------------------------
> -- Architecture section
> ------------------------------------------------------------------------------
>
> architecture IMP of user_logic is
>
>   --USER signal declarations added here, as needed for user logic
>
>   ------------------------------------------
>   -- Signals for user logic slave model s/w accessible register
> example
>   ------------------------------------------
>   signal slv_reg0                       : std_logic_vector(0 to
> C_SLV_DWIDTH-1);
>   signal slv_reg_write_sel              : std_logic_vector(0 to 0);
>   signal slv_reg_read_sel               : std_logic_vector(0 to 0);
>   signal slv_ip2bus_data                : std_logic_vector(0 to
> C_SLV_DWIDTH-1);
>   signal slv_read_ack                   : std_logic;
>   signal slv_write_ack                  : std_logic;
>
>   signal cnt:                                   integer range -1000 to 1000:=0;
>   signal direction:   std_logic;
>
> begin
>
>   --USER logic implementation added here
>
>   ------------------------------------------
>   -- Example code to read/write user logic slave model s/w accessible
> registers
>   --
>   -- Note:
>   -- The example code presented here is to show you one way of reading/
> writing
>   -- software accessible registers implemented in the user logic slave
> model.
>   -- Each bit of the Bus2IP_WrCE/Bus2IP_RdCE signals is configured to
> correspond
>   -- to one software accessible register by the top level template.
> For example,
>   -- if you have four 32 bit software accessible registers in the user
> logic,
>   -- you are basically operating on the following memory mapped
> registers:
>   --
>   --    Bus2IP_WrCE/Bus2IP_RdCE   Memory Mapped Register
>   --                     "1000"   C_BASEADDR + 0x0
>   --                     "0100"   C_BASEADDR + 0x4
>   --                     "0010"   C_BASEADDR + 0x8
>   --                     "0001"   C_BASEADDR + 0xC
>   --
>   ------------------------------------------
>   slv_reg_write_sel <= Bus2IP_WrCE(0 to 0);
>   slv_reg_read_sel  <= Bus2IP_RdCE(0 to 0);
>   slv_write_ack     <= Bus2IP_WrCE(0);
>   slv_read_ack      <= Bus2IP_RdCE(0);
>
>   -- Encoder Module Code
> -----------------------------------------------
>
> ----------------------------------------------------------------------
>
>          my_uut1:process(channel_A) is
>     begin
>         if(channel_A 'event and channel_A='1') then
>             direction<= '1' and channel_B;
>         end if;
>     end process;
>
>     my_uut2:process(channel_A) is
>     begin
>         if(channel_A 'event and channel_A='1') then
>             if(direction='0') then
>                 cnt<=cnt+1;
>             else
>                 cnt<=cnt-1;
>             end if;
>         end if;
>     end process;
>
> ----------------------------------------------------------------------
>
> ----------------------------------------------------------------------
>
>   -- implement slave model software accessible register(s)
>   SLAVE_REG_WRITE_PROC : process( Bus2IP_Clk ) is
>   begin
>
>     if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
>       if Bus2IP_Reset = '1' then
>         slv_reg0 <= (others => '0');
>       else
>         case slv_reg_write_sel is
>           when "1" =>
>             for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
>               if ( Bus2IP_BE(byte_index) = '1' ) then
>                 slv_reg0(byte_index*8 to byte_index*8+7) <= Bus2IP_Data
> (byte_index*8 to byte_index*8+7);
>               end if;
>             end loop;
>           when others => null;
>         end case;
>       end if;
>     end if;
>
>   end process SLAVE_REG_WRITE_PROC;
>
>   -- implement slave model software accessible register(s) read mux
>   SLAVE_REG_READ_PROC : process( slv_reg_read_sel, slv_reg0 ) is
>   begin
>
>     case slv_reg_read_sel is
>       when "1" => slv_ip2bus_data <= slv_reg0;
>       when others => slv_ip2bus_data <= (others => '0');
>     end case;
>
>   end process SLAVE_REG_READ_PROC;
>
>   ------------------------------------------
>   -- Example code to drive IP to Bus signals
>   ------------------------------------------
>   --IP2Bus_Data  <= slv_ip2bus_data when slv_read_ack = '1' else
>                   --(others => '0');
>
>   -- my logic--------------------------------------------------------
>
> -------------------------------------------------------------------
>   IP2Bus_Data(0 to 15)  <= (others=>'0');
>   IP2Bus_Data(16 to 31) <= conv_std_logic_vector(cnt,16);
>   -------------------------------------------------------------------
>   -------------------------------------------------------------------
>
>   IP2Bus_WrAck <= slv_write_ack;
>   IP2Bus_RdAck <= slv_read_ack;
>   IP2Bus_Error <= '0';
>
> end IMP;

It looks like IP2Bus_Data is declared 0 to N rather than N downto 0.
This is the signal that goes to the mBlaze, right?  How does uBlaze
declare this?  Have you checked this in simulation?  You should be
able to see what is happening there.   But like I said, I believe you
are doing this wrong.  You are putting the sign bit in the middle of
the 32 bit word.  Is that what you intended?  Is uBlaze reading just a
16 bit quanity or do you need to sign extend the value?

What values *are* being seen in the terminal display?  Are they all
positive?  Do you see *any* negative numbers from this data path?

I also suggest strongly that you replace

use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

with

use ieee.numeric_std.all;

The conversion functions have different names, but they are easy to
remember.  to_integer() works for the types defined in numeric_std
(signed and unsigned).  to_signed() and to_unsigned() work for
integer.  To convert between integer and SLV you need to use
to_integer, to_signed or to_unsigned to convert between integer and
either signed or unsigned, then you can use "implicit type conversion"
to convert between signed/unsigned and SLV.  e.g. std_logic_vector
(signed_signal)

under numeric_std signed, unsigned and SLV are "closely related types"
which do not need a function for conversion.  They will be converted
just by connecting the corresponding "wires" (elements of the array)
between the two types.  Since closely related types use the same
element types, this is defined without requiring any "conversion"
between them.

The reason that you can't convert directly between integer and SLV is
because that would require a specification of the format somehow.  By
converting to unsigned or signed in the middle, the format is
specified clearly.

Rick

Article: 143479
Subject: Re: FPGA ruined (?)
From: austin <austin@xilinx.com>
Date: Mon, 12 Oct 2009 13:16:17 -0700 (PDT)
Links: << >>  << T >>  << A >>
The last device to have a "inrush" current was the Virtex E,

Since then, the parts have no "excess" current requirements.  Now, the
poster may have a design which is using more power than he is able to
supply with his power supply design, so by forcing the part to NOT
configure (change mode pins,  ground the DIN pin, etc.) they will be
able to see if the power supplies can power the part when there is no
bitstream.

While the part waits for a bitstream, the power is virtually identical
to what the power is while loading the bitstream, and what the power
is immediately after the bitstream is loaded, before the part starts
doing whatever it is that the customer has told it to do.


Article: 143480
Subject: Re: integrating chipscope pro in EDK
From: Jim <jimw567@gmail.com>
Date: Mon, 12 Oct 2009 15:18:49 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Oct 12, 12:47=A0pm, Bond <prashant.gyaw...@gmail.com> wrote:
> hello everyone, i have been trying to integrate chipscope pro in the
> EDK using XPS but i didnt find any appropriate tutorials. i am using a
> microblaze processor and a plb bus. Please help me if you could
> suggest some approproate links. i tried to find out such tutorial by
> myself but all of them refered to integrating chipscope using ISE. any
> kind of help would be highly appreciated.
> Prashant

EDK already includes chipscope cores. Look for them under "Debug" in
the "IP Catalog" tab of XPS.

Cheers,
Jim
http://myfpgablog.blogspot.com/

Article: 143481
Subject: Re: How to enter lower boundary character pair within Microsoft
From: rickman <gnuarm@gmail.com>
Date: Mon, 12 Oct 2009 16:15:15 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Oct 12, 2:14=A0pm, Weng Tianxiang <wtx...@gmail.com> wrote:
> On Oct 12, 11:08=A0am, Weng Tianxiang <wtx...@gmail.com> wrote:
>
>
>
> > On Oct 12, 9:07=A0am, rickman <gnu...@gmail.com> wrote:
>
> > > On Oct 11, 8:34=A0pm, Weng Tianxiang <wtx...@gmail.com> wrote:
>
> > > > Hi,
> > > > Please help.
>
> > > > I want to enclose the following equation data n/2**j with a lower
> > > > boundary character pair within Microsoft Office Word 2007.
>
> > > > 0 <=3D i <=3D low_boundary(n/2**j) ;
>
> > > > Thank you.
>
> > > > Weng
>
> > > Have you checked the insert symbol table? =A0If what you need is not
> > > there, try inserting a Microsoft Equation object. =A0Insert, Object,
> > > Create New, Microsoft Equations 3.0 is the process in Word 2003.
>
> > > Rick
>
> > Hi Rick,
> > Thank you. I will try your method. The character pair is not within
> > the insert symbol table.
>
> > Weng- Hide quoted text -
>
> > - Show quoted text -
>
> Hi Rick,
> Sorry. Your method fails. The reason is when to insert a object, it
> needs you entering the characters which I don't know. If I know it, I
> don't have to use the Microsoft Equation.
>
> I think the pair is in some font which I need to know.
>
> Weng

I am not familiar with the term "low boundry".  Can you explain what
you mean by this?  What does the symbol look like?

When I use the Equation editor, I don't need to know *any*
characters.  It gives a toolbar that has various groups of known math
symbols such as a greek epsilon for summation or a pi for products.
It also has symbols for set theory which is where I find the term
"greatest lower bound" used.  That symbol is what I was taught was
called "cap" and looks like an upside down U.  Is that the symbol you
are looking for?

Rick

Article: 143482
Subject: Re: How to enter lower boundary character pair within Microsoft
From: Weng Tianxiang <wtxwtx@gmail.com>
Date: Mon, 12 Oct 2009 18:01:39 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Oct 12, 4:15=A0pm, rickman <gnu...@gmail.com> wrote:
> On Oct 12, 2:14=A0pm, Weng Tianxiang <wtx...@gmail.com> wrote:
>
>
>
>
>
> > On Oct 12, 11:08=A0am, Weng Tianxiang <wtx...@gmail.com> wrote:
>
> > > On Oct 12, 9:07=A0am, rickman <gnu...@gmail.com> wrote:
>
> > > > On Oct 11, 8:34=A0pm, Weng Tianxiang <wtx...@gmail.com> wrote:
>
> > > > > Hi,
> > > > > Please help.
>
> > > > > I want to enclose the following equation data n/2**j with a lower
> > > > > boundary character pair within Microsoft Office Word 2007.
>
> > > > > 0 <=3D i <=3D low_boundary(n/2**j) ;
>
> > > > > Thank you.
>
> > > > > Weng
>
> > > > Have you checked the insert symbol table? =A0If what you need is no=
t
> > > > there, try inserting a Microsoft Equation object. =A0Insert, Object=
,
> > > > Create New, Microsoft Equations 3.0 is the process in Word 2003.
>
> > > > Rick
>
> > > Hi Rick,
> > > Thank you. I will try your method. The character pair is not within
> > > the insert symbol table.
>
> > > Weng- Hide quoted text -
>
> > > - Show quoted text -
>
> > Hi Rick,
> > Sorry. Your method fails. The reason is when to insert a object, it
> > needs you entering the characters which I don't know. If I know it, I
> > don't have to use the Microsoft Equation.
>
> > I think the pair is in some font which I need to know.
>
> > Weng
>
> I am not familiar with the term "low boundry". =A0Can you explain what
> you mean by this? =A0What does the symbol look like?
>
> When I use the Equation editor, I don't need to know *any*
> characters. =A0It gives a toolbar that has various groups of known math
> symbols such as a greek epsilon for summation or a pi for products.
> It also has symbols for set theory which is where I find the term
> "greatest lower bound" used. =A0That symbol is what I was taught was
> called "cap" and looks like an upside down U. =A0Is that the symbol you
> are looking for?
>
> Rick- Hide quoted text -
>
> - Show quoted text -

Hi Rick,
The integer lower boundary function: L(1.2) =3D 1, L(2.5) =3D 2, L(3.999)
=3D 3.

The function drops all data after the decimal point.

The character is a 'L' in left side and a mirror image of 'L' along Y
aixis is in the right side.

Thank you.

Weng

Article: 143483
Subject: Re: Implement ARM cores on a FPGA chip?
From: -jg <jim.granville@gmail.com>
Date: Mon, 12 Oct 2009 18:46:33 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Oct 12, 9:21=A0pm, David Brown <da...@westcontrol.removethisbit.com>
wrote:
>
> Once you have an FPGA on the board, a soft core is almost free.

Only if it uses otherwise unused resource.

If that soft-cpu pushes you UP one FPGA size, it can become expensive
quickly.

The Vendors, of course, like to avoid mentioning such step-effects,
as they WANT to sell you bigger FPGAs !!

Then, there is the 'stone soup' aspect of soft-cpu, - the core may be
'free', but you have to get code into it somehow, and now that code
memory is not free....
-jg

Article: 143484
Subject: How to get clocks from DCM that the duty cycle is not 1:1
From: jay <heavenfish@gmail.com>
Date: Mon, 12 Oct 2009 19:29:48 -0700 (PDT)
Links: << >>  << T >>  << A >>
Hello all,

I have an ASIC design to be converted to FPGA, I'm using Spartan-3A.

The ASIC uses 60MHz input clock, and divides it to 3 20MHz clocks
inside, the duty cycle is not 1:1 and has phase shifting like below:
                     |<-  50ns ->|
     ___           ___           ___
 __/   \___.___/   \___.___/   \___.___.
    .   .   .   .   .   .   .   .   .   .
             _                _               _
  _.___._/ \___.___._/ \___.___._/ \___.
    .   .   .   .   .   .   .   .   .   .
                 _               _                _
  _.___.___/ \_.___.___/ \_.___.___/ \_.
    .   .   .   .   .   .   .   .   .   .

These 3 clocks are the main clocks in the design, so I want to get
them from DCM, but found I can't set duty cycles in DCM.

Now I use logic to divide the clocks and add BUFG after them, but the
skew before BUFG can't be managed.

Is there anyone has a better idea?

Article: 143485
Subject: Re: problem while receiving negative integer in microblaze
From: GrIsH <grishkunwar@gmail.com>
Date: Mon, 12 Oct 2009 22:06:21 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Oct 12, 1:04=A0pm, rickman <gnu...@gmail.com> wrote:
> On Oct 12, 1:08 pm, GrIsH <grishkun...@gmail.com> wrote:
>
> > On Oct 12, 9:02 am, rickman <gnu...@gmail.com> wrote:
>
> > > On Oct 11, 9:05 am, GrIsH <grishkun...@gmail.com> wrote:
>
> > > > I got the problem while receiving the value of "count" (i.e. of
> > > > integer type with value positive as well as negative) in MICROBLAZE
> > > > that was send from custom IP =A0named as encoder module using "User
> > > > Logic Software Register" =A0IPIF. Encoder module counts the value o=
f
> > > > encoder pulses ranges from -5000 to +5000.
>
> > > > I assigned value of =A0 "count" =A0to =A0IP2Bus_Data by converting =
it to
> > > > std_logic_vector type and receive this value in microblaze software
> > > > application using variable "Data_receive" of int type. and
> > > > "Data_received" was displayed into Hyper Terminal But data received
> > > > was not as expecting mainly the negative numbers.....so how this
> > > > problem is resolved to get exact data, positive as well as negative=
.
>
> > > > Can i receive the data in Microblaze application in std_logic_vecto=
r
> > > > form?? i mean std_logic_vector equivalent form....
>
> > > > OR is there any easier method of transferring negative data ...??
>
> > > > Another problem is...... i found SIGNED(N downto 0) is same as
> > > > std_logic_vector except it represents +ve as well as -ve
> > > > numbers....But it didn't work in my program...why??
>
> > > > my code written in "user_logic".vhd template is given below.....
> > > > -------------------------------------------------------------------=
-----------------------------------------------------------
> > > > signal cnt: =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0=
 =A0 =A0 =A0 =A0 integer range -5000 to 5000:=3D0;
>
> > > > =A0my_uut1:process(channel_A) is
> > > > =A0 =A0 begin
> > > > =A0 =A0 =A0 =A0 if(channel_A 'event and channel_A=3D'1') then
> > > > =A0 =A0 =A0 =A0 =A0 =A0 direction<=3D '1' and channel_B;
> > > > =A0 =A0 =A0 =A0 end if;
> > > > =A0 =A0 end process;
>
> > > > =A0 =A0 my_uut2:process(channel_A) is
> > > > =A0 =A0 begin
> > > > =A0 =A0 =A0 =A0 if(channel_A 'event and channel_A=3D'1') then
> > > > =A0 =A0 =A0 =A0 =A0 =A0 if(direction=3D'0') then
> > > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 cnt<=3Dcnt+1;
> > > > =A0 =A0 =A0 =A0 =A0 =A0 else
> > > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 cnt<=3Dcnt-1;
> > > > =A0 =A0 =A0 =A0 =A0 =A0 end if;
> > > > =A0 =A0 =A0 =A0 end if;
> > > > =A0 =A0 end process;
>
> > > > IP2Bus_Data(0 to 15) =A0<=3D (others=3D>'0');
> > > > IP2Bus_Data(16 to 31) <=3D conv_std_logic_vector(cnt,16);
> > > > -------------------------------------------------------------------=
----------------------------------------------------------
> > > > SOFTWARE APPLICATION IN MICROBLAZE
>
> > > > Xint DataRead;
>
> > > > encoder_module_p =3D (Xuint32 *)XPAR_ENCODER_MODULE_0_BASEADDR;
> > > > XASSERT_NONVOID(encoder_module_p !=3D XNULL);
> > > > encoder_module =3D (Xuint32 *)encoder_module_p;
>
> > > > =A0 =A0 =A0 =A0 while(1){
>
> > > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 DataRead =3D ENCODER_MODULE_mReadSl=
aveReg0(encoder_module, 0);
> > > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 xil_printf("Received data: %d\r\n",=
 DataRead);
>
> > > > =A0 =A0 =A0 =A0 }
>
> > > You only included part of your code, I don't see your library
> > > declarations and the other signal declarations. =A0I guess IP2Bus_Dat=
a
> > > is an output maybe?
>
> > > Your problem likely is in the numbering of your bus. =A0How was it
> > > declared, 31 downto 0 (the most common convention) or 0 to 31 (not so
> > > common)? =A0You are assigning the msb of the integer to bit 16 of you=
r
> > > SLV which is in the middle of the vector. =A0I can see why uBlaze is
> > > confused.
>
> > > I also recommend that you not use std_logic_arith. =A0This has been
> > > covered many, many times here and elsewhere. =A0There are some sticky
> > > issues with using this package. =A0It is highly recommended to use
> > > ieee.std_logic_1164 and ieee.numeric_std. =A0I won't go into the deta=
ils
> > > of why this is better, but if you continue to use std_logic_arith
> > > don't say you weren't warned.
>
> > > Rick
>
> > Here is my complete code:
>
> > library ieee;
> > use ieee.std_logic_1164.all;
> > use ieee.std_logic_arith.all;
> > use ieee.std_logic_unsigned.all;
>
> > library proc_common_v2_00_a;
> > use proc_common_v2_00_a.proc_common_pkg.all;
>
> > -- DO NOT EDIT ABOVE THIS LINE --------------------
>
> > --USER libraries added here
>
> > -----------------------------------------------------------------------=
-------
> > -- Entity section
> > -----------------------------------------------------------------------=
-------
> > -- Definition of Generics:
> > -- =A0 C_SLV_DWIDTH =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 -- Slave interface =
data bus width
> > -- =A0 C_NUM_REG =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0-- Number of so=
ftware accessible
> > registers
> > --
> > -- Definition of Ports:
> > -- =A0 Bus2IP_Clk =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 -- Bus to IP cloc=
k
> > -- =A0 Bus2IP_Reset =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 -- Bus to IP reset
> > -- =A0 Bus2IP_Data =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0-- Bus to IP data=
 bus
> > -- =A0 Bus2IP_BE =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0-- Bus to IP by=
te enables
> > -- =A0 Bus2IP_RdCE =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0-- Bus to IP read=
 chip enable
> > -- =A0 Bus2IP_WrCE =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0-- Bus to IP writ=
e chip enable
> > -- =A0 IP2Bus_Data =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0-- IP to Bus data=
 bus
> > -- =A0 IP2Bus_RdAck =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 -- IP to Bus read t=
ransfer
> > acknowledgement
> > -- =A0 IP2Bus_WrAck =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 -- IP to Bus write =
transfer
> > acknowledgement
> > -- =A0 IP2Bus_Error =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 -- IP to Bus error =
response
> > -----------------------------------------------------------------------=
-------
>
> > entity user_logic is
> > =A0 generic
> > =A0 (
> > =A0 =A0 -- ADD USER GENERICS BELOW THIS LINE ---------------
> > =A0 =A0 --USER generics added here
> > =A0 =A0 -- ADD USER GENERICS ABOVE THIS LINE ---------------
>
> > =A0 =A0 -- DO NOT EDIT BELOW THIS LINE ---------------------
> > =A0 =A0 -- Bus protocol parameters, do not add to or delete
> > =A0 =A0 C_SLV_DWIDTH =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 : integer =A0 =
=A0 =A0 =A0 =A0 =A0 =A0:=3D 32;
> > =A0 =A0 C_NUM_REG =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0: integer =
=A0 =A0 =A0 =A0 =A0 =A0 =A0:=3D 1
> > =A0 =A0 -- DO NOT EDIT ABOVE THIS LINE ---------------------
> > =A0 );
> > =A0 port
> > =A0 (
> > =A0 =A0 -- ADD USER PORTS BELOW THIS LINE ------------------
> > =A0 =A0 channel_A: =A0 =A0 =A0 =A0 =A0in std_logic;
> > =A0 =A0 =A0 =A0 =A0channel_B: =A0 =A0 =A0 =A0 =A0 =A0 in std_logic;
> > =A0 =A0 -- ADD USER PORTS ABOVE THIS LINE ------------------
>
> > =A0 =A0 -- DO NOT EDIT BELOW THIS LINE ---------------------
> > =A0 =A0 -- Bus protocol ports, do not add to or delete
> > =A0 =A0 Bus2IP_Clk =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 : in =A0std_=
logic;
> > =A0 =A0 Bus2IP_Reset =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 : in =A0std_lo=
gic;
> > =A0 =A0 Bus2IP_Data =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0: in =A0std_=
logic_vector(0 to
> > C_SLV_DWIDTH-1);
> > =A0 =A0 Bus2IP_BE =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0: in =A0st=
d_logic_vector(0 to
> > C_SLV_DWIDTH/8-1);
> > =A0 =A0 Bus2IP_RdCE =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0: in =A0std_=
logic_vector(0 to
> > C_NUM_REG-1);
> > =A0 =A0 Bus2IP_WrCE =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0: in =A0std_=
logic_vector(0 to
> > C_NUM_REG-1);
> > =A0 =A0 IP2Bus_Data =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0: out std_lo=
gic_vector(0 to
> > C_SLV_DWIDTH-1);
> > =A0 =A0 IP2Bus_RdAck =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 : out std_logi=
c;
> > =A0 =A0 IP2Bus_WrAck =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 : out std_logi=
c;
> > =A0 =A0 IP2Bus_Error =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 : out std_logi=
c
> > =A0 =A0 -- DO NOT EDIT ABOVE THIS LINE ---------------------
> > =A0 );
>
> > =A0 attribute SIGIS : string;
> > =A0 attribute SIGIS of Bus2IP_Clk =A0 =A0: signal is "CLK";
> > =A0 attribute SIGIS of Bus2IP_Reset =A0: signal is "RST";
>
> > end entity user_logic;
>
> > -----------------------------------------------------------------------=
-------
> > -- Architecture section
> > -----------------------------------------------------------------------=
-------
>
> > architecture IMP of user_logic is
>
> > =A0 --USER signal declarations added here, as needed for user logic
>
> > =A0 ------------------------------------------
> > =A0 -- Signals for user logic slave model s/w accessible register
> > example
> > =A0 ------------------------------------------
> > =A0 signal slv_reg0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 : std_l=
ogic_vector(0 to
> > C_SLV_DWIDTH-1);
> > =A0 signal slv_reg_write_sel =A0 =A0 =A0 =A0 =A0 =A0 =A0: std_logic_vec=
tor(0 to 0);
> > =A0 signal slv_reg_read_sel =A0 =A0 =A0 =A0 =A0 =A0 =A0 : std_logic_vec=
tor(0 to 0);
> > =A0 signal slv_ip2bus_data =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0: std_logic_v=
ector(0 to
> > C_SLV_DWIDTH-1);
> > =A0 signal slv_read_ack =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 : std_logic=
;
> > =A0 signal slv_write_ack =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0: std_logic=
;
>
> > =A0 signal cnt: =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0=
 =A0 =A0 =A0 integer range -1000 to 1000:=3D0;
> > =A0 signal direction: =A0 std_logic;
>
> > begin
>
> > =A0 --USER logic implementation added here
>
> > =A0 ------------------------------------------
> > =A0 -- Example code to read/write user logic slave model s/w accessible
> > registers
> > =A0 --
> > =A0 -- Note:
> > =A0 -- The example code presented here is to show you one way of readin=
g/
> > writing
> > =A0 -- software accessible registers implemented in the user logic slav=
e
> > model.
> > =A0 -- Each bit of the Bus2IP_WrCE/Bus2IP_RdCE signals is configured to
> > correspond
> > =A0 -- to one software accessible register by the top level template.
> > For example,
> > =A0 -- if you have four 32 bit software accessible registers in the use=
r
> > logic,
> > =A0 -- you are basically operating on the following memory mapped
> > registers:
> > =A0 --
> > =A0 -- =A0 =A0Bus2IP_WrCE/Bus2IP_RdCE =A0 Memory Mapped Register
> > =A0 -- =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 "1000" =A0 C_BASEADDR + =
0x0
> > =A0 -- =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 "0100" =A0 C_BASEADDR + =
0x4
> > =A0 -- =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 "0010" =A0 C_BASEADDR + =
0x8
> > =A0 -- =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 "0001" =A0 C_BASEADDR + =
0xC
> > =A0 --
> > =A0 ------------------------------------------
> > =A0 slv_reg_write_sel <=3D Bus2IP_WrCE(0 to 0);
> > =A0 slv_reg_read_sel =A0<=3D Bus2IP_RdCE(0 to 0);
> > =A0 slv_write_ack =A0 =A0 <=3D Bus2IP_WrCE(0);
> > =A0 slv_read_ack =A0 =A0 =A0<=3D Bus2IP_RdCE(0);
>
> > =A0 -- Encoder Module Code
> > -----------------------------------------------
>
> > ----------------------------------------------------------------------
>
> > =A0 =A0 =A0 =A0 =A0my_uut1:process(channel_A) is
> > =A0 =A0 begin
> > =A0 =A0 =A0 =A0 if(channel_A 'event and channel_A=3D'1') then
> > =A0 =A0 =A0 =A0 =A0 =A0 direction<=3D '1' and channel_B;
> > =A0 =A0 =A0 =A0 end if;
> > =A0 =A0 end process;
>
> > =A0 =A0 my_uut2:process(channel_A) is
> > =A0 =A0 begin
> > =A0 =A0 =A0 =A0 if(channel_A 'event and channel_A=3D'1') then
> > =A0 =A0 =A0 =A0 =A0 =A0 if(direction=3D'0') then
> > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 cnt<=3Dcnt+1;
> > =A0 =A0 =A0 =A0 =A0 =A0 else
> > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 cnt<=3Dcnt-1;
> > =A0 =A0 =A0 =A0 =A0 =A0 end if;
> > =A0 =A0 =A0 =A0 end if;
> > =A0 =A0 end process;
>
> > ----------------------------------------------------------------------
>
> > ----------------------------------------------------------------------
>
> > =A0 -- implement slave model software accessible register(s)
> > =A0 SLAVE_REG_WRITE_PROC : process( Bus2IP_Clk ) is
> > =A0 begin
>
> > =A0 =A0 if Bus2IP_Clk'event and Bus2IP_Clk =3D '1' then
> > =A0 =A0 =A0 if Bus2IP_Reset =3D '1' then
> > =A0 =A0 =A0 =A0 slv_reg0 <=3D (others =3D> '0');
> > =A0 =A0 =A0 else
> > =A0 =A0 =A0 =A0 case slv_reg_write_sel is
> > =A0 =A0 =A0 =A0 =A0 when "1" =3D>
> > =A0 =A0 =A0 =A0 =A0 =A0 for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
> > =A0 =A0 =A0 =A0 =A0 =A0 =A0 if ( Bus2IP_BE(byte_index) =3D '1' ) then
> > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 slv_reg0(byte_index*8 to byte_index*8+7=
) <=3D Bus2IP_Data
> > (byte_index*8 to byte_index*8+7);
> > =A0 =A0 =A0 =A0 =A0 =A0 =A0 end if;
> > =A0 =A0 =A0 =A0 =A0 =A0 end loop;
> > =A0 =A0 =A0 =A0 =A0 when others =3D> null;
> > =A0 =A0 =A0 =A0 end case;
> > =A0 =A0 =A0 end if;
> > =A0 =A0 end if;
>
> > =A0 end process SLAVE_REG_WRITE_PROC;
>
> > =A0 -- implement slave model software accessible register(s) read mux
> > =A0 SLAVE_REG_READ_PROC : process( slv_reg_read_sel, slv_reg0 ) is
> > =A0 begin
>
> > =A0 =A0 case slv_reg_read_sel is
> > =A0 =A0 =A0 when "1" =3D> slv_ip2bus_data <=3D slv_reg0;
> > =A0 =A0 =A0 when others =3D> slv_ip2bus_data <=3D (others =3D> '0');
> > =A0 =A0 end case;
>
> > =A0 end process SLAVE_REG_READ_PROC;
>
> > =A0 ------------------------------------------
> > =A0 -- Example code to drive IP to Bus signals
> > =A0 ------------------------------------------
> > =A0 --IP2Bus_Data =A0<=3D slv_ip2bus_data when slv_read_ack =3D '1' els=
e
> > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 --(others =3D> '0');
>
> > =A0 -- my logic--------------------------------------------------------
>
> > -------------------------------------------------------------------
> > =A0 IP2Bus_Data(0 to 15) =A0<=3D (others=3D>'0');
> > =A0 IP2Bus_Data(16 to 31) <=3D conv_std_logic_vector(cnt,16);
> > =A0 -------------------------------------------------------------------
> > =A0 -------------------------------------------------------------------
>
> > =A0 IP2Bus_WrAck <=3D slv_write_ack;
> > =A0 IP2Bus_RdAck <=3D slv_read_ack;
> > =A0 IP2Bus_Error <=3D '0';
>
> > end IMP;
>
> It looks like IP2Bus_Data is declared 0 to N rather than N downto 0.
> This is the signal that goes to the mBlaze, right? =A0How does uBlaze
> declare this? =A0Have you checked this in simulation? =A0You should be
> able to see what is happening there. =A0 But like I said, I believe you
> are doing this wrong. =A0You are putting the sign bit in the middle of
> the 32 bit word. =A0Is that what you intended? =A0Is uBlaze reading just =
a
> 16 bit quanity or do you need to sign extend the value?

    As you mentioned above,  IP2Bus_Data  should be declare N downto 0
rather than 0 to N.....I tried this but got the error message
IP2Bus_Data type can not be declared as DOWNTO .......i didn't have
any simulation for this till now and i just check the received number
in hyperterminal.....

This time i hav used 32 bit instead of 16 bit format(i.e.IP2Bus_Data(0
to 31)<=3Dconv_std_logic_vector(cnt,32))  .........
>
> What values *are* being seen in the terminal display? =A0Are they all
> positive? =A0Do you see *any* negative numbers from this data path?

   it shows positive as well as negative numbers but in random
order....

>
> I also suggest strongly that you replace
>
> use ieee.std_logic_arith.all;
> use ieee.std_logic_unsigned.all;
>
> with
>
> use ieee.numeric_std.all;
>
> The conversion functions have different names, but they are easy to
> remember. =A0to_integer() works for the types defined in numeric_std
> (signed and unsigned). =A0to_signed() and to_unsigned() work for
> integer. =A0To convert between integer and SLV you need to use
> to_integer, to_signed or to_unsigned to convert between integer and
> either signed or unsigned, then you can use "implicit type conversion"
> to convert between signed/unsigned and SLV. =A0e.g. std_logic_vector
> (signed_signal)
>
> under numeric_std signed, unsigned and SLV are "closely related types"
> which do not need a function for conversion. =A0They will be converted
> just by connecting the corresponding "wires" (elements of the array)
> between the two types. =A0Since closely related types use the same
> element types, this is defined without requiring any "conversion"
> between them.
>
> The reason that you can't convert directly between integer and SLV is
> because that would require a specification of the format somehow. =A0By
> converting to unsigned or signed in the middle, the format is
> specified clearly.
>

   I tried lots of data types and the conversion function but didn't
get the result what i want......
So iam going to put my problem straight forward to you.......your any
idea will be gr8ly appreciated....

Problem:
1. i need to count the pulses from quadrature encoder , value of count
can be +ve as well as -ve depending upon direction of rotation of
encoder...
2.This value is to be send to uBlaze....
3.I have a code for counting the encoder pulses that is included in
the "user_logic"....
4.I have used "user software register" method of transferring data
from my custom IP to uBlaze..
5.In phase of transferring the value of count from IP to uBlaze, the
value of count must be mapped to IP2Bus_Data in SLV format data
type....
6.Here i had defined "count " that counts value of pulses as integer
and it should be converted SLV while transferring...
7.But this method didn't work as i expected while receiving data in
uBlaze.....
So...Plz suggest me in....

what should be the data type of "count" that support +ve as well -ve
numbers and supports operation count<=3Dcount+1/-1
??
and how -ve values of count are represented in SLV format??



> Rick


Article: 143486
Subject: A simple rs232 CLI
From: colin <colin_toogood@yahoo.com>
Date: Tue, 13 Oct 2009 00:41:41 -0700 (PDT)
Links: << >>  << T >>  << A >>
I'm trying to implement a simple CLI so that I can do some debugging.
I have a microblaze license but I've just taken a look at it and
sledgehammers and nuts come to mind. I then took a look on opencores
and nothing seems quite finished enough (and few with a C compiler).

Does anyone have a suggestion?

Colin

Article: 143487
Subject: Re: FPGA ruined (?)
From: "gkonstan" <paraharaktis@gmail.com>
Date: Tue, 13 Oct 2009 04:19:32 -0500
Links: << >>  << T >>  << A >>
>The last device to have a "inrush" current was the Virtex E,
>
>Since then, the parts have no "excess" current requirements.  Now, the
>poster may have a design which is using more power than he is able to
>supply with his power supply design, so by forcing the part to NOT
>configure (change mode pins,  ground the DIN pin, etc.) they will be
>able to see if the power supplies can power the part when there is no
>bitstream.
>
>While the part waits for a bitstream, the power is virtually identical
>to what the power is while loading the bitstream, and what the power
>is immediately after the bitstream is loaded, before the part starts
>doing whatever it is that the customer has told it to do.
>
>

Actually I had followed the standard procedure, and the code I inserted was
identical to the one that already worked, with the addition of one led
which was supposed to stay always on (and it did, though in lower scale
than supposed). 
Thank you all very much for your help, in the end when I started going
'hardware', unplugging stuff and so, I noticed that the input current of
the board was close to 1,5A, (rather big, isnt it?)so I just told my
supervisor and we are checking if it is possible to find a new Fpga.
Thank you again for your time and trouble.	   
					
---------------------------------------		
This message was sent using the comp.arch.fpga web interface on
http://www.FPGARelated.com

Article: 143488
Subject: Re: integrating chipscope pro in EDK
From: Martin Thompson <martin.j.thompson@trw.com>
Date: Tue, 13 Oct 2009 11:40:25 +0100
Links: << >>  << T >>  << A >>
Bond <prashant.gyawali@gmail.com> writes:

> hello everyone, i have been trying to integrate chipscope pro in the
> EDK using XPS but i didnt find any appropriate tutorials. i am using a
> microblaze processor and a plb bus. Please help me if you could
> suggest some approproate links. i tried to find out such tutorial by
> myself but all of them refered to integrating chipscope using ISE. any
> kind of help would be highly appreciated.

The easiest (IMHO!) is to use the Debug..Debug Configuration menu in XPS
- Click the Add Chipscope peripheral button.

That walks you through the process to a large extent.  Just add an IBA
(bus analyser).  If you just want to monitor bus transations, it's all
done for you in terms of the wiring, and a sensible trigger setup.  It
also handles wiring up the ICON (the controller) to the IBA (the logic
analyser itself - you can have multiple of these).  Doing arbitrary
signals is also possible via the same route.

Make sure the trigger out goes to the debug halt if you want to halt the
processor when chipscope triggers.

Cheers,
Martin

-- 
martin.j.thompson@trw.com 
TRW Conekt - Consultancy in Engineering, Knowledge and Technology
http://www.conekt.net/electronics.html

Article: 143489
Subject: Re: A simple rs232 CLI
From: Martin Thompson <martin.j.thompson@trw.com>
Date: Tue, 13 Oct 2009 11:52:58 +0100
Links: << >>  << T >>  << A >>
colin <colin_toogood@yahoo.com> writes:

> I'm trying to implement a simple CLI so that I can do some debugging.
> I have a microblaze license but I've just taken a look at it and
> sledgehammers and nuts come to mind. I then took a look on opencores
> and nothing seems quite finished enough (and few with a C compiler).
>
> Does anyone have a suggestion?
>

Picoblaze (but that's assembly only..)

If you can fit a sledgehammer (sorry, microblaze :) in, why not use it?
What is it you're trying to do - just wiggle some port pins, or
something more complex?

If it's slow pin/signal wiggling, and alternative might be to use
Chipscope's VIO block - it's not CLI, but I gather it has some tcl
libraries which you could build something with...

Cheers,
Martin

-- 
martin.j.thompson@trw.com 
TRW Conekt - Consultancy in Engineering, Knowledge and Technology
http://www.conekt.net/electronics.html

Article: 143490
Subject: Re: How to get clocks from DCM that the duty cycle is not 1:1
From: Symon <symon_brewer@hotmail.com>
Date: Tue, 13 Oct 2009 12:08:14 +0100
Links: << >>  << T >>  << A >>
jay wrote:
> Hello all,
> 
> I have an ASIC design to be converted to FPGA, I'm using Spartan-3A.
> 
> The ASIC uses 60MHz input clock, and divides it to 3 20MHz clocks
> inside, the duty cycle is not 1:1 and has phase shifting like below:
>                      |<-  50ns ->|
>      ___           ___           ___
>  __/   \___.___/   \___.___/   \___.___.
>     .   .   .   .   .   .   .   .   .   .
>              _                _               _
>   _.___._/ \___.___._/ \___.___._/ \___.
>     .   .   .   .   .   .   .   .   .   .
>                  _               _                _
>   _.___.___/ \_.___.___/ \_.___.___/ \_.
>     .   .   .   .   .   .   .   .   .   .
> 
> These 3 clocks are the main clocks in the design, so I want to get
> them from DCM, but found I can't set duty cycles in DCM.
> 
> Now I use logic to divide the clocks and add BUFG after them, but the
> skew before BUFG can't be managed.
> 
> Is there anyone has a better idea?

Hi Jay,
Clock everything at 60 MHz. Use the 60MHz to make three clock enables 
for your three phase shifted domains.
HTH., Syms.

Article: 143491
Subject: Re: A simple rs232 CLI
From: "colin_toogood@yahoo.com" <colin_toogood@yahoo.com>
Date: Tue, 13 Oct 2009 05:12:34 -0700 (PDT)
Links: << >>  << T >>  << A >>
On 13 Oct, 11:52, Martin Thompson <martin.j.thomp...@trw.com> wrote:
> colin <colin_toog...@yahoo.com> writes:
> > I'm trying to implement a simple CLI so that I can do some debugging.
> > I have a microblaze license but I've just taken a look at it and
> > sledgehammers and nuts come to mind. I then took a look on opencores
> > and nothing seems quite finished enough (and few with a C compiler).
>
> > Does anyone have a suggestion?
>
> Picoblaze (but that's assembly only..)
>
> If you can fit a sledgehammer (sorry, microblaze :) in, why not use it?
> What is it you're trying to do - just wiggle some port pins, or
> something more complex?
>
> If it's slow pin/signal wiggling, and alternative might be to use
> Chipscope's VIO block - it's not CLI, but I gather it has some tcl
> libraries which you could build something with...
>
> Cheers,
> Martin
>
> --
> martin.j.thomp...@trw.com
> TRW Conekt - Consultancy in Engineering, Knowledge and Technologyhttp://www.conekt.net/electronics.html

Martin

Your right, using the VIO block answers the question I posted. I need
to read/write a dozen 32 bit registers. However I ultimately want a
processor at the outermost control loop. I will take a look at using
chipscope for debugging and the Picoblaze at the outer loop. Cludgy in
the short term but ultimately quite elegant.

Colin

Article: 143492
Subject: Handwritten recognition using FPGA
From: "kolopipo" <lanciao5001@yahoo.com>
Date: Tue, 13 Oct 2009 07:15:18 -0500
Links: << >>  << T >>  << A >>
Hi all,

I am doing my final year project on handwritten recognition using FPGA.
For the pre-processing part, I am going to do the following:
i) skew detection and correction
ii) slant detection and correction
iii) character segmentation
iv) size normalization
Then the output will be processed by using Discrete Wavelet Transform and
recognition is done using Fuzzy logic.

May I know how to do pre-processing part? Some guide to do in VHDL will be
very helpful.I had search a lot for VHDL code for pre-processing but to no
avail. Please advise me in any sense.

Thank you



Article: 143493
Subject: difference between virtex 5 and old versin(virtex3,2)
From: "CARLA" <bk_abir@hotmail.com>
Date: Tue, 13 Oct 2009 07:15:36 -0500
Links: << >>  << T >>  << A >>
HI,

why we can estimate the energy consumption whith a virtex5 and not with a
virtex3 or 2 for example? what is this special characteristic?

thank you 



Article: 143494
Subject: FPGA on-die LVDS termination issues
From: "dc207" <jaap.mol@planet.nl>
Date: Tue, 13 Oct 2009 07:15:44 -0500
Links: << >>  << T >>  << A >>
Hello,

We use several source-synchronous LVDS-based interfaces in several PCB
designs, such as a unidirectional interface from several multi-channel ADC
devices (TI ADS725x) towards FPGA (Xilinx Virtex4 family, SX subfamily), or
a full-duplex interface between high-end DSP devices (ADI ADSP-TS201S) and
FPGA (Xilinx Virtex4 family, FX subfamily).
In both mentioned cases, we use on-die LVDS termination on the FPGA side,
e.g. the LVDS receiver side. The used I/O standard is LVDS25, with the
attribute DIFF_TERM set to TRUE. In both cases, the (data)bitrate is about
500 MHz, both using DDR techniques, e.g. the clock-rate is half of this
(250 MHz).
The data-clock provided by the ADCs to FPGAs has a continous nature, the
data-clock provided by the DSPs to the FPGAs is non-continuous, e.g. only
active when there are databits (1 or 4 bits) to be transmitted, else in an
idle state.
In all cases, we have performed SI simulations with IBIS models provided by
the vendors (TI/ADI/Xilinx), and the exact transmission line details
extracted from our PCB layout, e.g. microstrip/vias/stripline, etc. Of
course, the nets have been routed according to the requirements, e.g. with
correct differential impedance, matched lengths, etc. etc.
SI simulation was succesful, simulated eye-diagrams etc. were OK.
Note: the on-die termination resistor (100 ohm) was not included in the
IBIS model of the Xilinx LVDS receiver, and needed to be added manually.
Based on the good simulation results and the overall lack of available PCB
area, we decided to use on-die termination.

On the physical target boards however, we encountered difficulties on these
LVDS interfaces, and the measured signals do not look good at all.
In the time-domain, we are measuring (with Lecroy SDA) RC-like curves on
the (data)signals, when they have been stable (either 0 or 1) for a while
and when they start switching again (to 1 or 0 respectively). 
We are aware that the 100 ohm on-die termination "resistor" is in reality
not a physical resistor between the P- and N terminal(s) of the LVDS
pair(s), at least not in case of FPGA devices.
In reality, both terminals have a Thevenin-equivalent circuit, each
consisting of two other "resistors", one from the terminal upto the I/O
supply voltage, and another downto ground. In reality, these "resistors"
are one or more FETs, switched on/off by the FPGA configuration bitstream
to achieve the right termination scheme for the chosen I/O standard.
We are almost running out of things we can still check, e.g. all FPGA
connections, power supply/integrity, decoupling, trace impedances, FPGA
configuration, etc. etc. 
The FPGA vendor is involved since several weeks now, but they seem to be as
flabbergasted by our observations as we are ourselves.... ;-)


My questions are:

- does anybody as a user of FPGA devices (or LVDS in general) recognize the
observations mentioned above, preferably from own experience/measurements?

- are the assumptions regarding the internal FPGA termination circuits
correct?

- can it be than any non-linearity of the Thevenin FETs causes these
problems?   

- any other brilliant ideas, hints, etc.

Any help is welcome.

Best regards,

Jaap



Article: 143495
Subject: communicating through rs232 in uclinux
From: "sukiminna" <sukiminna@gmail.com>
Date: Tue, 13 Oct 2009 07:15:59 -0500
Links: << >>  << T >>  << A >>
hi guys
i've working on a project for ship classification 
part of it is the communication to send the processed data to base station
via HF communication.
    
since controlling the modem doesnt really need the parallel processing, i
decided to design it using C instead of verilog, so logic elements can be
save for other parts

i don't have any problem designing the controller on nios ide.
to control the rs232 i just have to declare it in SOPCbuilder, and to
access it in C nios, i just open it as a file and read & write to it like
this:
    
    FILE * port;
    port = fopen("/dev/uart","w+"); // rs232 controller is declared in 
                                   // SOPCbuilder as uart
    fprintf(port,"testing"); //writing
    fscanf(port,"%c",&scan_buffer);//reading

but how am i going to access it through uClinux? Do i need to make any
extra step or it will just be the same as this?

i read some forums that said we have to change the stdout/stdin for uclinux
to be channel to uart instead of jtaguart.Is there any other way?

if anybody has any experience on controlling rs232 on uclinux please help
me.
    





Article: 143496
Subject: Problem with Black Box in VHDL in ISE 11.2 :: ERROR:NgdBuild:604
From: "subagha" <subagha@gmail.com>
Date: Tue, 13 Oct 2009 07:16:06 -0500
Links: << >>  << T >>  << A >>
Hi,
  I have a small design in VHDL with black box which i am trying to
synthesize
using Xilinx ISE 11.2. 

I get an error when running the command ngdbuild.
ERROR:NgdBuild:604 - logical block 'inst' with type 'my_block' could not
be
   resolved. A pin name misspelling can cause this, a missing edif or ngc
file,
   or the misspelling of a type name. Symbol 'my_block' is not supported
in
   target 'virtex5'.


The design has two files

my_block.vhd ---
library ieee;
use ieee.std_logic_1164.all;

entity my_block is
    port(I1, I2 : in std_logic;
         O : out std_logic);
end my_block;

architecture tmp of my_block is

begin 

end tmp;


black_box_1.vhd ---

library ieee;
use ieee.std_logic_1164.all;

entity black_box_1 is
    port(DI_1, DI_2 : in std_logic;
         DOUT : out std_logic);
end black_box_1;

architecture archi of black_box_1 is

    component my_block
    port (I1 : in std_logic;
          I2 : in std_logic;
          O : out std_logic);
    end component;
    attribute BOX_TYPE: string;
    attribute BOX_TYPE of my_block: component is "BLACK_BOX";

begin

    inst: my_block port map (I1=>DI_1,I2=>DI_2,O=>DOUT);

end archi;

I am using the commandline to run my commands and not the GUI.

command which generated error:
ngdbuild -intstyle xflow -sd . -dd _ngo -nt timestamp -p xc5vtx240t-2ff1759
black_box_1.ngc black_box_1.ngd

I am a newbie to XST. So your help is most appreciated. Please explain
all the steps i need to do as i am a newbie to XST.I normally use
command line to run the tools so please send across a solution for
command line.

Thanking you in advance

regards,
suba




Article: 143497
Subject: Re: Problem with Black Box in VHDL in ISE 11.2 :: ERROR:NgdBuild:604
From: Alan Fitch <alan.fitch@spamtrap.com>
Date: Tue, 13 Oct 2009 13:56:51 +0100
Links: << >>  << T >>  << A >>
subagha wrote:
> Hi,
>   I have a small design in VHDL with black box which i am trying to
> synthesize
> using Xilinx ISE 11.2. 
> 
> I get an error when running the command ngdbuild.
> ERROR:NgdBuild:604 - logical block 'inst' with type 'my_block' could not
> be
>    resolved. A pin name misspelling can cause this, a missing edif or ngc
> file,
>    or the misspelling of a type name. Symbol 'my_block' is not supported
> in
>    target 'virtex5'.
> 
> 
> The design has two files
> 
> my_block.vhd ---
> library ieee;
> use ieee.std_logic_1164.all;
> 
> entity my_block is
>     port(I1, I2 : in std_logic;
>          O : out std_logic);
> end my_block;
> 
> architecture tmp of my_block is
> 
> begin 
> 
> end tmp;
> 
> 
> black_box_1.vhd ---
> 
> library ieee;
> use ieee.std_logic_1164.all;
> 
> entity black_box_1 is
>     port(DI_1, DI_2 : in std_logic;
>          DOUT : out std_logic);
> end black_box_1;
> 
> architecture archi of black_box_1 is
> 
>     component my_block
>     port (I1 : in std_logic;
>           I2 : in std_logic;
>           O : out std_logic);
>     end component;
>     attribute BOX_TYPE: string;
>     attribute BOX_TYPE of my_block: component is "BLACK_BOX";
> 
> begin
> 
>     inst: my_block port map (I1=>DI_1,I2=>DI_2,O=>DOUT);
> 
> end archi;
> 
> I am using the commandline to run my commands and not the GUI.
> 
> command which generated error:
> ngdbuild -intstyle xflow -sd . -dd _ngo -nt timestamp -p xc5vtx240t-2ff1759
> black_box_1.ngc black_box_1.ngd
> 
> I am a newbie to XST. So your help is most appreciated. Please explain
> all the steps i need to do as i am a newbie to XST.I normally use
> command line to run the tools so please send across a solution for
> command line.
> 
> Thanking you in advance
> 
> regards,
> suba
> 
> 
> 

Hi Suba,

you're not just synthesizing, you're doing place and route as well. The 
place and route fails because it cannot find a file my_block.ngd.

You can't have a black box at place and route, only during synthesis.

regards
Alan



-- 
Alan Fitch
Senior Consultant

Doulos  Developing Design Know-how
VHDL * Verilog * SystemVerilog * SystemC * PSL * Perl * Tcl/Tk * Project 
Services

Doulos Ltd. Church Hatch, 22 Marketing Place, Ringwood, Hampshire, BH24 
1AW, UK
Tel:  + 44 (0)1425 471223		Email: alan.fitch@doulos.com	
Fax:  +44 (0)1425 471573		http://www.doulos.com

------------------------------------------------------------------------

This message may contain personal views which are not the views of 
Doulos, unless specifically stated.

Article: 143498
Subject: Re: ASIC Prototyping using FPGA
From: Test01 <cpandya@yahoo.com>
Date: Tue, 13 Oct 2009 07:12:22 -0700 (PDT)
Links: << >>  << T >>  << A >>
Thanks Gae for detailed response.  This seems to be a big
undertaking.  One of the issue that I see is that the ASIC design team
will be constantly reving the HDL code.  I get the feeling that there
is a fair amount of time needed to convert the asic design that can
work in FPGA.  I am not sure if it is easy to keep up with the latest
code drop from asic design team.  Cadence has emulation hardware
called Palladium.   ASIC to Palladium netlist conversion seems a bit
easier.  It does not require big changes to the design - for example
replacing latches with flipflops, clocking.  Thus asiic to palladium
netlist conversion process is able to keep up with the design team
code drop updates.

Any comments on how this can be as good as Palladium?


Article: 143499
Subject: Re: FPGA on-die LVDS termination issues
From: austin <austin@xilinx.com>
Date: Tue, 13 Oct 2009 07:45:18 -0700 (PDT)
Links: << >>  << T >>  << A >>
Jaap,

The waveforms will look different at any point OTHER than across the
termination.

You can see this for yourself in the simulation, by placing the
package element in the simulation (i.e. two short -- 10-20mm t-lines
before the termination and IO pin loading model).

If you have already done this, then you are aware of where you look
influences what you see.

Looking directly across the termination is what the receiver sees, so
that is what matters.

The termination is not a carbon resistor, but it is as good as one
when it comes to looking like a resistor, so that is not the issue.
Often, the attribute is not set properly, and the resistor is not
enabled.  Have you checked in FPGA_editor, and do you clearly see the
resistor termination enabled?  Does the receive voltage appear twice
as high as it is indicated in the simulation? (clearly indicating the
resistor is not enabled)

You do not mention the problem:  bad data, occasional incorrect data,
bad data when other IOs switch only, etc.

As a customer, the magic words are "lines down."  If you say this, the
case MUST be escalated.  If unresolved, it must be escalated again and
again, until it gets to the "Fire Marshall"  who reports to the Senior
VP and CEO on unresolved cases, and their status.

Since I invented, implemented, this system, and was the first Fire
Marshall, I am very familiar with the system, and it works really well
-- use it!

A case number is very useful:  if you email it to me, I can check on
its status, and help get it escalated.




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