Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarAprMayJunJulAugSepOctNovDec2017
2018JanFebMarAprMayJunJulAugSepOctNovDec2018
2019JanFebMarAprMayJunJulAugSepOctNovDec2019
2020JanFebMarAprMay2020

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search

Messages from 143650

Article: 143650
Subject: Spartan-3A DSP and include a Digital Clock Manager (DCM_SP) - How to
From: "fab." <fabrizio.tappero@gmail.com>
Date: Tue, 20 Oct 2009 03:54:37 -0700 (PDT)
Links: << >>  << T >>  << A >>
Dear All,

I have a Spartan 3A-DSP 3400A board
http://www.xilinx.com/products/devkits/HW-SD3400A-DSP-DB-UNI-G.htm


and a licence for the ISE System Edition.

I am trying to implement the simple stop watch tutorial at page 19 of
the ISE In-depth tutorial at here:
http://www.xilinx.com/support/documentation/sw_manuals/xilinx11/ise11tut.pdf

Unfortunately at page 35 I get stack because the Digital Clock Manager
"Single DCM_SP" does not seem to be available, see screenshot here:
http://topo.epfl.ch/research/indoor_nav/prj_rep/uploads/FpgaRadioPrj/DCM_problem.png


Can somebody please help me out by telling me how to proceed on this
tutorial? am I making a mistake by using a DCM_SP? is this a problem
with my license? unfortunately I have googled this problem in all
possible ways but I found no solution.

best regards
fabrizio


Article: 143651
Subject: Re: Handwritten recognition using FPGA
From: Moazzam <moazzamhussain@gmail.com>
Date: Tue, 20 Oct 2009 05:20:51 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Oct 19, 1:49=C2=A0pm, "jerzy.g...@gmail.com" <jerzy.g...@gmail.com>
wrote:
> On 14 Pa=C5=BA, 16:14, "Nial Stewart"
>
> <nial*REMOVE_TH...@nialstewartdevelopments.co.uk> wrote:
> > > =C2=A0Please advise me in any sense.
>
> > If you've any sense you'll pick a more realistic final year project!
>
> > Sorry to be blunt but from the questions you're asking there's no
> > way you'll get this finished.
>
> > Nial
>
> Why the promotor - lecturer has approved this kind of project?
> Where is the common sense?
> Kolopipo, change the project if you can.
>
> Kind Regards,
>
> Jerzy Gbur

Kolopipo,
I am second to the other posters who responded to your mail. It is a
big challenge for some one who lacks knowledge in advanced digital
design to implement hand writing recognition engine.

But I would suggest you to understand the algorithms and implement
them in Matlab. Xilinx Accel DSP is a very helpful tool for problem
like yours. Without going into the deeper details, you can get your
prototype working hardware on the FPGA.

Hope this helps,


Regards,
Moazzam

Article: 143652
Subject: Re: problem while receiving negative integer in microblaze
From: Martin Thompson <martin.j.thompson@trw.com>
Date: Tue, 20 Oct 2009 13:32:45 +0100
Links: << >>  << T >>  << A >>
rickman <gnuarm@gmail.com> writes:

> On Oct 19, 9:58 am, Gabor <ga...@alacron.com> wrote:
> Are you saying that on the Power PC they number bits in the data bus
> with 0 as msb and 31 as lsb?  How about address bits, is the lsb
> numbered 31 and the msb numbered 0?  

Yes.  And IIRC on the Motorola 88110 which preceded it, on which the
PowerPC 601 was based (buswise anyway).

> I would find that very confusing.
>
> I could care less if the byte addressing is big-endian or little-
> endian.  I don't see that having much import when defining the bits in
> a bus.
>

If you look at address 0, it corresponds with bits 0 to 7 of the data
bus, address 1 is bits 8 to 15.  Just like on a little-endian processor.
(Would you want address 0 on bits 31 downto 24?  Maybe?)

Anyway, once they've taken that convention, making the address bus
numbered the same way makes more sense than making it opposite to the
databus!

(But nothing beats the SHARC DSP booting from an 8 bit EPROM on bits 16-23 of
the 48 bit address bus :)

Cheers,
Martin

-- 
martin.j.thompson@trw.com 
TRW Conekt - Consultancy in Engineering, Knowledge and Technology
http://www.conekt.net/electronics.html

Article: 143653
Subject: Re: xilinx edge trigger interrupt
From: Martin Thompson <martin.j.thompson@trw.com>
Date: Tue, 20 Oct 2009 13:38:02 +0100
Links: << >>  << T >>  << A >>
"hvo" <hai.vo@synrad.com> writes:

> Yes I see the limitation of GPIO interrupts.  There are no parameters to
> set the gpio to only generate an interrupt on a rising or falling edge.  
>
> How else can I connect an external interrupt without using GPIO?  
>

Create an external pin for it - give it an "INTERRUPT" type, and
you can set it to be edge or level triggered, and what polarity it
should be.

You get an MHS line like this for example:
 PORT xps_epc_usb_HC_IRQ = USB_HC_IRQ, DIR = I, SIGIS = INTERRUPT, SENSITIVITY = LEVEL_LOW

Cheers,
Martin

-- 
martin.j.thompson@trw.com 
TRW Conekt - Consultancy in Engineering, Knowledge and Technology
http://www.conekt.net/electronics.html

Article: 143654
Subject: Re: where can price list of FPGA be found?
From: Colin Paul Gloster <Colin_Paul_Gloster@ACM.org>
Date: Tue, 20 Oct 2009 12:49:29 +0000
Links: << >>  << T >>  << A >>
On Mon, 19 Oct 2009, Frank Buss wrote:

|-----------------------------------------------------------------------|
|"> Fist of all I hope to learn the performance/price.                  |
|> Is available a price list for each FPGA device?                      |
|> I find a selection guide on xilinx's websit, and                     |
|> price information is not available. I search it                      |
|> on the internet but no helpful information is                        |
|> found.                                                               |
|                                                                       |
|Try Digikey, it has prices for Xilinx parts. The Altera parts are nice,|
|too, and the prices are in their online shop.                          |
|                                                                       |
|--                                                                     |
|Frank Buss, fb@frank-buss.de                                           |
|http://www.frank-buss.de, http://www.it4-systems.de "                  |
|-----------------------------------------------------------------------|

You could also try
WWW.FPGA-FAQ.com/FPGA_Boards.shtml
to get an idea but it is not for FPGAs on their own and it is probably
old.

Regards,
Colin Paul Gloster

Article: 143655
Subject: Re: problem while receiving negative integer in microblaze
From: Gabor <gabor@alacron.com>
Date: Tue, 20 Oct 2009 06:30:37 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Oct 20, 8:32=A0am, Martin Thompson <martin.j.thomp...@trw.com> wrote:
> rickman <gnu...@gmail.com> writes:
> > On Oct 19, 9:58=A0am, Gabor <ga...@alacron.com> wrote:
> > Are you saying that on the Power PC they number bits in the data bus
> > with 0 as msb and 31 as lsb? =A0How about address bits, is the lsb
> > numbered 31 and the msb numbered 0? =A0
>
> Yes. =A0And IIRC on the Motorola 88110 which preceded it, on which the
> PowerPC 601 was based (buswise anyway).
>
> > I would find that very confusing.
>
> > I could care less if the byte addressing is big-endian or little-
> > endian. =A0I don't see that having much import when defining the bits i=
n
> > a bus.
>
> If you look at address 0, it corresponds with bits 0 to 7 of the data
> bus, address 1 is bits 8 to 15. =A0Just like on a little-endian processor=
.
> (Would you want address 0 on bits 31 downto 24? =A0Maybe?)
>
> Anyway, once they've taken that convention, making the address bus
> numbered the same way makes more sense than making it opposite to the
> databus!
>
> (But nothing beats the SHARC DSP booting from an 8 bit EPROM on bits 16-2=
3 of
> the 48 bit address bus :)
>
> Cheers,
> Martin
>
> --
> martin.j.thomp...@trw.com
> TRW Conekt - Consultancy in Engineering, Knowledge and Technologyhttp://w=
ww.conekt.net/electronics.html

By the way the "hard" big endian numbering was IBM's not Motorola's.
The
Power-PC originated at IBM and was later a joint venture with
Motorola.
Motorola's own processors, 68K series, use a mix of big endian byte
numbering
and little endian bit numbering, so in fact bits 31:24 of a 32-bit
word
on a 32-bit bus would be byte 0.

How did we get on this topic?

Regards,
Gabor

Article: 143656
Subject: Re: License issues
From: Colin Paul Gloster <Colin_Paul_Gloster@ACM.org>
Date: Tue, 20 Oct 2009 13:47:05 +0000
Links: << >>  << T >>  << A >>
On Sun, 18 Oct 2009, Rickman wrote:

|---------------------------------------------------------------------|
|"[..]                                                                |
|[..]  My copy of ispLever from Lattice will                          |
|not run compile or simulate because neither of these tools will run  |
|due to the license expiring.  [..]                                   |
|                                                                     |
|[..]                                                                 |
|                                                                     |
|So now I am trying to use the Xilinx Webpack to allow me to continue |
|working until I can get a new license file, but it won't run either."|
|---------------------------------------------------------------------|

Xilinx Webpack used to be licensed such that it was forbidden to use
it for Lattice FPGAs. I do not recall that prohibition being removed.

|---------------------------------------------------------------------|
|"I think that it somehow is using networking to communicate between  |
|processes and it won't go through the firewall!  Talk about making   |
|simple things difficult!  [..]                                       |
|                                                                     |
|[..]"                                                                |
|---------------------------------------------------------------------|

OpenSolaris had a very complicated way to simulate X-Windows of
GNU/Linux (on top of X-Windows of OpenSolaris) via networking.

Article: 143657
Subject: Re: where can price list of FPGA be found?
From: jogging <joggingsong@gmail.com>
Date: Tue, 20 Oct 2009 08:15:33 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Oct 20, 8:49=A0pm, Colin Paul Gloster <Colin_Paul_Glos...@ACM.org>
wrote:
> On Mon, 19 Oct 2009, Frank Buss wrote:
>
> |-----------------------------------------------------------------------|
> |"> Fist of all I hope to learn the performance/price. =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0|
> |> Is available a price list for each FPGA device? =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 =A0|
> |> I find a selection guide on xilinx's websit, and =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 |
> |> price information is not available. I search it =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 =A0|
> |> on the internet but no helpful information is =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 =A0|
> |> found. =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0=
 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 |
> | =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0=
 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 |
> |Try Digikey, it has prices for Xilinx parts. The Altera parts are nice,|
> |too, and the prices are in their online shop. =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 =A0 =A0|
> | =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0=
 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 |
> |-- =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 |
> |Frank Buss, f...@frank-buss.de =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 |
> |http://www.frank-buss.de,http://www.it4-systems.de" =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0|
> |-----------------------------------------------------------------------|
>
> You could also try
> WWW.FPGA-FAQ.com/FPGA_Boards.shtml
> to get an idea but it is not for FPGAs on their own and it is probably
> old.
>
> Regards,
> Colin Paul Gloster

Thanks for your replies.
Actually I am an DSP software engineer for video codec and image
processing,
but want to master skills to design application with FPGA.
I don't have any application at hand planned to use FPGA.
 At first I hope to know its applications in practical applications
besides in IC design.
I think cost is an important factor when choice is made.

Best Regards
Jogging

Article: 143658
Subject: Re: xilinx edge trigger interrupt
From: "hvo" <hai.vo@synrad.com>
Date: Tue, 20 Oct 2009 10:46:33 -0500
Links: << >>  << T >>  << A >>
>"hvo" <hai.vo@synrad.com> writes:
>
>> Yes I see the limitation of GPIO interrupts.  There are no parameters
to
>> set the gpio to only generate an interrupt on a rising or falling edge. 

>>
>> How else can I connect an external interrupt without using GPIO?  
>>
>
>Create an external pin for it - give it an "INTERRUPT" type, and
>you can set it to be edge or level triggered, and what polarity it
>should be.
>
>You get an MHS line like this for example:
> PORT xps_epc_usb_HC_IRQ = USB_HC_IRQ, DIR = I, SIGIS = INTERRUPT,
SENSITIVITY = LEVEL_LOW
>
>Cheers,
>Martin
>
>-- 
>martin.j.thompson@trw.com 
>TRW Conekt - Consultancy in Engineering, Knowledge and Technology
>http://www.conekt.net/electronics.html
>


Thanks!

That worked for me.  This is definately more versatile than GPIO
interrtupts, and it takes less slices to implement.

Cheers
HV	   
					
---------------------------------------		
This message was sent using the comp.arch.fpga web interface on
http://www.FPGARelated.com

Article: 143659
Subject: Dealing with SPI ADC timings
From: "ElVale" <josedgv@yahoo.com>
Date: Tue, 20 Oct 2009 10:55:57 -0500
Links: << >>  << T >>  << A >>
I'd like to implement an SPI master to read an AD7924 ADC. The thing is
that there are some setup and hold time I have to respect, ie CS'to SCLK
setup time, SCLK to DOUT valid hold time, etc. They go from typically 10 ns
to 50 ns.

What's the best way to implement these delays?



Article: 143660
Subject: Re: Dealing with SPI ADC timings
From: "ElVale" <josedgv@yahoo.com>
Date: Tue, 20 Oct 2009 11:12:32 -0500
Links: << >>  << T >>  << A >>
>I'd like to implement an SPI master to read an AD7924 ADC. The thing is
>that there are some setup and hold time I have to respect, ie CS'to SCLK
>setup time, SCLK to DOUT valid hold time, etc. They go from typically 10
ns
>to 50 ns.
>
>What's the best way to implement these delays?
>
>
>

I mean implementing them in VHDL.	   
					
---------------------------------------		
This message was sent using the comp.arch.fpga web interface on
http://www.FPGARelated.com

Article: 143661
Subject: Re: Dealing with SPI ADC timings
From: Marc Jet <jetmarc@hotmail.com>
Date: Tue, 20 Oct 2009 09:54:53 -0700 (PDT)
Links: << >>  << T >>  << A >>
> What's the best way to implement these delays?

You can easily implement them with a state machine that is clocked
considerably faster than the SPI bit rate.

Article: 143662
Subject: Re: Spartan-3A DSP and include a Digital Clock Manager (DCM_SP) - How to do it?
From: "maxascent" <maxascent@yahoo.co.uk>
Date: Tue, 20 Oct 2009 11:55:56 -0500
Links: << >>  << T >>  << A >>
I have ISE 11.1 and the DCM does exist in the coregen for this release. Is
it not in your version of coregen or is it grayed out? Your image doesnt
seem to work.

Jon	   
					
---------------------------------------		
This message was sent using the comp.arch.fpga web interface on
http://www.FPGARelated.com

From usenet+5@ladybug.xs4all.nl Tue Oct 20 10:36:44 2009
Path: unlimited.newshosting.com!s02-b77!filter01.iad!npeer02.iad.highwinds-media.com!news.highwinds-media.com!feed-me.highwinds-media.com!postnews.google.com!news2.google.com!news.glorb.com!feeder.erje.net!newsfeed.xs4all.nl!newsfeed6.news.xs4all.nl!xs4all!newsgate.cistron.nl!newsgate.news.xs4all.nl!post.news.xs4all.nl!not-for-mail
From: Arlet <usenet+5@ladybug.xs4all.nl>
Subject: Re: Dealing with SPI ADC timings
Date: Tue, 20 Oct 2009 19:36:44 +0200
User-Agent: Pan/0.14.2.91 (As She Crawled Across the Table (Debian GNU/Linux))
Message-Id: <pan.2009.10.20.17.36.43.626195@ladybug.xs4all.nl>
Newsgroups: comp.arch.fpga
References: <to6dnegeVNwQQEDXnZ2dnUVZ_qmdnZ2d@giganews.com>
MIME-Version: 1.0
Content-Type: text/plain; charset=ISO-8859-1
Content-Transfer-Encoding: 8bit
Lines: 11
NNTP-Posting-Host: 213.84.26.192
X-Trace: 1256060204 news.xs4all.nl 83251 [::ffff:213.84.26.192]:37343
X-Complaints-To: abuse@xs4all.nl
Xref: unlimited.newshosting.com comp.arch.fpga:94612
X-Received-Date: Tue, 20 Oct 2009 17:36:44 UTC (s02-b77)

On Tue, 20 Oct 2009 10:55:57 -0500, ElVale wrote:

> I'd like to implement an SPI master to read an AD7924 ADC. The thing is
> that there are some setup and hold time I have to respect, ie CS'to SCLK
> setup time, SCLK to DOUT valid hold time, etc. They go from typically 10 ns
> to 50 ns.
> 
> What's the best way to implement these delays?

If the FPGA is too fast, add some dummy states to your state machine where
you don't change the outputs.

Article: 143663
Subject: Re: Any interest in a group Xilinx FPGA board build/buy ??
From: "nwreader" <noone@home.com>
Date: Tue, 20 Oct 2009 11:03:08 -0700
Links: << >>  << T >>  << A >>
I have foundation so compiling for large FPGAs is not a problem.  There 
seems to me to be a gap between
the exisiting $200/$300 boards & the $2000 and up boards.  This gap is 
probably not big enough
for commercial vendors which is why I asked if other people are interested 
in joining up for a larger
"naked" FPGA board with lot of IOs so that it can be customized for whatever 
usage.  The large FPGAs
really need assembly with X-ray inspection to verify the soldering so doing 
it with manual tools is not
appealing to me. But professional assembly has a large setup charge so doing 
a number of boards is
 necessary to get the per board cost down.

Low cost & fast IO is not a problem, spending the money on the FPGA rather 
than setup charges for PCB &
assembly is the aim for a group buy.

"nwreader" <noone@home.com> wrote in message 
news:BvcCm.1404$MZ1.582@newsfe11.iad...
> Is there any interest in a group buy & design of a Xilinx fpga board ?
> I would like a fairly large Spartan FPGA + lots of IO expansion + low cost 
> $200 - $250 usd.
> The exisiting FPGA boards on the market seems either too expensive or 
> small FPGA or too little
> expansion potential.
>
> The idea is to get a high capacity & low cost expandable board via a group 
> buy to save on the
> PCB + assembly. Probably only for US participants.
> 



Article: 143664
Subject: Teammates, interested?
From: nobody <cydrollinger@gmail.com>
Date: Tue, 20 Oct 2009 11:07:51 -0700 (PDT)
Links: << >>  << T >>  << A >>
Is anyone in this group interested in forming a team of loosely
collected engineers, not of exclusivity but of mutual benefit? I work
alone and have been successful in a few endeavors, but at this pace
things are becoming excruciating. I am thinking that a team could
generate a robust solution to a problem at an accelerated rate by
combining resources of its members. I find myself isolated and need to
reach out to prevent myself from sinking. I am not looking to drag
anyone else down, but am reaching out for stability and stabilization.
Words sometimes really miss the point I am trying to make.
Anyone know what I am talking about.

Sincerely,

Cy Drollinger

Electronic Realization L.L.C.
Bozeman, MT
cy@montana.net
406-586-5502

Article: 143665
Subject: Re: Any interest in a group Xilinx FPGA board build/buy ??
From: nobody <cydrollinger@gmail.com>
Date: Tue, 20 Oct 2009 11:33:43 -0700 (PDT)
Links: << >>  << T >>  << A >>
newbie,

I would be interested. Having just completed a similar project, having
posted a similar topic, and found a lot of interest, what is your
ideal outcome of this project? On the topic of daughter boards what if
the they were connected to themselves board to board like, bga, no
cost?

Cy Drollinger


Article: 143666
Subject: Re: problem while receiving negative integer in microblaze
From: rickman <gnuarm@gmail.com>
Date: Tue, 20 Oct 2009 11:47:21 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Oct 20, 8:32=A0am, Martin Thompson <martin.j.thomp...@trw.com> wrote:
> rickman <gnu...@gmail.com> writes:
> > On Oct 19, 9:58=A0am, Gabor <ga...@alacron.com> wrote:
> > Are you saying that on the Power PC they number bits in the data bus
> > with 0 as msb and 31 as lsb? =A0How about address bits, is the lsb
> > numbered 31 and the msb numbered 0? =A0
>
> Yes. =A0And IIRC on the Motorola 88110 which preceded it, on which the
> PowerPC 601 was based (buswise anyway).
>
> > I would find that very confusing.
>
> > I could care less if the byte addressing is big-endian or little-
> > endian. =A0I don't see that having much import when defining the bits i=
n
> > a bus.
>
> If you look at address 0, it corresponds with bits 0 to 7 of the data
> bus, address 1 is bits 8 to 15. =A0Just like on a little-endian processor=
.
> (Would you want address 0 on bits 31 downto 24? =A0Maybe?)
>
> Anyway, once they've taken that convention, making the address bus
> numbered the same way makes more sense than making it opposite to the
> databus!
>
> (But nothing beats the SHARC DSP booting from an 8 bit EPROM on bits 16-2=
3 of
> the 48 bit address bus :)

Why would I care what the numeric name of the bits for a given byte
are?  I much prefer to be able to determine the weights of each bit
without messy arithmetic.

The part that would really confuse me is if the address bus were
numbered with 0 as the msb.  Do the big endian processors do that as
well?  Is the uBlaze really done this way?

Rick

Article: 143667
Subject: Re: Teammates, interested?
From: "Jon Slaughter" <Jon_Slaughter@Hotmail.com>
Date: Tue, 20 Oct 2009 14:04:56 -0500
Links: << >>  << T >>  << A >>
nobody wrote:
> Is anyone in this group interested in forming a team of loosely
> collected engineers, not of exclusivity but of mutual benefit? I work
> alone and have been successful in a few endeavors, but at this pace
> things are becoming excruciating. I am thinking that a team could
> generate a robust solution to a problem at an accelerated rate by
> combining resources of its members. I find myself isolated and need to
> reach out to prevent myself from sinking. I am not looking to drag
> anyone else down, but am reaching out for stability and stabilization.
> Words sometimes really miss the point I am trying to make.
> Anyone know what I am talking about.
>
> Sincerely,
>
> Cy Drollinger
>
> Electronic Realization L.L.C.
> Bozeman, MT
> cy@montana.net
> 406-586-5502

I was thinking something similar on a global scale. An organization of 
scientists who would group together and work on common problems. People who 
"request" problems to be solved. The idea would be similar to massive 
computing but with humans instead. By having a proper way to organize 
communications it could be very powerful. The organization would be more 
towards theoretical problems but potentially could be for practical issues. 
For example, a company could put out a work order for solving a problem. 
It's not necessarily about money of course but about giving people the 
ability to work together. There is power in numbers... 


Article: 143668
Subject: Re: License issues
From: rickman <gnuarm@gmail.com>
Date: Tue, 20 Oct 2009 12:19:28 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Oct 20, 9:47=A0am, Colin Paul Gloster <Colin_Paul_Glos...@ACM.org>
wrote:
> On Sun, 18 Oct 2009, Rickman wrote:
>
> |---------------------------------------------------------------------|
> |"[..] =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0|
> |[..] =A0My copy of ispLever from Lattice will =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 =A0 =A0|
> |not run compile or simulate because neither of these tools will run =A0|
> |due to the license expiring. =A0[..] =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0=
 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 |
> | =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0=
 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 |
> |[..] =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0=
 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 |
> | =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0=
 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 |
> |So now I am trying to use the Xilinx Webpack to allow me to continue |
> |working until I can get a new license file, but it won't run either."|
> |---------------------------------------------------------------------|
>
> Xilinx Webpack used to be licensed such that it was forbidden to use
> it for Lattice FPGAs. I do not recall that prohibition being removed.

How is this about Lattice FPGAs?  I'm trying to compile VHDL code and
simulate it.

Rick

Article: 143669
Subject: Re: problem while receiving negative integer in microblaze
From: glen herrmannsfeldt <gah@ugcs.caltech.edu>
Date: Tue, 20 Oct 2009 19:21:10 +0000 (UTC)
Links: << >>  << T >>  << A >>
rickman <gnuarm@gmail.com> wrote:
(snip)
 
> Why would I care what the numeric name of the bits for a given byte
> are?  I much prefer to be able to determine the weights of each bit
> without messy arithmetic.
 
> The part that would really confuse me is if the address bus were
> numbered with 0 as the msb.  Do the big endian processors do that as
> well?  Is the uBlaze really done this way?

IBM consistently numbered the MSB 0 on S/360, S/370, XA/370,
ESA/370, ESA/390, and z/Architecture.

Note that z/ is the 64 bit extension, where all general registers
and addresses are now 64 bits.  The 32 bit instructions consistently
operate on bits 32 to 63 of general registers, leaving 0 to 31
unchanged.

Even more, z/ can operate on code using 64, 31, or 24 bit addressing
as appropriate, and instructions change as the addressing mode changes.

It is nice and consistent, and not so hard to get used to.

-- glen

Article: 143670
Subject: Re: problem while receiving negative integer in microblaze
From: rickman <gnuarm@gmail.com>
Date: Tue, 20 Oct 2009 12:30:59 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Oct 20, 3:21=A0pm, glen herrmannsfeldt <g...@ugcs.caltech.edu> wrote:
> rickman <gnu...@gmail.com> wrote:
>
> (snip)
>
> > Why would I care what the numeric name of the bits for a given byte
> > are? =A0I much prefer to be able to determine the weights of each bit
> > without messy arithmetic.
> > The part that would really confuse me is if the address bus were
> > numbered with 0 as the msb. =A0Do the big endian processors do that as
> > well? =A0Is the uBlaze really done this way?
>
> IBM consistently numbered the MSB 0 on S/360, S/370, XA/370,
> ESA/370, ESA/390, and z/Architecture.
>
> Note that z/ is the 64 bit extension, where all general registers
> and addresses are now 64 bits. =A0The 32 bit instructions consistently
> operate on bits 32 to 63 of general registers, leaving 0 to 31
> unchanged.
>
> Even more, z/ can operate on code using 64, 31, or 24 bit addressing
> as appropriate, and instructions change as the addressing mode changes.
>
> It is nice and consistent, and not so hard to get used to.
>
> -- glen

How are the bits in the address bus numbered?  I would find it
extremely confusing to deal with an address where the lsb is numbered
N where N varies depending on the size of the address range.

Rick

Article: 143671
Subject: Re: problem while receiving negative integer in microblaze
From: glen herrmannsfeldt <gah@ugcs.caltech.edu>
Date: Tue, 20 Oct 2009 20:09:21 +0000 (UTC)
Links: << >>  << T >>  << A >>
rickman <gnuarm@gmail.com> wrote:
> On Oct 20, 3:21?pm, glen herrmannsfeldt <g...@ugcs.caltech.edu> wrote:
(snip)

>> IBM consistently numbered the MSB 0 on S/360, S/370, XA/370,
>> ESA/370, ESA/390, and z/Architecture.

(snip)
>> Even more, z/ can operate on code using 64, 31, or 24 bit addressing
>> as appropriate, and instructions change as the addressing mode changes.
 
> How are the bits in the address bus numbered?  I would find it
> extremely confusing to deal with an address where the lsb is numbered
> N where N varies depending on the size of the address range.

If by 'address bus' you mean the physical hardware, that is a separate
question from the architecture.  

Otherwise, the numbering changed in z/, but is internally consistent.

For S/360, 24 bit addresses are in bits 8 to 31 of general registers,
for example, and the address as stored in the PSW is bits 40 to 63.

z/ extended to 64 bits, so 24 bit addresses are in bits 40 to 63,
31 bit in 33 to 63, and 64 bit addresses in bits 0 to 63.

That only comes up in reading the descriptions of the instructions.

In actual coding, (software) one can write a loop in whichever
way one wants.  The hardware will execute it independent of the
thought process of the programmer.

It never confused me.

-- glen

Article: 143672
Subject: External IO Port without using Xilinx's GPIO IP
From: "hvo" <hai.vo@synrad.com>
Date: Tue, 20 Oct 2009 15:16:21 -0500
Links: << >>  << T >>  << A >>
Hi,

I am trying to connect an IO signal from my microblaze to the external
top-level vhdl code without using xilinx GPIO IP.  My question is, couldn't
I make a port definition in the MHS file and connect to it? for example,

PORT Test_IO = Test_IO, DIR = I     // an external port not defined by gpio
ip

and then on my top-level VHDL I would connect to it in the port map by

Test_IO  => somesignal,

My second question is how can I read the signal value in microblaze.  With
xilinx's GPIO, I could read base address to get the value.  But now there's
no base address associated with Test_IO.

Best Regards

HV	   
					
---------------------------------------		
This message was sent using the comp.arch.fpga web interface on
http://www.FPGARelated.com

Article: 143673
Subject: Re: Handwritten recognition using FPGA
From: "ElVale" <josedgv@yahoo.com>
Date: Tue, 20 Oct 2009 16:20:31 -0500
Links: << >>  << T >>  << A >>
>But I would suggest you to understand the algorithms and implement
>them in Matlab. Xilinx Accel DSP is a very helpful tool for problem
>like yours. Without going into the deeper details, you can get your
>prototype working hardware on the FPGA.

I think that's the smartest, fastest way to do it, I've worked with DSP
Builder and Synplify DSP with great results. You may not have a clue of
what's going low level but the job gets done.	   
					
---------------------------------------		
This message was sent using the comp.arch.fpga web interface on
http://www.FPGARelated.com

Article: 143674
Subject: Re: Teammates, interested?
From: "ElVale" <josedgv@yahoo.com>
Date: Tue, 20 Oct 2009 16:29:11 -0500
Links: << >>  << T >>  << A >>
If such organization ever takes place I would recommend strict
implementation of guidelines for coding (like STARC VHDL desing rules,
Aldec ALINT) and documentation (doxigen), so we could all understand each
other easily.	   
					
---------------------------------------		
This message was sent using the comp.arch.fpga web interface on
http://www.FPGARelated.com



Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarAprMayJunJulAugSepOctNovDec2017
2018JanFebMarAprMayJunJulAugSepOctNovDec2018
2019JanFebMarAprMayJunJulAugSepOctNovDec2019
2020JanFebMarAprMay2020

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search