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Messages from 148875

Article: 148875
Subject: Re: We need an administrator for the group to fight spam
From: Peter Alfke <alfke@sbcglobal.net>
Date: Sun, 5 Sep 2010 21:21:33 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Sep 5, 6:31=A0pm, Rob <noth...@nowhere.com> wrote:
> Hi Rich,
>
> What has happened in the last year or so? =A0This group never had this
> much spam when Peter was a regular contributor. =A0I thought perhaps he
> had a hand in keeping this group free from the crap?
>
> Rob

Thanks for the friendly mentioning.
I may have done my part in keeping this newsgroup helpful and perhaps
even friendly, but I had nothing to do with spam suppression.
Now, after having left Xilinx, I just look at this ng occasionally,
and am dismayed by its decay.
Peter Alfke, from home


Article: 148876
Subject: Problems with timing constraints
From: "salimbaba" <a1234573@n_o_s_p_a_m.n_o_s_p_a_m.owlpic.com>
Date: Mon, 06 Sep 2010 06:49:54 -0500
Links: << >>  << T >>  << A >>
Hey, I am facing difficulties in dealing with timing constraints. I have
different sections of my logic running on different clocks. All clocks have
their own timing constraints ,PERIOD and OFFSET IN BEFORE..
the problem is that when i change one of the constraints of one interface
on one clock it also effects the other interface on the 2nd clock with
seperate constrainsts...this varies from run to run,,,,i have also
generated the verbose timing and par report....
 
there is not much difference in the timing values(Slack,Setup,Hold) between
the working bit files and the non working bit files..can anyone plz help
 
 
there are the constraints   
 
 
NET "mclk" TNM_NET = "mclk"; TIMESPEC "TS_mclk" = PERIOD "mclk" 40 ns HIGH
50 %;
 
NET "mclk" TNM_NET = "mclk"; 
 TIMESPEC "TS_mclk" = PERIOD "mclk" 40 ns HIGH 50 %;
 
 
NET "tx_clk_1" TNM_NET = "tx_clk_1";
TIMESPEC "TS_tx_clk_1" = PERIOD "tx_clk_1" 40 ns HIGH 50 %;

INST "write_"  TNM = "mclk_pads";
INST "read_"  TNM = "mclk_pads";
INST "cs"   TNM = "mclk_pads";

INST "d1_stream_data_in_pos_A" TNM = "tx_clk_1_pads";
INST "d1_stream_data_in_neg_A" TNM = "tx_clk_1_pads";
INST "d1_stream_clk_in_pos_A" TNM = "tx_clk_1_pads";

TIMEGRP "mclk_pads" OFFSET = IN 27 ns BEFORE "mclk"  ;
TIMEGRP "tx_clk_1_pads" OFFSET = IN 25 ns BEFORE "tx_clk_1"  ;
ITS IN the last two lines that if i change OFFESET for tx_clk_1 pads it
makes my mclk_pads interface to go hay wire :(	   
					
---------------------------------------		
Posted through http://www.FPGARelated.com

Article: 148877
Subject: Re: We need an administrator for the group to fight spam
From: Thomas Entner <thomas.entner@entner-electronics.com>
Date: Mon, 6 Sep 2010 07:04:06 -0700 (PDT)
Links: << >>  << T >>  << A >>
> and am dismayed by its decay.

I think the main reason for this is because it has lost its "critical
mass". I suppose mainly due to the vendor-supplied forums (like
www.alteraforum.com). The vendor-supplied forums give you better
feedback in most cases...

Thomas

P.S.: And the spam is really annoying...

Article: 148878
Subject: Re: We need an administrator for the group to fight spam
From: Rich Webb <bbew.ar@mapson.nozirev.ten>
Date: Mon, 06 Sep 2010 11:19:02 -0400
Links: << >>  << T >>  << A >>
On Sun, 05 Sep 2010 21:31:12 -0400, Rob <nothear@nowhere.com> wrote:

>What has happened in the last year or so?  This group never had this 
>much spam when Peter was a regular contributor.  I thought perhaps he 
>had a hand in keeping this group free from the crap?

Actually, going back over the logs [*] it looks like the rate of spam in
this group has been decreasing. There was a peak period from late August
until early December 2009 where there were about 50-60 spam postings per
week. By February of this year, the rate had fallen to below 30/wk and
then to the low 'teens and single digits since then. Hardly more than
one/day most recently.

[*] I run Hamster Playground 2.5 as a local server to pre-filter the
news feed, upstream of my news reader. I don't add *every* faux Prada
handbags!!!! posting to the filters but wait until a given spam source
becomes "noticeable," so the true spam rate will be slightly higher than
and to the left of what the logs captured.

-- 
Rich Webb     Norfolk, VA

Article: 148879
Subject: Re: Text compression Huffman Encoder and Decoder
From: "kude" <tadmas09@n_o_s_p_a_m.n_o_s_p_a_m.gmail.com>
Date: Mon, 06 Sep 2010 10:23:49 -0500
Links: << >>  << T >>  << A >>
And can anybody tell me how can I give the input text to the FPGA pls?	   
					
---------------------------------------		
Posted through http://www.FPGARelated.com

Article: 148880
Subject: Re: Text compression Huffman Encoder and Decoder
From: "kude" <tadmas09@n_o_s_p_a_m.n_o_s_p_a_m.gmail.com>
Date: Mon, 06 Sep 2010 11:04:29 -0500
Links: << >>  << T >>  << A >>
And can anybody tell me how can I give the input text to the FPGA pls?	   
					
---------------------------------------		
Posted through http://www.FPGARelated.com

Article: 148881
Subject: Re: We need an administrator for the group to fight spam
From: Peter Alfke <alfke@sbcglobal.net>
Date: Mon, 6 Sep 2010 13:57:41 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Sep 6, 7:04=A0am, Thomas Entner <thomas.ent...@entner-
electronics.com> wrote:
> > and am dismayed by its decay.
>
> I think the main reason for this is because it has lost its "critical
> mass". I suppose mainly due to the vendor-supplied forums (likewww.altera=
forum.com). The vendor-supplied forums give you better
> feedback in most cases...
>
> Thomas
>
> P.S.: And the spam is really annoying...

You can find the Xilinx User Forum at
http://forums.xilinx.com/
Lots of helpful hints and solutions, even without my participation
Peter Alfke

Article: 148882
Subject: Re: We need an administrator for the group to fight spam
From: "langwadt@fonz.dk" <langwadt@fonz.dk>
Date: Mon, 6 Sep 2010 14:42:25 -0700 (PDT)
Links: << >>  << T >>  << A >>
On 6 Sep., 17:19, Rich Webb <bbew...@mapson.nozirev.ten> wrote:
> On Sun, 05 Sep 2010 21:31:12 -0400, Rob <noth...@nowhere.com> wrote:
> >What has happened in the last year or so? =A0This group never had this
> >much spam when Peter was a regular contributor. =A0I thought perhaps he
> >had a hand in keeping this group free from the crap?
>
> Actually, going back over the logs [*] it looks like the rate of spam in
> this group has been decreasing. There was a peak period from late August
> until early December 2009 where there were about 50-60 spam postings per
> week. By February of this year, the rate had fallen to below 30/wk and
> then to the low 'teens and single digits since then. Hardly more than
> one/day most recently.
>
> [*] I run Hamster Playground 2.5 as a local server to pre-filter the
> news feed, upstream of my news reader. I don't add *every* faux Prada
> handbags!!!! posting to the filters but wait until a given spam source
> becomes "noticeable," so the true spam rate will be slightly higher than
> and to the left of what the logs captured.
>

looking at groups.google.com the latest post I see looking like spam
is a reply to something about natural gas for your car from august 13.

that ain't bad

-Lasse

Article: 148883
Subject: Re: Text compression Huffman Encoder and Decoder
From: Stef <stef33d@yahooI-N-V-A-L-I-D.com.invalid>
Date: Tue, 07 Sep 2010 00:55:34 +0200
Links: << >>  << T >>  << A >>
In comp.arch.fpga,
kude <tadmas09@n_o_s_p_a_m.n_o_s_p_a_m.gmail.com> wrote:
> And can anybody tell me how can I give the input text to the FPGA pls?	   

There are lots of options:
- Implement a PS2 interface on the FPGA and connect a PC keyboard
- Connect 2 HEX switches and an Enter key and input ASCII codes
- Implement a serial port on your FPGA and connect to your PC
- If it's written text, you may want to connect a scanner and
  implement OCR
- And many more ...


-- 
Stef    (remove caps, dashes and .invalid from e-mail address to reply by mail)

"People should have access to the data which you have about them.  There should
 be a process for them to challenge any inaccuracies."
-- Arthur Miller

Article: 148884
Subject: Re: Want to get into FPGA
From: Andy <jonesandy@comcast.net>
Date: Tue, 7 Sep 2010 07:40:42 -0700 (PDT)
Links: << >>  << T >>  << A >>
An interesting trend in universtities is to dumb down the bachelors'
degrees (fewer hours required), and then extract more $$ in "graduate"
school to get an MS that only teaches you what you should have been
taught as an undergrad. A BSEE program that does not offer an elective
for FPGA design?!  My father got his BS in Chem Eng in the '50's when
it took over 160 hrs. I got my BSEE in the '80's and it took ~140 hrs.
Now some BSEE programs require only 120-130 hrs, and at a time when
even more specialized courses are required to be productive in any
given area. Too many schools just won't push their students more than
15 hrs per semester. More likely they can't push their professors to
teach as much either.

Andy

Article: 148885
Subject: Re: Want to get into FPGA
From: mac <alexc@theworld.com>
Date: Tue, 07 Sep 2010 23:47:29 -0400
Links: << >>  << T >>  << A >>

> > When I started in electronics it wasn't that way. A
> > technician could learn on the job and grow into an engineering
> > position. But now companies are much more "anal" about having a
> > degree.


They're that way about a lot of things. They've outsourced recruiting to 
someone who only knows how to match keywords.

> Hm, I see that most companies requires BSEE _OR_ MSEE. Its a new
> question on offtopic actually. I am on the last year of my BSEE and
> thinking of not taking MSEE. I believe MSEE is a start way to Ph.D?
> Then whats the point of studying for MSEE?

Some MS degrees are intended to be final, some not. Many weren't 
intended to be, but became so.

It has been said that the BS degree shows that you already know 
something.
A MS degree shows that you can learn new things. This makes you more 
valuable in the long run.
I guess the PhD shows that you didn't get the point.

In terms of FPGAs, the BS might indicate that you can program in a HDL, 
MS that you understand HDLs in general, and PhD that you understand how 
HDLs actually work.

Some employers balk at hiring PhDs, considering them expensive and 
impractical.

-- mac the naf, who didn't get the point, but who is nonetheless cheap 
and practical.

Article: 148886
Subject: Re: We need an administrator for the group to fight spam
From: Ed McGettigan <ed.mcgettigan@xilinx.com>
Date: Wed, 8 Sep 2010 11:03:13 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Sep 4, 2:33=A0am, KingOfDisaster <francescopoder...@googlemail.com>
wrote:
> Hi all,
> this group needs an administrator.
> there is too much spam on it!
> this group was one of the best a few years ago and now it's just a
> damp for spam!
> Who is the current admin? do we have one?
> is anybody =A0willing to be an administrator?
> I'm willing to do as far I'm not alone.
>
> Regards,
> Francesco

Something appears to have been kicked loose with the Google groups
version.  I don't see a single spam related post on the first page of
topics.

Whenever I see a spam post, I go through a couple of the reporting
options and flag it with a single star rating.  If enough other people
are doing the same we may have hit the magic threshold for action.

Ed McGettigan
--
Xilinx Inc.

Article: 148887
Subject: Divide clock by 4/5 in Spartan 3A?
From: Tim Wescott <tim@seemywebsite.com>
Date: Wed, 08 Sep 2010 12:03:33 -0700
Links: << >>  << T >>  << A >>
Part: Xilinx Spartan 3A DSP
Problem:
  (a) My customer has a 100MHz clock, my test board has a 125MHz clock.
  (b) I'm a systems guy who knows enough FPGA designs to turn math
      into HDL, but I'm no FPGA guru.

Solution?

The customer suggested just using Xilinx's DCM wizard to divide the 
clock by 4/5 -- but I don't see where that can be done (I'm using ISE 
11.5, to match my customer's set up).

So -- is there a way to get a clean 100MHz clock from a 125MHz clock 
with the DCM hardware?

I could, I suppose, generate a 250MHz clock then divide it by 3 then 2 
then 3 then 2 etc -- but that's weird, and besides I'd still need 
everything to be good to 8ns rather than 10ns as with a 100MHz clock.

(Or I could just jigger a bunch of constants, which is looking more 
attractive by the second).

-- 

Tim Wescott
Wescott Design Services
http://www.wescottdesign.com

Do you need to implement control loops in software?
"Applied Control Theory for Embedded Systems" was written for you.
See details at http://www.wescottdesign.com/actfes/actfes.html

Article: 148888
Subject: Re: Divide clock by 4/5 in Spartan 3A?
From: Tim Wescott <tim@seemywebsite.com>
Date: Wed, 08 Sep 2010 12:07:09 -0700
Links: << >>  << T >>  << A >>
Divide clock by 5/4.  Oops.

This is why I make a better engineer than the fighter pilot I wanted to 
be.  If you're doing design and you flip a few digits, then you check 
back later and fix -- no problem.  OTOH, get your targeting system 
locked on a bogey, push the big red button, find out it was a transport 
full of brass or civilians -- oopsie, no second tries there!

On 09/08/2010 12:03 PM, Tim Wescott wrote:
> Part: Xilinx Spartan 3A DSP
> Problem:
> (a) My customer has a 100MHz clock, my test board has a 125MHz clock.
> (b) I'm a systems guy who knows enough FPGA designs to turn math
> into HDL, but I'm no FPGA guru.
>
> Solution?
>
> The customer suggested just using Xilinx's DCM wizard to divide the
> clock by 4/5 -- but I don't see where that can be done (I'm using ISE
> 11.5, to match my customer's set up).
>
> So -- is there a way to get a clean 100MHz clock from a 125MHz clock
> with the DCM hardware?
>
> I could, I suppose, generate a 250MHz clock then divide it by 3 then 2
> then 3 then 2 etc -- but that's weird, and besides I'd still need
> everything to be good to 8ns rather than 10ns as with a 100MHz clock.
>
> (Or I could just jigger a bunch of constants, which is looking more
> attractive by the second).
>


-- 

Tim Wescott
Wescott Design Services
http://www.wescottdesign.com

Do you need to implement control loops in software?
"Applied Control Theory for Embedded Systems" was written for you.
See details at http://www.wescottdesign.com/actfes/actfes.html

Article: 148889
Subject: Re: Divide clock by 4/5 in Spartan 3A?
From: glen herrmannsfeldt <gah@ugcs.caltech.edu>
Date: Wed, 8 Sep 2010 19:16:50 +0000 (UTC)
Links: << >>  << T >>  << A >>
Tim Wescott <tim@seemywebsite.com> wrote:
> Divide clock by 5/4.  Oops.

When I read the previous post, I was wondering if it would be
more usual to specify as a multiply than divide.  That is,
multiply by 4/5 or divide by 5/4.

In the case of using a counter to divide by an integer, divide
makes sense.  Also, some time ago Peter Alfke gave a design
for a divide by 2.5 using FF's circuit.  I almost thought that
was what you were asking about, but then I saw the 4.
 
> This is why I make a better engineer than the fighter pilot I wanted to 
> be.  If you're doing design and you flip a few digits, then you check 
> back later and fix -- no problem.  OTOH, get your targeting system 
> locked on a bogey, push the big red button, find out it was a transport 
> full of brass or civilians -- oopsie, no second tries there!

-- glen 

Article: 148890
Subject: clock net placement and routing
From: "Steve Ravet" <steve.ravet@arm.com>
Date: Wed, 8 Sep 2010 14:34:56 -0500
Links: << >>  << T >>  << A >>
I am using ISE 12.2 and targeting virtex6 LX760.  When I take the netlist 
through map I get the following error:

ERROR:Place:1153 - A clock IOB / BUFGCTRL clock component pair have been 
found
   that are not placed at an optimal clock IOB / BUFGCTRL site pair. The 
clock
   IOB component <SWCLKTCK> is placed at site <IOB_X0Y179>. The 
corresponding
   BUFGCTRL component <SWCLKTCK_ibuf> is placed at site <BUFGCTRL_X0Y2>. The
   clock IO can use the fast path between the IOB and the Clock Buffer if a) 
the
   IOB is placed on a Global Clock Capable IOB site that has the fastest
   dedicated path to all BUFGCTRL sites, or b) the IOB is placed on a Local
   Clock Capable IOB site that has dedicated fast path to BUFGCTRL sites in 
its
   half of the device (TOP or BOTTOM). You may want to analyze why this 
problem
   exists and correct it. If this sub optimal condition is acceptable for 
this
   design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .ucf file 
to
   demote this message to a WARNING and allow your design to continue. 
However,
   the use of this override is highly discouraged as it may lead to very 
poor
   timing results. It is recommended that this error condition be corrected 
in
   the design. A list of all the COMP.PINs used in this clock placement rule 
is
   listed below. These examples can be used directly in the .ucf file to
   override this clock rule.
   < NET "SWCLKTCK" CLOCK_DEDICATED_ROUTE = FALSE; >

The clock net is assigned to pin AB37 via a LOC constraint in the .ncf file. 
This corresponds to IOB_X0Y179 listed, which according to the package docs 
is multi-region clock capable.  There is no LOC for the BUFGCTRL, it was 
inserted by the synthesis tool.  So apparently the mapper selected the bad 
location.  I have a webcase open with xilinx on that question.

The workaround would seem to be to assign the BUFG to a compatible location, 
but which ones are?  In FPGA editor I have created nets from AB37 to BUFGs 
in all four groups.  It routed all of them, including to the one the mapper 
complains about, but the nets all have 3-4ns of delay so I think they're on 
general routing resources not clock nets.

I pulled up a different design with properly routed clock nets to compare 
but I don't know enough about the internals to see the difference between 
them.

So, in FPGA editor is there a way to restrict the routing of a net to only 
be on clock nets?  Is there a quicker way of finding out which IOBs and 
BUFGs share fast paths?

thanks,
--steve



Article: 148891
Subject: Re: Divide clock by 4/5 in Spartan 3A?
From: Ed McGettigan <ed.mcgettigan@xilinx.com>
Date: Wed, 8 Sep 2010 14:02:37 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Sep 8, 12:03=A0pm, Tim Wescott <t...@seemywebsite.com> wrote:
> Part: Xilinx Spartan 3A DSP
> Problem:
> =A0 (a) My customer has a 100MHz clock, my test board has a 125MHz clock.
> =A0 (b) I'm a systems guy who knows enough FPGA designs to turn math
> =A0 =A0 =A0 into HDL, but I'm no FPGA guru.
>
> Solution?
>
> The customer suggested just using Xilinx's DCM wizard to divide the
> clock by 4/5 -- but I don't see where that can be done (I'm using ISE
> 11.5, to match my customer's set up).
>
> So -- is there a way to get a clean 100MHz clock from a 125MHz clock
> with the DCM hardware?
>
> I could, I suppose, generate a 250MHz clock then divide it by 3 then 2
> then 3 then 2 etc -- but that's weird, and besides I'd still need
> everything to be good to 8ns rather than 10ns as with a 100MHz clock.
>
> (Or I could just jigger a bunch of constants, which is looking more
> attractive by the second).
>
> --
>
> Tim Wescott
> Wescott Design Serviceshttp://www.wescottdesign.com
>
> Do you need to implement control loops in software?
> "Applied Control Theory for Embedded Systems" was written for you.
> See details athttp://www.wescottdesign.com/actfes/actfes.html

This is easy to do using the Coregen Spartan-3A DCM Wizard.

1) Start CoreGen
2) Create a new project that targets Spartan-3A DSP
3) Select FPGA Features -> Clocking -> Spartan-3A -> Single DCM_SP
core
4) Customize the core with your settings
    - Select the CLKFX output
    - Add 125 MHz as the CLKIN frequency
    - Use the internal feedback mode
    - Use Global buffers for clock outputs
    - Add 100 MHz as the CLKFX output frequency and click Calculate
Values
    - Click Finish to generate your HDL

Ed McGettigan
--
Xilinx Inc.

Article: 148892
Subject: Re: Want to get into FPGA
From: Socrates <mailsoc@gmail.com>
Date: Wed, 8 Sep 2010 16:23:55 -0700 (PDT)
Links: << >>  << T >>  << A >>
> In terms of FPGAs, the BS might indicate that you can program in a HDL,
> MS that you understand HDLs in general, and PhD that you understand how
> HDLs actually work.

Well, thats the point! I would like to go for MSEE somewhere in
Europe. Some people recommends me RWTH @ Germany. Maybe any other
offers in other places? :) I am mainly pointing to FPGA design
studies.



Article: 148893
Subject: Re: Divide clock by 4/5 in Spartan 3A?
From: Tim Wescott <tim@seemywebsite.com>
Date: Wed, 08 Sep 2010 16:51:15 -0700
Links: << >>  << T >>  << A >>
Thanks Ed -- that appears to do what I need.

Now if I can just get the _rest_ of it to work, I'll be fine!

On 09/08/2010 02:02 PM, Ed McGettigan wrote:
> On Sep 8, 12:03 pm, Tim Wescott<t...@seemywebsite.com>  wrote:
>> Part: Xilinx Spartan 3A DSP
>> Problem:
>>    (a) My customer has a 100MHz clock, my test board has a 125MHz clock.
>>    (b) I'm a systems guy who knows enough FPGA designs to turn math
>>        into HDL, but I'm no FPGA guru.
>>
>> Solution?
>>
>> The customer suggested just using Xilinx's DCM wizard to divide the
>> clock by 4/5 -- but I don't see where that can be done (I'm using ISE
>> 11.5, to match my customer's set up).
>>
>> So -- is there a way to get a clean 100MHz clock from a 125MHz clock
>> with the DCM hardware?
>>
>> I could, I suppose, generate a 250MHz clock then divide it by 3 then 2
>> then 3 then 2 etc -- but that's weird, and besides I'd still need
>> everything to be good to 8ns rather than 10ns as with a 100MHz clock.
>>
>> (Or I could just jigger a bunch of constants, which is looking more
>> attractive by the second).
>>
>> --
>>
>> Tim Wescott
>> Wescott Design Serviceshttp://www.wescottdesign.com
>>
>> Do you need to implement control loops in software?
>> "Applied Control Theory for Embedded Systems" was written for you.
>> See details athttp://www.wescottdesign.com/actfes/actfes.html
>
> This is easy to do using the Coregen Spartan-3A DCM Wizard.
>
> 1) Start CoreGen
> 2) Create a new project that targets Spartan-3A DSP
> 3) Select FPGA Features ->  Clocking ->  Spartan-3A ->  Single DCM_SP
> core
> 4) Customize the core with your settings
>      - Select the CLKFX output
>      - Add 125 MHz as the CLKIN frequency
>      - Use the internal feedback mode
>      - Use Global buffers for clock outputs
>      - Add 100 MHz as the CLKFX output frequency and click Calculate
> Values
>      - Click Finish to generate your HDL
>
> Ed McGettigan
> --
> Xilinx Inc.


-- 

Tim Wescott
Wescott Design Services
http://www.wescottdesign.com

Do you need to implement control loops in software?
"Applied Control Theory for Embedded Systems" was written for you.
See details at http://www.wescottdesign.com/actfes/actfes.html

Article: 148894
Subject: Re: We need an administrator for the group to fight spam
From: Robert Miles <robertmilesxyz@gmail.com>
Date: Thu, 9 Sep 2010 03:30:36 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Sep 6, 4:42=A0pm, "langw...@fonz.dk" <langw...@fonz.dk> wrote:
> On 6 Sep., 17:19, Rich Webb <bbew...@mapson.nozirev.ten> wrote:
>
>
>
>
>
> > On Sun, 05 Sep 2010 21:31:12 -0400, Rob <noth...@nowhere.com> wrote:
> > >What has happened in the last year or so? =A0This group never had this
> > >much spam when Peter was a regular contributor. =A0I thought perhaps h=
e
> > >had a hand in keeping this group free from the crap?
>
> > Actually, going back over the logs [*] it looks like the rate of spam i=
n
> > this group has been decreasing. There was a peak period from late Augus=
t
> > until early December 2009 where there were about 50-60 spam postings pe=
r
> > week. By February of this year, the rate had fallen to below 30/wk and
> > then to the low 'teens and single digits since then. Hardly more than
> > one/day most recently.
>
> > [*] I run Hamster Playground 2.5 as a local server to pre-filter the
> > news feed, upstream of my news reader. I don't add *every* faux Prada
> > handbags!!!! posting to the filters but wait until a given spam source
> > becomes "noticeable," so the true spam rate will be slightly higher tha=
n
> > and to the left of what the logs captured.
>
> looking at groups.google.com the latest post I see looking like spam
> is a reply to something about natural gas for your car from august 13.
>
> that ain't bad
>
> -Lasse- Hide quoted text -
>
> - Show quoted text -

Perhaps because I've recently added this newsgroup to those I report
the Google Group spam for.

Article: 148895
Subject: Re: Want to get into FPGA
From: rickman <gnuarm@gmail.com>
Date: Thu, 9 Sep 2010 05:35:10 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Sep 8, 7:23=A0pm, Socrates <mail...@gmail.com> wrote:
> > In terms of FPGAs, the BS might indicate that you can program in a HDL,
> > MS that you understand HDLs in general, and PhD that you understand how
> > HDLs actually work.
>
> Well, thats the point! I would like to go for MSEE somewhere in
> Europe. Some people recommends me RWTH @ Germany. Maybe any other
> offers in other places? :) I am mainly pointing to FPGA design
> studies.

What would you like to learn about FPGAs?  I can't see how FPGAs would
be a topic of study in any level of school, not just graduate school.
FPGAs are where you would apply the general design theory you learn as
an undergraduate, but I don't see how there is anything you could
learn beyond that which would be a topic of "study".  Typically areas
of application are what you learn after you get out of school.

When I got my undergraduate, they taught us Karnaugh maps and various
methods of logic minimization as well as describing how PLAs worked.
But PLAs were a part of one class, not a topic of study.  On the other
hand, I took a class in more advanced logic design techniques which
covered things like string recognizers, state equivalence (in FSMs)
and asynchronous logic, all of which are applicable to PLAs as well as
FPGAs.

What would be the topics of study in FPGA design?  I can't think of
anything I have learned about FPGAs that would be considered college
level material.  Or are you thinking of how to design FPGA
architectures rather than FPGA usage?

I don't see HDL and FPGA as being synonymous as HDLs apply to all
logic devices, not just FPGAs.

Rick

Article: 148896
Subject: Re: We need an administrator for the group to fight spam
From: rickman <gnuarm@gmail.com>
Date: Thu, 9 Sep 2010 05:39:46 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Sep 9, 6:30=A0am, Robert Miles <robertmiles...@gmail.com> wrote:
> On Sep 6, 4:42=A0pm, "langw...@fonz.dk" <langw...@fonz.dk> wrote:
>
>
>
> > On 6 Sep., 17:19, Rich Webb <bbew...@mapson.nozirev.ten> wrote:
>
> > > On Sun, 05 Sep 2010 21:31:12 -0400, Rob <noth...@nowhere.com> wrote:
> > > >What has happened in the last year or so? =A0This group never had th=
is
> > > >much spam when Peter was a regular contributor. =A0I thought perhaps=
 he
> > > >had a hand in keeping this group free from the crap?
>
> > > Actually, going back over the logs [*] it looks like the rate of spam=
 in
> > > this group has been decreasing. There was a peak period from late Aug=
ust
> > > until early December 2009 where there were about 50-60 spam postings =
per
> > > week. By February of this year, the rate had fallen to below 30/wk an=
d
> > > then to the low 'teens and single digits since then. Hardly more than
> > > one/day most recently.
>
> > > [*] I run Hamster Playground 2.5 as a local server to pre-filter the
> > > news feed, upstream of my news reader. I don't add *every* faux Prada
> > > handbags!!!! posting to the filters but wait until a given spam sourc=
e
> > > becomes "noticeable," so the true spam rate will be slightly higher t=
han
> > > and to the left of what the logs captured.
>
> > looking at groups.google.com the latest post I see looking like spam
> > is a reply to something about natural gas for your car from august 13.
>
> > that ain't bad
>
> > -Lasse- Hide quoted text -
>
> > - Show quoted text -
>
> Perhaps because I've recently added this newsgroup to those I report
> the Google Group spam for.

I was reporting spam to Google for a while and I never saw a result of
my efforts.

Rick

Article: 148897
Subject: PSOC3/5
From: rickman <gnuarm@gmail.com>
Date: Thu, 9 Sep 2010 06:11:15 -0700 (PDT)
Links: << >>  << T >>  << A >>
Assuming the PSOC3/5 ever actually comes on the market, should we
consider these to be embedded processors with on board FPGA et. al. or
should we think of them as FPGAs with an on board, hard ARM CM3, et.
al.?

I guess I'm wondering if they will be discussed here much.

Rick

Article: 148898
Subject: Re: Want to get into FPGA
From: Andy <jonesandy@comcast.net>
Date: Thu, 9 Sep 2010 07:25:16 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Sep 9, 7:35=A0am, rickman <gnu...@gmail.com> wrote:
> On Sep 8, 7:23=A0pm, Socrates <mail...@gmail.com> wrote:
>
> > > In terms of FPGAs, the BS might indicate that you can program in a HD=
L,
> > > MS that you understand HDLs in general, and PhD that you understand h=
ow
> > > HDLs actually work.
>
> > Well, thats the point! I would like to go for MSEE somewhere in
> > Europe. Some people recommends me RWTH @ Germany. Maybe any other
> > offers in other places? :) I am mainly pointing to FPGA design
> > studies.
>
> What would you like to learn about FPGAs? =A0I can't see how FPGAs would
> be a topic of study in any level of school, not just graduate school.
> FPGAs are where you would apply the general design theory you learn as
> an undergraduate, but I don't see how there is anything you could
> learn beyond that which would be a topic of "study". =A0Typically areas
> of application are what you learn after you get out of school.
>
> When I got my undergraduate, they taught us Karnaugh maps and various
> methods of logic minimization as well as describing how PLAs worked.
> But PLAs were a part of one class, not a topic of study. =A0On the other
> hand, I took a class in more advanced logic design techniques which
> covered things like string recognizers, state equivalence (in FSMs)
> and asynchronous logic, all of which are applicable to PLAs as well as
> FPGAs.
>
> What would be the topics of study in FPGA design? =A0I can't think of
> anything I have learned about FPGAs that would be considered college
> level material. =A0Or are you thinking of how to design FPGA
> architectures rather than FPGA usage?
>
> I don't see HDL and FPGA as being synonymous as HDLs apply to all
> logic devices, not just FPGAs.
>
> Rick

When I was in college in the early/mid 80's, we learned the Karnaugh
maps, QM methods, etc. and how to implement logic functions with muxes
and decoders and other SSI devices (PALs were still pretty new, and
were addressed in a couple of labs). We did state machines with
registered PROMs. On the job, later in that decade, I learned more
about PALs, and CUPL and ABEL programming. Then the earliest days of
FPGAs were schematic capture, and many of those old SSI design methods
were called upon again, but with more rigid clocking rules. Then HDLs
came along, and we started coding our schematics in VHDL (what I call
netlisting in VHDL), which was only marginally more productive. But
gradually we got more comfortable with higher levels of abstraction in
HDL, and focusing on describing behavior (on a cycle-by-cyle basis)
rather than physical structure, and on more advanced verification
techniques.

My point is, FPGAs are the medium in which much of digital design is
accomplished today, and teaching design techniques that are applicable
to that medium (as opposed to SSIs or PALs) is certainly within the
realm of undergraduate courses, particularly lab courses, where using
an FPGA development board allows students to accomplish much more
complex logic designs in the time available. Even in a non-lab
environment, working with FPGAs, HDLs and testbenches lays a
foundation that I believe should be a part of a good undergraduate
education.

Andy

Article: 148899
Subject: Question about OC PCI Cores
From: "Sink0" <sink00@n_o_s_p_a_m.n_o_s_p_a_m.gmail.com>
Date: Thu, 09 Sep 2010 10:56:47 -0500
Links: << >>  << T >>  << A >>
Hi, i am using a FPGA PCI board on my project. I was looking at OpenCores
and i found 2 interesting cores. PCI_Bridge and PCI_Target (pci32tlite_oc).


Any one here have any experience with one or both boards? Are they
different on performance? Are they reliable? I was looking on OpenCores
forum and a user was having a problem using PCI_Target on Windows. He had
success to use it on Linux (i will be using on Linux too). He was able to
use PCI_Bridge at both OS with no problem but he wrote that PCI_Bridge is
too slow. PCI_Bridge looks so much complete, whay it would be slower? I was
unconfortable using PCI_Target becouse it is VHDL and PCI_Bridge is
Verilog, and i dont have much experience with VHDL (actualy very little).
So what would you guys sugest me? Any comment about both Cores? 

Thank you!! 	   
					
---------------------------------------		
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