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Hi, I am using xiling 9.1 for my design and i am working on 125Mhz system clock. The problem is that i can see the clock on the board and inside FPGA as well but no logic block in my fpga is working. I have no clue about why is it happening because all the timing constraints are met. Kindly give me some pointers, i shall be thankful. Regards Salimbaba --------------------------------------- Posted through http://www.FPGARelated.comArticle: 149101
On Fri, 01 Oct 2010 05:28:41 -0500, "salimbaba" <a1234573@n_o_s_p_a_m.n_o_s_p_a_m.owlpic.com> wrote: >Hi, >I am using xiling 9.1 for my design and i am working on 125Mhz system >clock. The problem is that i can see the clock on the board and inside FPGA >as well but no logic block in my fpga is working. I have no clue about why >is it happening because all the timing constraints are met. Kindly give me >some pointers, i shall be thankful. > > >Regards >Salimbaba > >--------------------------------------- >Posted through http://www.FPGARelated.com Hi Salimbaba, I think we need a little more information in order to give a concrete answer. What kind of FPGA are you using, and how are you distributing the clock within the FPGA? Are you using a DCM to instantiate BUFG's, etc? Regards, KimArticle: 149102
On Oct 1, 6:28=A0am, "salimbaba" <a1234573@n_o_s_p_a_m.n_o_s_p_a_m.owlpic.com> wrote: > Hi, > I am using xiling 9.1 for my design and i am working on 125Mhz system > clock. The problem is that i can see the clock on the board and inside FP= GA > as well but no logic block in my fpga is working. I have no clue about wh= y > is it happening because all the timing constraints are met. Kindly give m= e > some pointers, i shall be thankful. > - Did the simulation run correctly? - Did you check that power at the device is correct? - Do you have multiple clocks in your design? - Is this a new board design or a known working board? You've given so little information, that all one can suggest is the basic checks KJArticle: 149103
o yeah sorry i should've provided you ppl with more info. Well i am using Spartan 3 FPGA (XC3S4000) in my design and it is receiving data from a phy at the clock speed of 125Mhz. I can latch the data at the input which i can see on chipscope, apart from this input signal, i cannot see any other logic block performing. I am not using DCM to instantiate the BUFG's .. i tried that but same problem. >>--------------------------------------- >>Posted through http://www.FPGARelated.com > >Hi Salimbaba, > >I think we need a little more information in order to give a concrete >answer. What kind of FPGA are you using, and how are you distributing >the clock within the FPGA? Are you using a DCM to instantiate BUFG's, >etc? > >Regards, Kim > --------------------------------------- Posted through http://www.FPGARelated.comArticle: 149104
I am running the Xilinx Software Development Kit Release Version:
11.2.00
My system has a Microblaze and is running Xilkernel. I have had good
luck getting my code running with the C compiler, but now I am
transitioning to C++ to allow a pile of C++ to be ported over. As a
first step, I renamed all the .c files to be .cpp and got a successful
compile after a few changes, most notably having to add this to one of
my files:
extern "C" {
void xilkernel_init ();
void xilkernel_start ();
int pthread_attr_setstack(const pthread_attr_t *attr, void
*stackaddr, size_t stacksize);
}
I could not find prototypes for any of these three functions. Shame
shame.
I also changed to this:
extern "C" int main(void)
to make the linker happy.
Now that I have a clean compile, I am trying to debug the results. It
seems that some of
the interrupts and/or calls to semaphores are flakey. Specifically,
the timer interrupt is fine since Xilkernel starts, But I am having
trouble with code associated with my interrupt driven driver for the
serial port. Just interrupts and semaphores involved here; when I run
with the original programmed i/o code everything is fine.
Remember, this all worked when I was compiling with gcc compiler and
failed when I went to g++.
In the past, I have used g++ to compile c code as a "better c
compiler". Better at enforcing
interfaces and requiring prototypes. So, these problems are a bit of
a surprise, especially given that the underlying tools are gnu.
Short of debugging the underlying machine/assembly code, does anyone
have any suggestions?
--
Jack Bonn <> Software Design Labs, Inc.
jack.bonn@swlabs.com (847)526-1337
Dyslexics untie.
Article: 149105On Fri, 01 Oct 2010 05:28:41 -0500, "salimbaba" <a1234573@n_o_s_p_a_m.n_o_s_p_a_m.owlpic.com> wrote: >Hi, >I am using xiling 9.1 for my design and i am working on 125Mhz system >clock. The problem is that i can see the clock on the board and inside FPGA >as well but no logic block in my fpga is working. I have no clue about why >is it happening because all the timing constraints are met. Kindly give me >some pointers, i shall be thankful. Did you simulate your design? Before p&r, after p&r (last resort)? Do you have a reset which is not arriving on hardware? Is clock really arriving into the chip? when you say you can see the clock inside FPGA, what do you mean? Are you forwarding it to a pin which you can probe? -- Muzaffer Kal DSPIA INC. ASIC/FPGA Design Services http://www.dspia.comArticle: 149106
Brian, you are right. Also thanks gabor for the insight, I am right now looking at a chart and trying to figure out worst case timings, and it appears to work, even without duplicating sdrams or having the same data in multiple banks. Something like this: SDRAM @ 125 MHz. - host cpu issues a read for adress 'A'. FPGA propagation delay appr. 12 ns before reaching SDRAM - synchronizing to SDRAM clk costs maximum 1 clk' = 8 ns - 0.5 clk' delay for command to be clocked in to SDRAM - SDRAM cycle 1: ACTIVE adress 'A' - SDRAM cycle 2: NOP - SDRAM cycle 3: READ (2 clk' between ACTIVE and READ fulfills Trcd > 15 ns) - SDRAM cycle 4: ACTIVE adress 'B' for refresh, according to a running refresh counter. (3 clk' between the two actives fullfills Trrd > 15 ns) - SDRAM cycle 5: NOP - SDRAM cycle 5,5: DATA valid (CAS latency = 2) - FPGA propagation delay appr: 12 ns TOTAL SUM: 12+8+4+4,5*8+12 = 72 ns then the next cycle the refresh algorithm could do a precharge for that row. If a read request for an already open row would appear this is no problem since it's just to go on and read then. I will go through this again monday, but so far so good. Good feeling a friday night, again thanks all for this precious help! /JohannesArticle: 149107
On Oct 1, 11:43 am, Johannes <johannesman...@gmail.com> wrote:
> Brian, you are right. Also thanks gabor for the insight, I am right
> now looking at a chart and trying to figure out worst case timings,
> and it appears to work, even without duplicating sdrams or having the
> same data in multiple banks. Something like this:
>
> SDRAM @ 125 MHz.
>
> - host cpu issues a read for adress 'A'. FPGA propagation delay appr.
> 12 ns before reaching SDRAM
> - synchronizing to SDRAM clk costs maximum 1 clk' = 8 ns
> - 0.5 clk' delay for command to be clocked in to SDRAM
> - SDRAM cycle 1: ACTIVE adress 'A'
> - SDRAM cycle 2: NOP
> - SDRAM cycle 3: READ (2 clk' between ACTIVE and READ fulfills Trcd >
> 15 ns)
> - SDRAM cycle 4: ACTIVE adress 'B' for refresh, according to a running
> refresh counter. (3 clk' between the two actives fullfills Trrd > 15
> ns)
> - SDRAM cycle 5: NOP
> - SDRAM cycle 5,5: DATA valid (CAS latency = 2)
> - FPGA propagation delay appr: 12 ns
> TOTAL SUM: 12+8+4+4,5*8+12 = 72 ns
>
> then the next cycle the refresh algorithm could do a precharge for
> that row. If a read request for an already open row would appear this
> is no problem since it's just to go on and read then. I will go
> through this again monday, but so far so good.
>
> Good feeling a friday night, again thanks all for this precious help!
>
> /Johannes
Are you sure you can do a refresh on a currently running read? I'm
not saying you can't, but it seems like it might mess up the read.
You actually have two separate timing constraints. One is the path
you have outlined above, the read access timing. The other is the
SDRAM read cycle and refresh timing. Your FPGA interface timings add
up to 32 ns of the 72 ns total. The SDRAM is only using 40 ns in this
process. That means you can use the other 40 ns (or is it 32 ns?) of
the total cycle time to do the refresh and not have to worry about the
refresh conflicting with the read in progress.
... | NOP | ACTIVE | NOP | READ | NOP | DATA | REFRESH | NOP | ... |
NOP | ACTIVE | ...
^ ^
^
Processor Req Data Output to FPGA
Processor Req
Another advantage of this approach is that you can use the chip wide
auto refresh and don't need to supply the address. You can use an
internal counter to time the refresh interval and just send NOPs in
the idle time until a refresh is required. Heck, I think the timing
may work out to let you run the SDRAM at 100 MHz.
Rick
Article: 149108On Oct 1, 12:29=A0pm, rickman <gnu...@gmail.com> wrote: > On Oct 1, 11:43 am, Johannes <johannesman...@gmail.com> wrote: > > > > > Brian, you are right. Also thanks gabor for the insight, I am right > > now looking at a chart and trying to figure out worst case timings, > > and it appears to work, even without duplicating sdrams or having the > > same data in multiple banks. Something like this: > > > SDRAM @ 125 MHz. > > > - host cpu issues a read for adress 'A'. FPGA propagation delay appr. > > 12 ns before reaching SDRAM > > - synchronizing to SDRAM clk costs maximum 1 clk' =3D 8 ns > > - 0.5 clk' delay for command to be clocked in to SDRAM > > - SDRAM cycle 1: ACTIVE adress 'A' > > - SDRAM cycle 2: NOP > > - SDRAM cycle 3: READ (2 clk' between ACTIVE and READ fulfills Trcd > > > 15 ns) > > - SDRAM cycle 4: ACTIVE adress 'B' for refresh, according to a running > > refresh counter. (3 clk' between the two actives fullfills Trrd > 15 > > ns) > > - SDRAM cycle 5: NOP > > - SDRAM cycle 5,5: DATA valid (CAS latency =3D 2) > > - FPGA propagation delay appr: 12 ns > > TOTAL SUM: 12+8+4+4,5*8+12 =3D 72 ns > > > then the next cycle the refresh algorithm could do a precharge for > > that row. If a read request for an already open row would appear this > > is no problem since it's just to go on and read then. I will go > > through this again monday, but so far so good. > > > Good feeling a friday night, again thanks all for this precious help! > > > /Johannes > > Are you sure you can do a refresh on a currently running read? =A0I'm > not saying you can't, but it seems like it might mess up the read. > You actually have two separate timing constraints. =A0One is the path > you have outlined above, the read access timing. =A0The other is the > SDRAM read cycle and refresh timing. =A0Your FPGA interface timings add > up to 32 ns of the 72 ns total. =A0The SDRAM is only using 40 ns in this > process. =A0That means you can use the other 40 ns (or is it 32 ns?) of > the total cycle time to do the refresh and not have to worry about the > refresh conflicting with the read in progress. > > ... | NOP | ACTIVE | NOP | READ | NOP | DATA | REFRESH | NOP | ... | > NOP | ACTIVE | ... > =A0 =A0 =A0 =A0^ =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 = =A0 =A0 =A0^ > ^ > =A0 =A0 Processor Req =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 Data Output to FPGA > Processor Req > > Another advantage of this approach is that you can use the chip wide > auto refresh and don't need to supply the address. =A0You can use an > internal counter to time the refresh interval and just send NOPs in > the idle time until a refresh is required. =A0Heck, I think the timing > may work out to let you run the SDRAM at 100 MHz. > > Rick The only problem is that the auto-refresh needs to start with all banks precharged. I don't think there's enough time to complete the current cycle including precharge and have an additional Trc for the auto-refresh cycle.Article: 149109
On Oct 1, 2:03=A0pm, Gabor <ga...@alacron.com> wrote: > On Oct 1, 12:29=A0pm, rickman <gnu...@gmail.com> wrote: > > > > > On Oct 1, 11:43 am, Johannes <johannesman...@gmail.com> wrote: > > > > Brian, you are right. Also thanks gabor for the insight, I am right > > > now looking at a chart and trying to figure out worst case timings, > > > and it appears to work, even without duplicating sdrams or having the > > > same data in multiple banks. Something like this: > > > > SDRAM @ 125 MHz. > > > > - host cpu issues a read for adress 'A'. FPGA propagation delay appr. > > > 12 ns before reaching SDRAM > > > - synchronizing to SDRAM clk costs maximum 1 clk' =3D 8 ns > > > - 0.5 clk' delay for command to be clocked in to SDRAM > > > - SDRAM cycle 1: ACTIVE adress 'A' > > > - SDRAM cycle 2: NOP > > > - SDRAM cycle 3: READ (2 clk' between ACTIVE and READ fulfills Trcd > > > > 15 ns) > > > - SDRAM cycle 4: ACTIVE adress 'B' for refresh, according to a runnin= g > > > refresh counter. (3 clk' between the two actives fullfills Trrd > 15 > > > ns) > > > - SDRAM cycle 5: NOP > > > - SDRAM cycle 5,5: DATA valid (CAS latency =3D 2) > > > - FPGA propagation delay appr: 12 ns > > > TOTAL SUM: 12+8+4+4,5*8+12 =3D 72 ns > > > > then the next cycle the refresh algorithm could do a precharge for > > > that row. If a read request for an already open row would appear this > > > is no problem since it's just to go on and read then. I will go > > > through this again monday, but so far so good. > > > > Good feeling a friday night, again thanks all for this precious help! > > > > /Johannes > > > Are you sure you can do a refresh on a currently running read? =A0I'm > > not saying you can't, but it seems like it might mess up the read. > > You actually have two separate timing constraints. =A0One is the path > > you have outlined above, the read access timing. =A0The other is the > > SDRAM read cycle and refresh timing. =A0Your FPGA interface timings add > > up to 32 ns of the 72 ns total. =A0The SDRAM is only using 40 ns in thi= s > > process. =A0That means you can use the other 40 ns (or is it 32 ns?) of > > the total cycle time to do the refresh and not have to worry about the > > refresh conflicting with the read in progress. > > > ... | NOP | ACTIVE | NOP | READ | NOP | DATA | REFRESH | NOP | ... | > > NOP | ACTIVE | ... > > =A0 =A0 =A0 =A0^ =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 = =A0 =A0 =A0 =A0^ > > ^ > > =A0 =A0 Processor Req =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 Data Output to FP= GA > > Processor Req > > > Another advantage of this approach is that you can use the chip wide > > auto refresh and don't need to supply the address. =A0You can use an > > internal counter to time the refresh interval and just send NOPs in > > the idle time until a refresh is required. =A0Heck, I think the timing > > may work out to let you run the SDRAM at 100 MHz. > > > Rick > > The only problem is that the auto-refresh needs to start with all > banks precharged. =A0I don't think there's enough time to complete > the current cycle including precharge and have an additional Trc > for the auto-refresh cycle. Yes, tRC is 60 ns and tRP is 15 ns so the minimum read cycle time is 60 ns at 133 MHz. So you can't use the auto REFRESH with a read in 80 ns. The PRECHARGE to ACTIVE timing requirement convinces me there is no way a second ACTIVATE command can be run to refresh the same bank while it is being read. The refresh will have to be done on a different bank containing the same data and the two banks will need to be ping-ponged to allow refreshing to both. RickArticle: 149110
Hi,
I am a newbie in FPGA realm. They have just bought a Xilinx
Spartan 3E Starter Board in our college. So I am planning to give it a
try. I synthesized some gates, some combinatorial and some sequential
digital circuits.
But if we need to connect some external circuitry to the board what
should I do? I can see many connectors in the board. And what about
the voltage level and isolation?
San.
Article: 149111On a typical SDRAM, you have tRC = 60ns (active to active-time of the same bank) and tRFC = 60ns (auto-refresh-duration). So it will never be possible to do a random-access + a refresh in one 80ns cycle. The only thing that should work, like others already suggested, is to store the data twice in different banks and do the refreshing "by hand", i.e. issuing activate + precharge-commands to every row of every bank (I am not sure if this solution is even officially specified by the SDRAM-manufacturers, altought it should work). So you can refresh one bank while reading the data from the other bank. So reading should be straight forward. Writing is more difficult, as you have to write every data twice to both banks. As you are emulating an EEPROM, there should the possibility to delay the CPU after a write (with a BUSY-bit or something), otherwise it would get very tricky. But as you mentioned that this is a price sensitive application, have you considered to switch to another CPU and/or change something on the firmware-level, as my feeling is that this would result in the most cost effective solution with similar development effort. Thomas www.entner-electronics.comArticle: 149112
If the I/O of the fpga are connected to the connector (you need to check the schematics of the board) then you can choose the IO standard that you want to use. For example you could choose a 3.3V CMOS standard. The FPGA outputs will have no protection so you will need to make sure that whatever you connect to them you make limit the amount of current. So if you put some LEDs on the outputs you would need to add a current limit resistor. This needs to be sized so that you dont exceed the maximum output current (typically around 25mA, but check the data sheet). Jon --------------------------------------- Posted through http://www.FPGARelated.comArticle: 149113
Yeah I studied the Quick Start Guide of Spartan 3E, but it doesn't mentions any I/O. It has got some analog pins, and a big 100 pin Hirose port. If I need to get some input form external circuit(say digitized sensor data) how can I interface it with the board? San.Article: 149114
>Yeah I studied the Quick Start Guide of Spartan 3E, but it doesn't >mentions any I/O. It has got some analog pins, and a big 100 pin >Hirose port. If I need to get some input form external circuit(say >digitized sensor data) how can I interface it with the board? > >San. > Without knowing what board you have I cant say exactly, but I guess that the connector has some of its pins connected to the fpga pins. You need to look at the schematics for the board. The fpga has IO banks which means a group of pins on the fpga will be related to an IO voltage. You may be able to set this voltage or it may be hard wired on the board. When you connect your sensor to the board you need to make sure that the output of the sensor matches the IO standard of the fpga pin. So if the sensor outputs 3.3V cmos logic then the fpga pin needs to be set to accept that type of sigmal. If the IO voltage on the fpga is set to something different than say 3.3V and you cant alter it on the fpga board then you may need a level translator chip. Jon --------------------------------------- Posted through http://www.FPGARelated.comArticle: 149115
"salimbaba" <a1234573@n_o_s_p_a_m.n_o_s_p_a_m.owlpic.com> wrote in message news:DqydnWwUoM5EKjjRnZ2dnUVZ_oCdnZ2d@giganews.com... > Hi, > I am using xiling 9.1 for my design and i am working on 125Mhz system > clock. The problem is that i can see the clock on the board and inside > FPGA > as well but no logic block in my fpga is working. I have no clue about why > is it happening because all the timing constraints are met. Kindly give me > some pointers, i shall be thankful. Learn the basics of the fpga editor. Here you can quickly find out if your design has been optimized out for some reason. It is also possible to track signals and add TP's internally with this and just rebuild the bitfile.Article: 149116
Morten Leikvoll wrote: > Learn the basics of the fpga editor. Here you can quickly find out if your > design has been optimized out for some reason. It is also possible to track > signals and add TP's internally with this and just rebuild the bitfile. I never needed to use a FPGA editor, but it is important to read and understand all the warnings and trying to reduce it to 0 warnings (not always possible, but e.g. in Quartus you can suppress unimportant warnings to see new important ones). -- Frank Buss, http://www.frank-buss.de piano and more: http://www.youtube.com/user/frankbussArticle: 149117
Frank Buss <fb@frank-buss.de> wrote: >Morten Leikvoll wrote: > >> Learn the basics of the fpga editor. Here you can quickly find out if your >> design has been optimized out for some reason. It is also possible to track >> signals and add TP's internally with this and just rebuild the bitfile. > >I never needed to use a FPGA editor, but it is important to read and >understand all the warnings and trying to reduce it to 0 warnings (not >always possible, but e.g. in Quartus you can suppress unimportant warnings >to see new important ones). I doubt it is possible to have an fpga design without warnings using Xilinx's software. First thing to check is whether the done pin and other programming pins are indicating the configuration is properly loaded. If that is OK I'd create an output signal which is the clock divided by 256 or so to check whether the design is at least doing something. -- Failure does not prove something is impossible, failure simply indicates you are not using the right tools... nico@nctdevpuntnl (punt=.) --------------------------------------------------------------Article: 149118
On 07/16/2010 09:07 AM, Nicolas Matringe wrote: > On 15 juil, 10:08, Nicolas Matringe<nic_o_...@msn.com> wrote: >> Hello >> I've been trying to download these 2.9GB for 3 days with numerous >> retries (thanks to the download manager, the 'resume' resulted in a >> restart from 0) and when I finally managed to get the full file it was >> corrupted. > > I finally managed to get the full file in running order after another > 6 hours download, now I'm installing it. Love to know the secret. Just tried to download 12.2 and received this: Message from the NSAPI plugin: No backend server available for connection: timed out after 10 seconds or idempotent set to OFF. Build date/time: May 1 2006 12:12:04 Change Number: 755164Article: 149119
On Sun, 03 Oct 2010 13:37:34 -0400, Steven Hirsch <snhirsch@gmail.com> wrote: >On 07/16/2010 09:07 AM, Nicolas Matringe wrote: >> On 15 juil, 10:08, Nicolas Matringe<nic_o_...@msn.com> wrote: >>> Hello >>> I've been trying to download these 2.9GB for 3 days with numerous >>> retries (thanks to the download manager, the 'resume' resulted in a >>> restart from 0) and when I finally managed to get the full file it was >>> corrupted. >> >> I finally managed to get the full file in running order after another >> 6 hours download, now I'm installing it. > >Love to know the secret. Just tried to download 12.2 and received this: > > > >Message from the NSAPI plugin: > >No backend server available for connection: timed out after 10 seconds or >idempotent set to OFF. > > >Build date/time: May 1 2006 12:12:04 > >Change Number: 755164 > There is an announcement on xilinx.com front-page which says parts of the site would be unavailable from 6:00am to 3:00pm PST. That might be your problem. Anyway, they are coming out with 12.3 on tuesday so it might be a better idea to wait for that. -- Muzaffer Kal DSPIA INC. ASIC/FPGA Design Services http://www.dspia.comArticle: 149120
>On Oct 1, 6:28=A0am, "salimbaba" ><a1234573@n_o_s_p_a_m.n_o_s_p_a_m.owlpic.com> wrote: >> Hi, >> I am using xiling 9.1 for my design and i am working on 125Mhz system >> clock. The problem is that i can see the clock on the board and inside FP= >GA >> as well but no logic block in my fpga is working. I have no clue about wh= >y >> is it happening because all the timing constraints are met. Kindly give m= >e >> some pointers, i shall be thankful. >> > >- Did the simulation run correctly? >- Did you check that power at the device is correct? >- Do you have multiple clocks in your design? >- Is this a new board design or a known working board? > >You've given so little information, that all one can suggest is the >basic checks > >KJ > Hi KJ, yeah i successfully simulated the design first and the device power up is also correct. Actually there are 4 clocks coming to the fpga, 2 from ethernet PHY and 2 from oscillators. I am latching the data on the PHY clocks and my whole design is also working on them but i cannot see anything happening =( . and well i have tested this board on 100 Mbps connectivity but now i am testing it on 1Gbps but so far i haven't been able to make it work even a bit. It did work the very first time i programmed it, but when i re-synthesized and reimplemented to make sure it works, it stopped working. Probably different PAR. Any guesses ?any pointers ? Also when i take out some debug signals on Chipscope for debugging purposes, sometimes my design stops working but on removal of those signals it starts working again, do u know its reason ? thanks SalimBaba --------------------------------------- Posted through http://www.FPGARelated.comArticle: 149121
>On Fri, 01 Oct 2010 05:28:41 -0500, "salimbaba" ><a1234573@n_o_s_p_a_m.n_o_s_p_a_m.owlpic.com> wrote: > >>Hi, >>I am using xiling 9.1 for my design and i am working on 125Mhz system >>clock. The problem is that i can see the clock on the board and inside FPGA >>as well but no logic block in my fpga is working. I have no clue about why >>is it happening because all the timing constraints are met. Kindly give me >>some pointers, i shall be thankful. > >Did you simulate your design? Before p&r, after p&r (last resort)? Do >you have a reset which is not arriving on hardware? Is clock really >arriving into the chip? when you say you can see the clock inside >FPGA, what do you mean? Are you forwarding it to a pin which you can >probe? >-- >Muzaffer Kal > >DSPIA INC. >ASIC/FPGA Design Services > Hi muzaffar, yes i have simulated my design and it works fine. i'll have to see the reset signal,i'll check it tomorrow morning and yes the clock is coming into the chip, i have checked it on Oscilloscope, and i used the data sampling clock as the chipscope master clock so yeah it is coming on chip. and i'll have to confirm the last point by forwarding it to some test point. I'll update it in the morning mate. Thanks a lot =) >http://www.dspia.com > --------------------------------------- Posted through http://www.FPGARelated.comArticle: 149122
Hello. I'm currently coming to the end of my last semester of my four year engineering degree in electronics and computer systems engineering. I've really enjoyed working with FPGAs as part of my degree and am now tutoring the FPGA course. Basically I want to start a career working with FPGAs, but am not sure how to go about it. I live in New Zealand, but as the job market here is so small I'm looking at Europe (as I speak both English and German I figure that opens up several countries I could work in). Does anyone have any suggestions or advice as to how I go about entering such a career, or what kind of options are out there, or even websites I can look for jobs on? Thanks in advance. - AlexanderArticle: 149123
On Oct 2, 7:33=A0am, Santosh <santos...@gmail.com> wrote: > Hi, > =A0 =A0 I am a newbie in FPGA realm. They have just bought a Xilinx > Spartan 3E Starter Board in our college. So I am planning to give it a > try. I synthesized some gates, some combinatorial and some sequential > digital circuits. > But if we need to connect some external circuitry to the board what > should I do? I can see many connectors in the board. And what about > the voltage level and isolation? > > San. Those boards are made by Digilent. You might check and see if they have a breadboard with the Hirose connector on it.Article: 149124
another thing is that when i don't put any kind of logic in my design i.e. simple sampling the data coming from phy and on negedge forwarding it, it works fine but as soon as i add extra logic for the complete functioning, it stops working. --------------------------------------- Posted through http://www.FPGARelated.com
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