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>>On Oct 13, 6:50=A0pm, "PaulHam" >><hamsdeji@n_o_s_p_a_m.n_o_s_p_a_m.gmail.com> wrote: >>> >> It's unbelievable and different from theasmi_paralleldata sheet. >>> >> The data sheet shows that only 3 us is needed after single byte >write >>> >> operation. >>> >> So, I'd like to get some advice here what makes unexpected result. >>> >> The signals I giveasmi_parallelip core, the write/wren/addr/data are >>> >> exact. >>> >>> >I'd check the data sheet for whatever flash device you're using, that >>> will >>> >be what determines the delay (mostly), not the core. >>> >>> >Nial. >>> >>> Thanks for checking my question. >>> You mean, the Serial Configuration Device determines the speed of >writing >>> ? >>> >>> Paul. >>> >>> --------------------------------------- =A0 =A0 =A0 =A0 >>> Posted throughhttp://www.FPGARelated.com >> >>Hi Paul, >> >>Take note that the waveforms in the ALTASMI_PARALLEL user guide do not >>reflect the real time operation. Just like Nial said, the speed of >>writing depends on the flash device used. >> >>When the IP receives any write command (either byte write or page >>write), it will follow this procedure: >>- Stage 1: read status register >>- Stage 2: issue write enable command >>- Stage 3: write data >>- Stage 4: read busy bit from status register to end operation >>If you are using single byte write, only 1 byte of data is sent at >>stage 3 and repeat the process for the subsequent bytes. When page >>write is used, the whole bunch of data can be transferred one shot in >>stage 3. So if you are using single byte write to write a bunch of >>data, it will definitely take longer time. The single byte write >>shouldn't take longer time than page write if only 1 byte of data is >>transferred. As for the 300us delay, is it the time taken to write a >>bunch of data or you are just transferring a single byte? >> > > > >Thanks for your concern. >I understand 4 step stage you said. >But I compare the only single byte "busy delay" with page(bunch) write. >Every single byte write makes 300us "busy delay". >So entirely, a single byte write takes (300us X 256)us differently with >30us of page write. > >As you said, single byte write shouldnot take longer time than page write. >However, I found that they are quitely different. > >Actually, I use the EPCS4 as serial configuration device. >But I think EPCS4,16,64,... have almost same performance >except of flash memory size. > >I'm trying to find the missing point at that project today. >But I have a confidence due to your help & advice. > >Thanks >Paul > > >--------------------------------------- >Posted through http://www.FPGARelated.com > I found my fault. The busy time delay of page write is longer than single byte write. It was probed about 440us by oscilloscope. However, the busy time delay of single byte write is still too longer(300us) than datasheet(3us). --------------------------------------- Posted through http://www.FPGARelated.comArticle: 149376
Hello all, I need to change a design that I have done years ago in Spartan XCS05 devices. Unfortunately I have failed to install software that is capable to do this. I found an old carton containing ISE 4.1i, could install this but the FPGA Express License that is included in it is expired (according to FLEX utility) in 2003. Downloaded Webpack 4.1 and 4.2, but they do not support the Spartan device. Downloaded "Xilinx Spartan 4k 4.2", but that does require third party software for synthesis. Does anyone know if it is still possible to synthesise for a Spartan device? Thanks, ThomasArticle: 149377
On 20 Ott, 09:46, "maxascent" <maxascent@n_o_s_p_a_m.n_o_s_p_a_m.yahoo.co.uk> wrote: > Please go and read the Spartan 6 DC data sheet and the Select IO guide and > I am sure that all your questions will be answered. You are asking > questions that you could find out quite easily by yourself. I am not saying > I dont want to give you the answer, but in the long term I think it would > be better that you did it. it's what i've done and from datasheet i think it's possible, but i asked in this newsgroup to became totally sure...in datasheet (pag 28 in SelectIO resources) i've found "LVDS_33 is used to drive TIA/EIA644 LVDS levels in a bank powered with 3.3V VCCO. Electrically the same as LVDS_25." So i think is possible, right?Article: 149378
>Hello all, > >I need to change a design that I have done years ago in Spartan XCS05 devices. > >Unfortunately I have failed to install software that is capable to do this. >I found an old carton containing ISE 4.1i, could install this but the FPGA Express >License that is included in it is expired (according to FLEX utility) in 2003. > Have you tried winding the system clock back to 2002 to fool FlexLM? May need to uninstall the old ISE first. --------------------------------------- Posted through http://www.FPGARelated.comArticle: 149379
On 10/20/2010 2:37 PM, fasf wrote: > On 20 Ott, 09:46, "maxascent" > <maxascent@n_o_s_p_a_m.n_o_s_p_a_m.yahoo.co.uk> wrote: >> Please go and read the Spartan 6 DC data sheet and the Select IO guide and >> I am sure that all your questions will be answered. You are asking >> questions that you could find out quite easily by yourself. I am not saying >> I dont want to give you the answer, but in the long term I think it would >> be better that you did it. > > it's what i've done and from datasheet i think it's possible, but i > asked in this newsgroup to became totally sure...in datasheet (pag 28 > in SelectIO resources) i've found "LVDS_33 is used to drive TIA/EIA644 > LVDS levels in a bank powered with 3.3V VCCO. Electrically the same as > LVDS_25." > So i think is possible, right? Although you quote here the datasheet which says you can transmit LVDS from a 3.3V bank, you originally asked whether you can receive LVDS signals in a 3.3V bank. What does the datasheet say about that? What about termination? Cheers, Syms.Article: 149380
On Oct 14, 10:56=A0am, Prevailing over Technology <steve.kn...@prevailing-technology.com> wrote: > Happy birthday, Bernie! =A0We miss you! > <snip> > > Bernie's influence at Xilinx was obvious and legendary. =A0His > organization chart put customers at the top, in the most important > position, and the board and the CEO at the bottom. =A0 Here is a link to a picture of that org chart : http://www.fastertechnology.com/fileadmin/images/IMG00066-20101019-1446.jpg Regards, John McCaskillArticle: 149381
On Oct 20, 4:39=A0am, Thomas Heller <thel...@python.net> wrote: > Hello all, > > I need to change a design that I have done years ago in Spartan XCS05 dev= ices. > > Unfortunately I have failed to install software that is capable to do thi= s. > I found an old carton containing ISE 4.1i, could install this but the FPG= A Express > License that is included in it is expired (according to FLEX utility) in = 2003. > > Downloaded Webpack 4.1 and 4.2, but they do not support the Spartan devic= e. > Downloaded "Xilinx Spartan 4k 4.2", but that does require third party sof= tware > for synthesis. > > Does anyone know if it is still possible to synthesize for a Spartan devi= ce? > > Thanks, > Thomas The Spartan-I was never supported by XST. If you can't get you old FPGA-Express license to work, the only option I know of is to buy a license from Synopsys. (OK, there are other options, like FPGA- Advantage, but none are well integrated into ISE.) Xilinx is not allowed to sell/renew your license. And I believe that ISE-4.2 is the last version that supported the Spartan-I. If you're really, really stuck, I should be able to re-build it (shameless plug). RKArticle: 149382
On Oct 19, 2:18=A0pm, "MM" <mb...@yahoo.com> wrote: > Well, it turned out ISE was picking up either system.ncf or system.ucf > created originally by the EDK wizard I believe. They were not explicitly > included in the project as far as I could tell. > > /Mikhail > If you read the fine print in the command-line documentation, it mentions files that are scanned if they exist and are not specifically excluded with a command-line option. No warning/error message if they don't exist, no log message if they do. Be wary of any file that has the same name as your top level module. RKArticle: 149383
On Oct 20, 7:39=A0am, Thomas Heller <thel...@python.net> wrote: > Hello all, > > I need to change a design that I have done years ago in Spartan XCS05 dev= ices. > > Unfortunately I have failed to install software that is capable to do thi= s. > I found an old carton containing ISE 4.1i, could install this but the FPG= A Express > License that is included in it is expired (according to FLEX utility) in = 2003. > > Downloaded Webpack 4.1 and 4.2, but they do not support the Spartan devic= e. > Downloaded "Xilinx Spartan 4k 4.2", but that does require third party sof= tware > for synthesis. > > Does anyone know if it is still possible to synthesise for a Spartan devi= ce? > > Thanks, > Thomas I just looked at my license file for Foundation Express 4.1i, and although it shows a date of 2002.12 in all the lines, I think it still works (I have used it within the past year). My understanding is that these don't expire, but the software updates end at the date in the license file. Do you still have the FPGA Express disk in your old 4.1i package? That version should still work with the license you have. Make sure that the node it is locked to still matches your computer. Mine is linked to the system hard drive serial number which is easy enough to change if you have moved to another computer. This information should be apparent in the license.dat file. I'm running Foundation 4.1i service pack 3. HTH, GaborArticle: 149384
On Oct 20, 2:10=A0pm, Gabor <ga...@alacron.com> wrote: > On Oct 20, 7:39=A0am, Thomas Heller <thel...@python.net> wrote: > > > > > Hello all, > > > I need to change a design that I have done years ago in Spartan XCS05 d= evices. > > > Unfortunately I have failed to install software that is capable to do t= his. > > I found an old carton containing ISE 4.1i, could install this but the F= PGA Express > > License that is included in it is expired (according to FLEX utility) i= n 2003. > > > Downloaded Webpack 4.1 and 4.2, but they do not support the Spartan dev= ice. > > Downloaded "Xilinx Spartan 4k 4.2", but that does require third party s= oftware > > for synthesis. > > > Does anyone know if it is still possible to synthesise for a Spartan de= vice? > > > Thanks, > > Thomas > > I just looked at my license file for Foundation Express 4.1i, and > although it > shows a date of 2002.12 in all the lines, I think it still works (I > have used > it within the past year). =A0My understanding is that these don't > expire, but > the software updates end at the date in the license file. =A0Do you > still have the > FPGA Express disk in your old 4.1i package? =A0That version should still > work with the license you have. =A0Make sure that the node it is locked > to > still matches your computer. =A0Mine is linked to the system hard drive > serial number which is easy enough to change if you have moved to > another computer. =A0This information should be apparent in the > license.dat > file. =A0I'm running Foundation 4.1i service pack 3. > > HTH, > Gabor I just re-checked and I can still compile with FPGA Express. The version is 3.6.1 which was an update at about the same time as service pack 3 for 4.1i Regards, GaborArticle: 149385
Hi, I am new in fpga boards, actually this is the first time I ever used an fpga. Anyway I have a set of data which I want to store them in the SRAM of the fpga. I understand that I have to create a DMA controller which will be master of the AMBA bus but the only block that I can add any hardware is a predefined block called gp_custom which is slave to the AMBA bus. The fpga board I am using is from altera and the DMA block has to be part of the LEON 3 system. Does anyone has any tips on how to add a block into the LEON system which will be master on the AMBA bus ??? --------------------------------------- Posted through http://www.FPGARelated.comArticle: 149386
"d_s_klein" <d_s_klein@yahoo.com> wrote > > If you read the fine print in the command-line documentation, it > mentions files that are scanned if they exist and are not specifically > excluded with a command-line option. I've read the fine print and I couldn't find why it is doing what it is doing. I think it is just yet another bug... > No warning/error message if they don't exist, no log message if they do. For some bizzare reason I am not surprized.... /MikhailArticle: 149387
I saw a console message today generated by either ISE or PlanAhead offering me to run some command to save all invalid constraints to a file. I can't find this information in any of the reports or user guides... Could someone point me in the right direction please? And I am not asking why they couldn't just generate the damn file instead of asking me to do so! /MikhailArticle: 149388
On Oct 20, 2:04=A0pm, "MM" <mb...@yahoo.com> wrote: > "d_s_klein" <d_s_kl...@yahoo.com> wrote > > > > > If you read the fine print in the command-line documentation, it > > mentions files that are scanned if they exist and are not specifically > > excluded with a command-line option. > > I've read the fine print and I couldn't find why it is doing what it is > doing. I think it is just yet another bug... > > > No warning/error message if they don't exist, no log message if they do= . > > For some bizzare reason I am not surprized.... > > /Mikhail I'm not sure where it is documentated, but the ISE software tools have always picked up the NCF, UCF and PCF file extensions that match the base name of the file that is being processed (NGC, EDIF, or NGD). Ed McGettigan -- Xilinx Inc.Article: 149389
Am 20.10.2010 16:25, schrieb RCIngham: >>Hello all, >> >>I need to change a design that I have done years ago in Spartan XCS05 > devices. >> >>Unfortunately I have failed to install software that is capable to do > this. >>I found an old carton containing ISE 4.1i, could install this but the FPGA > Express >>License that is included in it is expired (according to FLEX utility) in > 2003. >> > > Have you tried winding the system clock back to 2002 to fool FlexLM? Yep, this works ;-). Now, I have to get the bitfile into the device. For whatever reasons, the parallel cable III that I have is not recognized by the software or does simply not work. I tried to use IMPACT from a newer version that I have installed (ISE 9.1i) together with the Platform Cable USB but that didn't work either. At least IMPACT refuses to read the .bit file for the device. Gabor wrote: > I just looked at my license file for Foundation Express 4.1i, and > although it > shows a date of 2002.12 in all the lines, I think it still works (I > have used > it within the past year). My understanding is that these don't > expire, but > the software updates end at the date in the license file. Do you > still have the > FPGA Express disk in your old 4.1i package? That version should still > work with the license you have. Make sure that the node it is locked > to > still matches your computer. Mine is linked to the system hard drive > serial number which is easy enough to change if you have moved to > another computer. This information should be apparent in the > license.dat > file. I'm running Foundation 4.1i service pack 3. Thanks for this information. I dont have the old license anymore, only the temporary license that is installed by the installer.Article: 149390
On 20 Ott, 16:26, Symon <symon_bre...@hotmail.com> wrote: > On 10/20/2010 2:37 PM, fasf wrote: > > > On 20 Ott, 09:46, "maxascent" > > <maxascent@n_o_s_p_a_m.n_o_s_p_a_m.yahoo.co.uk> =A0wrote: > >> Please go and read the Spartan 6 DC data sheet and the Select IO guide= and > >> I am sure that all your questions will be answered. You are asking > >> questions that you could find out quite easily by yourself. I am not s= aying > >> I dont want to give you the answer, but in the long term I think it wo= uld > >> be better that you did it. > > > it's what i've done and from datasheet i think it's possible, but i > > asked in this newsgroup to became totally sure...in datasheet =A0(pag 2= 8 > > in SelectIO resources) i've found "LVDS_33 is used to drive TIA/EIA644 > > LVDS levels in a bank powered with 3.3V VCCO. Electrically the same as > > LVDS_25." > > So i think is possible, right? > > Although you quote here the datasheet which says you can transmit LVDS > from a 3.3V bank, you originally asked whether you can receive LVDS > signals in a 3.3V bank. I'm interested in LVDS input >What does the datasheet say about that? What > about termination? "LVDS inputs require a parallel termination resistor, either through the use of a discrete resistor on the PCB, or the use of the DIFF_TERM attribute to enable internal termination. LVDS inputs can be placed on any I/O bank, while LVDS outputs are only available on I/O banks 0 and 2." So, i can use DIFF_TERM to set internal termination and, due to fact that LVDS_3.3 is elettrically the same as LVDS_2.5, i can use 3.3V bank to receive LVDS_2.5 Right?Article: 149391
On 18 Oct, 16:04, fasf <silusilus...@gmail.com> wrote: > Hi, > i'm new with FPGA,so excuse me for my question... > Any FPGA is composed by banks, each with its Vdd: IO pins of that bank > can be used with each logic with high state and low state between 0- > vdd? > For example, if Vdd is 3V, i can use IO pins for LVDS signals (1.8V > +-200mV)?And for TTL signal 0-5V? > Thanks You are asking a question that the tools will answer in ten minutes. Create a design with one input driving one output. Set the input IO standard to LVDS_whatever, set the output IO standard to CMOS_33. Put them both in the same IO bank and compile. Unless you are using a ten year old FPGA you can't run 5v IO. ColinArticle: 149392
On 21 Ott, 11:00, colin <colin_toog...@yahoo.com> wrote: > On 18 Oct, 16:04, fasf <silusilus...@gmail.com> wrote: > > > Hi, > > i'm new with FPGA,so excuse me for my question... > > Any FPGA is composed by banks, each with its Vdd: IO pins of that bank > > can be used with each logic with high state and low state between 0- > > vdd? > > For example, if Vdd is 3V, i can use IO pins for LVDS signals (1.8V > > +-200mV)?And for TTL signal 0-5V? > > Thanks > > You are asking a question that the tools will answer in ten minutes. > Create a design with one input driving one output. Set the input IO > standard to LVDS_whatever, set the output IO standard to CMOS_33. Put > them both in the same IO bank and compile. Ok, but i've never used IDE before, so i'm studying from user guideArticle: 149393
On Oct 21, 7:17=A0am, fasf <silusilus...@gmail.com> wrote: > On 21 Ott, 11:00, colin <colin_toog...@yahoo.com> wrote: > > > On 18 Oct, 16:04, fasf <silusilus...@gmail.com> wrote: > > > > Hi, > > > i'm new with FPGA,so excuse me for my question... > > > Any FPGA is composed by banks, each with its Vdd: IO pins of that ban= k > > > can be used with each logic with high state and low state between 0- > > > vdd? > > > For example, if Vdd is 3V, i can use IO pins for LVDS signals (1.8V > > > +-200mV)?And for TTL signal 0-5V? > > > Thanks > > > You are asking a question that the tools will answer in ten minutes. > > Create a design with one input driving one output. Set the input IO > > standard to LVDS_whatever, set the output IO standard to CMOS_33. Put > > them both in the same IO bank and compile. > > Ok, but i've never used IDE before, so i'm studying from user guide While the user guides have a lot of useful information, you'll never get everything you need to know without running the tools. Get used to it. This is the way FPGA Engineering works. There are even cases where you find an issue that is not described in the documentation, and Xilinx responds with "run the tools". Want to know which I/O bank is in which column in a Virtex 5? Can you really use LVDS_25 in a Virtex 5 on any bank regardless of Vcco? These are not well explained in the documentation. For example for Virtex 5, LVDS_25 is powered by the VccAux supply, so you don't need a particular Vcco, BUT if you want to use DIFF_TERM, Vcco MUST be 2.5V. I don't think that the Spartan 6 has the same issue, but there are other things you will certainly miss if you just lay out a board and expect everything to work without running it through the tools. I had a very expensive flex- laminate that could only use 55 out of 64 bits of a DDR SO-DIMM because of a poorly documented IOB clock routing issue in Virtex 2. So get out the tools, run through a tutorial or two, and then use the manuals as a reference guide. Regards, GaborArticle: 149394
On Oct 20, 2:29=A0pm, "MM" <mb...@yahoo.com> wrote: > I saw a console message today generated by either ISE or PlanAhead offeri= ng > me to run some command to save all invalid constraints to a file. I can't > find this information in any of the reports or user guides... Could someo= ne > point me in the right direction please? And I am not asking why they > couldn't just generate the damn file instead of asking me to do so! > > /Mikhail What you are looking for may be in the process properties for 'Generate Post-Place & Route Static Timing' - the step just before PlanAhead. (Why is PlanAhead the *last* step in the process? Make me wonder.) RKArticle: 149395
"d_s_klein" <d_s_klein@yahoo.com> wrote in message news:8bc41a80-0d1f-4416-9917-a1d624cb69cf@h37g2000pro.googlegroups.com... > > What you are looking for may be in the process properties for > 'Generate Post-Place & Route Static Timing' - the step just before > PlanAhead. (Why is PlanAhead the *last* step in the process? Make me > wonder.) No, I don't see an explicit option for that there... If I am looking in the right place... /MikhailArticle: 149396
Analyze Timing / Floorplan Design with PlanAhead is using a different number for total system jitter (TSJ) compared to Post-Place & Route Static Timing Analysis yielding very different results... The PlanAhead seems to be more conservative. Or does it know more about where the clock comes from? Also, for some reason even being more conservative in my case it somehow reports less number of errors... Perhaps it is not always more conservative... Any comments? Thanks, /MikhailArticle: 149397
Le 18/10/2010 12:39, sandy a écrit : > Hello, > > For one of my project, I want to send data from zigbee to FPGA and > vice versa. Can this possible? No. Unless I misunderstood the question. NicoArticle: 149398
Actually, the difference seems to be not between PlanAhead and Post-Place & Route Static Timing Analysis, but between different runs of the latter. In one case it picks the TSJ from the top UCF file, in another case it inserts some 70 ps instead... The question still remains why PlanAhead reports a much smaller number of errors than the Post-Place & Route Static Timing Analysis even though the top errors are exactly the same... Is there are a hidden limit on the number of errors reported in PlanAhead, which I can't find? When I tried running Report Timing from PlanAhead it quietly crashed... :( /MikhailArticle: 149399
maxascent wrote: > > I am trying to run a Hyperlynx simulation for LVDS in a Spartan 6 FPGA. > <snip> > when I select this model the simulation complains that it cant perform > it because it cant model a series resistor at the receiver input. > What version of Hyperlynx are you using? When I checked a few years back, 7.5 & earlier couldn't handle the series elements: http://groups.google.com/group/comp.arch.fpga/msg/c6e28cb7cc0ce3d0 Brian
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