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On Oct 27, 5:48=A0pm, "Steve Ravet" <steve.ra...@arm.com> wrote: > Walter, thanks for the advice. =A0I have already made the change in the R= TL but need to press on with this image, and find as many > bugs as possible, before spending a week respinning the design. > > The word back from xilinx support is to not use the TIEOFF, but to instea= d connect the OBUF.O input to the net GLOBAL_LOGIC1. =A0Did > that and it works great. =A0I'd still like to know what the problem was r= outing the TIEOFF though... > > --steve > > "Walter" <wsf...@adinet.com.uy> wrote in messagenews:ia9m0j$a9e$1@adenine= .netfront.net... > > Steve : > > > FPGA Editor is a great tool to debug and to find synthesis and or imple= mentations tools bugs but never use it as design tool. > > > If you need a new output go back to your HDL add a new output and then = go to your UCF to setup the properties to the added output. > > > Never break the implementation tool chain other than to do some simple = test. > > > Walter > > > El 2010-10-27 13:53, Steve Ravet escribi=F3: > >> That's a good idea, to add a probe to the TIEOFF and see how fpga_edit= or routes it. =A0I just got off the phone with xilinx > >> support, > >> they were able to duplicate the problem. =A0He tried manually routing = it as well and was unable to. > > >> For now the pullup is exactly what I've done, although I'd like to und= erstand why those pins aren't routable. > > >> thanks, > >> --steve > > >> "MM"<mb...@yahoo.com> =A0wrote in messagenews:8iqujvF3leU1@mid.individ= ual.net... > >>> A simpler way might be adding a probe pin if you can find an existing= net to attach it to. Yet another possibility is simply > >>> enabling a pullup. > > >>> /Mikhail > > >>> "Steve Ravet"<steve.ra...@arm.com> =A0wrote in messagenews:ia9e1k$5gk= $1@cam-news1.cambridge.arm.com... > >>>> I thought this would be easy but I'm having a problem routing one of= the wires. =A0I need to create a new output from my fpga, > >>>> tied > >>>> high (LX760). What I've done so far: > > >>>> Added a new OBUF H36(and set the OSTANDARD, SLEW, and DRIVE, thanks = Ed). Edited the OBUF OUTMUX and OINMUX to create a path > >>>> from > >>>> O to the pad. > > >>>> Added a new OLOGIC X0Y318 and created a path from D1 to OQ. > > >>>> Selected OBUF.O and OLOGIC.OQ and created a routed net between them = with the add command. > > >>>> Added a new TIEOFF x0Y318. =A0Selected pins TIEOFF.HARD1, OLOGIC.D1,= tried to create a routed net between them with the add > >>>> command > >>>> but it failed. =A0The specific commands were: > > >>>> select pin VTREF_TIEOFF.HARD1 > >>>> select pin VTREF_ologic.D1 > >>>> add > > >>>> The failure message is: > > >>>> ERROR:FPGAEditor:313 - Failed to route net "$NET_1". > >>>> ERROR:FPGAEditor:316 - Failed to route pin "VTREF_ologic.D1" on net = "$NET_1". > > >>>> I've done this kind of thing before, I'm not sure why it isn't worki= ng. Any suggestions? > > >>>> thanks, > >>>> --steve > > > --- news://freenews.netfront.net/ - complaints: n...@netfront.net --- You might get more clues if you turn on the switch boxes in the FPGA editor view settings. It's possible that the TIEOFF is only accessible for routing to the internal fabric and not the IOB's.Article: 149476
On Oct 27, 10:00=A0am, "salimbaba" <a1234573@n_o_s_p_a_m.n_o_s_p_a_m.owlpic.com> wrote: > Hi, > i am using spartan 3 xc3s4000 in my design and 2 national phys are > integrated with it. The problem is that when i transmit from phy 1 to phy= 2 > ,i receive the packet and i can view it on wireshark. When i transmit it > from phy2 to phy1 , wireshark display "receive ok" in statistics menu but > it doesn't display any packet. and it doesn't report fcs error either. > > btw i am using xilinx 12.1 for synthesis. > > So,i switched to chipscope pro to debug my design,and i can see the > transmitting nibbles , which are correct. But i don't know why isn't the = pc > showing any packet. > > Also, both are phys are just using 2 instances of same module. So, if the > logic works at one end, technically it should work at the other end as > well. > > can anyone give me any pointers as to what should i do now? how to debug > it? > Because i have been stuck for 2 days now and my vision has narrowed down = a > lot and i am out of ideas now. Kindly! > > Regards > SalimBaba =A0 =A0 =A0 =A0 =A0 > > --------------------------------------- =A0 =A0 =A0 =A0 > Posted throughhttp://www.FPGARelated.com Have you checked your timing constraints? You could be lucky that one PHY interconnect makes timing and the other doesn't. John ProvidenzaArticle: 149477
Hi, I am unable to find sufficient documentation on Altera's site for bitstream encryption. I have a design for which I need to generate an encrypted bistream onto the device (doesn't matter which family, documentation on any would be fine). Can someone help me and point to the resources? Thanks, Rohit --------------------------------------- Posted through http://www.FPGARelated.comArticle: 149478
> >Have you checked your timing constraints? You could be lucky that one >PHY interconnect >makes timing and the other doesn't. > >John Providenza > Exactly john, i figured out today that it was a timing constraints issue. One phy was meeting them and the other one wasn't. But xilinx wasn't reporting it so i guess i was operating on the boundary. But john its a funny world we live in, we placed some constraints and it started to work. Both ports working fine but then we added another thing in the design, a counter actually, and the design again stopped working on one end.Now, the port was switched. So, we took out some signals in chipscope and the problem again switched ports :p funny, right ? :p i don't know what's happening, i mean if it's a timing issue and xilinx isn't saying that timing failed, then i guess it should work each time we run. what do u have to say on this ? --------------------------------------- Posted through http://www.FPGARelated.comArticle: 149479
On Oct 28, 12:53=A0pm, "salimbaba" <a1234573@n_o_s_p_a_m.n_o_s_p_a_m.owlpic.com> wrote: > >Have you checked your timing constraints? =A0You could be lucky that one > >PHY interconnect > >makes timing and the other doesn't. > > >John Providenza > > Exactly john, i figured out today that it was a timing constraints issue. > One phy was meeting them and the other one wasn't. But xilinx wasn't > reporting it so i guess i was operating on the boundary. But john its a > funny world we live in, we placed some constraints and it started to work= . > Both ports working fine but then we added another thing in the design, a > counter actually, and the design again stopped working on one end.Now, th= e > port was switched. So, we took out some signals in chipscope and the > problem again switched ports :p funny, right ? :p =A0i don't know what's > happening, i mean if it's a timing issue and xilinx isn't saying that > timing failed, then i guess it should work each time we run. what do u ha= ve > to say on this ? =A0 =A0 =A0 =A0 =A0 > > --------------------------------------- =A0 =A0 =A0 =A0 > Posted throughhttp://www.FPGARelated.com A suggestion - look at the timing report and make sure you have the timing analyzer report all unconstrained paths. I always try to eliminate them so I know that I've got a fully constrained design. John ProvidenzaArticle: 149480
Hi All, As was discussed in an FMC-related thread a few weeks back, Epiq Solutions has now publicly announced the Bitshark FMC-1RX software- defined radio receiver that complies with the FPGA Mezzanine Card (FMC) digital interface standard defined by VITA 57. Quick list of highlights of this card: -Direct conversion (zero-IF) architecture -Frequency tuning range: 300 MHz - 4 GHz -RF channel bandwidth: up to 50 MHz -A/D converters: dual 14-bit/105 Msample/sec (one for 'I', one for 'Q') -Low-Pin Count (LPC) variant of the FMC standard, using LVDS lanes to transport -On-board GPS receiver for time/position tagging of receive data More details of this card can be found at the following link: http://www.epiq-solutions.com/product_detail.php?line=Bitshark&product=Bitshark_FMC Comments/question welcome. Thanks for the bandwidth. Regards, John Orlando www.epiq-solutions.comArticle: 149481
W dniu 10/28/2010 20:15, sinharo pisze: > Hi, > > I am unable to find sufficient documentation on Altera's site for bitstream > encryption. I have a design for which I need to generate an encrypted > bistream onto the device (doesn't matter which family, documentation on any > would be fine). Can someone help me and point to the resources? > > Thanks, > Rohit Hi, I can help you. But without question I can't give you answer. I used EP3CLS70 with internal AES decryption Best regards AdamArticle: 149482
>Hi, > >I am unable to find sufficient documentation on Altera's site for bitstream >encryption. I have a design for which I need to generate an encrypted >bistream onto the device (doesn't matter which family, documentation on any >would be fine). Can someone help me and point to the resources? > >Thanks, >Rohit http://www.xilinx.com/itp/xilinx10/isehelp/pp_db_encryption_options.htm --------------------------------------- Posted through http://www.FPGARelated.comArticle: 149483
I am running the Xilinx ISE Release Version: 10.1.03. I am making a validation for an ARM926EJS IP core. At the step of check syntax, a series of such errors as "HDLCompilers:108 - 'a926InstrCache.v' line 3051 Part-select of scalar wire 'sNSeqVAIndex' is illegal" occurs, but when I changed to running the project including the same source files in Altera Quartus, there aren't any syntax errors. It bothering me very well. Could anyone help me? The part of program is as follows: module ...; .. wire [ 4: 2] PWFBWord; wire [ 3: 0] PWFBByteSel; .. a926CacheFB uFB( .CClk (CClk), .CnReset (CnReset), .PWFBFull (PWFBFull), // .PWFBWord (PWFBWord), .PWFBWord (PWFBWord[4:2]), // .PWFBByteSel (PWFBByteSel), .PWFBByteSel (PWFBByteSel[3:0]), .PWFBWriteback (PWFBWriteback), .PWFBD (PWFBD), // .PWFBD (PWFBD[31:0]), .BIURD (BIURD), // .BIURD (BIURD[31:0]), .CACHEBIUReady (CACHEBIUReady), .sMemReq (sMemReq), // .sVA (sVA), .sVA (sVA[4:2]), .sNSeqVA (sNSeqVA[24:5]), .RawMVA (RawMVA[31:25]), .LfVA (LfVA[24:5]), .LfMVA (LfMVA[31:25]), .LfWay (LfWayFB[3:0]), .FBHit (FBHit), .FBWordHit (FBWordHit), .FBFull (FBFull), .FBFilling (FBFilling), .FBFill (FBFill), .FBDirtyLower (FBDirtyLower), .FBDirtyUpper (FBDirtyUpper), .FBDrain (FBDrain), .DATAFBUpperSel (DATAFBUpperSel), .LFStart (LFStart), .CP15InvalAll (CP15InvalAll), .CP15InvalFB (CP15InvalFB), .CNoLinefill (CNoLinefill), .FBWD0 (FBWD0[31:0]), .FBWD1 (FBWD1[31:0]), .FBWD2 (FBWD2[31:0]), .FBWD3 (FBWD3[31:0]), .FBRD (FBRD[31:0]) ); The errors are very strange. Once the part-select index among the brackets of each variable is deleted in the instantiation of a926CacheFB module, the corresponding error will disappear. I am not sure whether the method is useful to eliminate the errors while not to change its functions because of the complexity of the project. I am sorry if I made a unclear explanation of my question. Please excuse me for my poor English.Article: 149484
On Oct 29, 7:17=A0am, zhangbert <u...@compgroups.net/> wrote: > I am running the Xilinx ISE Release Version: 10.1.03. I am making a valid= ation for an ARM926EJS IP core. At the step of check syntax, a series of su= ch errors as "HDLCompilers:108 - 'a926InstrCache.v' line 3051 Part-select o= f scalar wire 'sNSeqVAIndex' is illegal" occurs, but when I changed to runn= ing the project including the same source files in Altera Quartus, there ar= en't any syntax errors. It bothering me very well. Could anyone help me? Th= e part of program is as follows: > module ...; > ... > wire =A0 [ 4: 2] PWFBWord; > wire =A0 [ 3: 0] PWFBByteSel; > ... > a926CacheFB uFB( > =A0 .CClk =A0 =A0 =A0 =A0 =A0 (CClk), > =A0 .CnReset =A0 =A0 =A0 =A0(CnReset), > > =A0 .PWFBFull =A0 =A0 =A0 (PWFBFull), > // =A0.PWFBWord =A0 =A0 =A0 (PWFBWord), > =A0 .PWFBWord =A0 =A0 =A0 (PWFBWord[4:2]), > // =A0.PWFBByteSel =A0 =A0(PWFBByteSel), > =A0 .PWFBByteSel =A0 =A0(PWFBByteSel[3:0]), > =A0 .PWFBWriteback =A0(PWFBWriteback), > =A0 .PWFBD =A0 =A0 =A0 =A0 =A0(PWFBD), > // =A0.PWFBD =A0 =A0 =A0 =A0 =A0(PWFBD[31:0]), > > =A0 .BIURD =A0 =A0 =A0 =A0 =A0(BIURD), > // =A0.BIURD =A0 =A0 =A0 =A0 =A0(BIURD[31:0]), > =A0 .CACHEBIUReady =A0(CACHEBIUReady), > > =A0 .sMemReq =A0 =A0 =A0 =A0(sMemReq), > // =A0.sVA =A0 =A0 =A0 =A0 =A0 =A0(sVA), > =A0 .sVA =A0 =A0 =A0 =A0 =A0 =A0(sVA[4:2]), > =A0 .sNSeqVA =A0 =A0 =A0 =A0(sNSeqVA[24:5]), > =A0 .RawMVA =A0 =A0 =A0 =A0 (RawMVA[31:25]), > =A0 .LfVA =A0 =A0 =A0 =A0 =A0 (LfVA[24:5]), > =A0 .LfMVA =A0 =A0 =A0 =A0 =A0(LfMVA[31:25]), > =A0 .LfWay =A0 =A0 =A0 =A0 =A0(LfWayFB[3:0]), > > =A0 .FBHit =A0 =A0 =A0 =A0 =A0(FBHit), > =A0 .FBWordHit =A0 =A0 =A0(FBWordHit), > =A0 .FBFull =A0 =A0 =A0 =A0 (FBFull), > =A0 .FBFilling =A0 =A0 =A0(FBFilling), > =A0 .FBFill =A0 =A0 =A0 =A0 (FBFill), > =A0 .FBDirtyLower =A0 (FBDirtyLower), > =A0 .FBDirtyUpper =A0 (FBDirtyUpper), > =A0 .FBDrain =A0 =A0 =A0 =A0(FBDrain), > =A0 .DATAFBUpperSel (DATAFBUpperSel), > =A0 .LFStart =A0 =A0 =A0 =A0(LFStart), > > =A0 .CP15InvalAll =A0 (CP15InvalAll), > =A0 .CP15InvalFB =A0 =A0(CP15InvalFB), > =A0 .CNoLinefill =A0 =A0(CNoLinefill), > > =A0 .FBWD0 =A0 =A0 =A0 =A0 =A0(FBWD0[31:0]), > =A0 .FBWD1 =A0 =A0 =A0 =A0 =A0(FBWD1[31:0]), > =A0 .FBWD2 =A0 =A0 =A0 =A0 =A0(FBWD2[31:0]), > =A0 .FBWD3 =A0 =A0 =A0 =A0 =A0(FBWD3[31:0]), > =A0 .FBRD =A0 =A0 =A0 =A0 =A0 (FBRD[31:0]) > ); > > =A0 =A0The errors are very strange. Once the part-select index among the = brackets of each variable is deleted in the instantiation of a926CacheFB mo= dule, the corresponding error will disappear. I am not sure whether the met= hod is useful to eliminate the errors while not to change its functions bec= ause of the complexity of the project. I am sorry if I made a unclear expla= nation of my question. Please excuse me for my poor English. You didn't include the full file, so it isn't possible to determine which line is 3051. The code portion that you posted doesn't have anything called "sNSeqVAIndex" and the closest item that I could find was .sNSeqVA (sNSeqVA[24:5]), Was the "sNSeqVA" port on the "a926CacheFB" module defined as [19:0]? Does the wire or reg "sNSeqVA" that drives this port have a size that is at least [24:0]? It could be a XST bug that has since been fixed. You are using 10.1.3 and the latest software is 12.3. BTW, Your english is perfect. Ed McGettigan -- Xilinx Inc.Article: 149485
I have a Virtex 5 design that uses a GTP. I have a simple simulation that justs transmits some data and looks at the received data. The simulation works fine and I see the correct received data. The trouble is when I run the design in hardware and look at the data using chipscope it doesnt match. I am using 8b10b coding and the comma character is detected correctly but the following data is not correct. The data doesnt seem to be rubbish as if I send two bytes that are the same (4A 4A) I get two bytes that are the same (38 38) just the wrong value. Has anybody seen anything like this? Thanks Jon --------------------------------------- Posted through http://www.FPGARelated.comArticle: 149486
On Oct 29, 11:08=A0am, "maxascent" <maxascent@n_o_s_p_a_m.n_o_s_p_a_m.yahoo.co.uk> wrote: > I have a Virtex 5 design that uses a GTP. I have a simple simulation that > justs transmits some data and looks at the received data. The simulation > works fine and I see the correct received data. The trouble is when I run > the design in hardware and look at the data using chipscope it doesnt > match. I am using 8b10b coding and the comma character is detected > correctly but the following data is not correct. The data doesnt seem to = be > rubbish as if I send two bytes that are the same (4A 4A) I get two bytes > that are the same (38 38) just the wrong value. Has anybody seen anything > like this? > > Thanks > > Jon =A0 =A0 =A0 =A0 > > --------------------------------------- =A0 =A0 =A0 =A0 > Posted throughhttp://www.FPGARelated.com How did you attach the ChipScope ILA? Is it instantiated in your project or did you use the inserter? I have in the past tried to debug bit-ordering issues that ended up being ChipScope re-ordering the bits for me. See if you can map the values you get to the expected values by re-arranging the bits. For example hex 38 and hex 4A each have exactly three 1 bits and five 0 bits. Regards, GaborArticle: 149487
I have the ILA instantiated in the design. As I said the data does seem to have some sort of pattern so I guess it could be a chipscope issue. Its a bit strange that the comma value is correct but the data isnt. I will have a go using the inserter and see if that makes any difference. Cheers Jon --------------------------------------- Posted through http://www.FPGARelated.comArticle: 149488
Normally I would contact Xilinx directly, but my FAE's email just bounced. I have a design that works in 11.5, and does not work in 12.3. It's not meeting timing in 11.5 due to routing delays (the top 5 timing offenders are all > 80% route), so I tried it in 12.3. First pass MAP failed. It told me to add constraints to get it to build. When I add the constraints, PAR reports un-routable nets. This from the usage of the GTX_DUAL module in a Virtex-5 Any ideas? What files would be interesting?Article: 149489
First, make sure you clean the project well. What was the original MAP error? Was it related to enabling idle GTX tiles for passing reference clock? /Mikhail "ghelbig" <ghelbig@lycos.com> wrote in message news:2dfc4e04-88d0-41df-a9b5-85c9350a302e@s9g2000vby.googlegroups.com... > Normally I would contact Xilinx directly, but my FAE's email just > bounced. > > > > I have a design that works in 11.5, and does not work in 12.3. > > It's not meeting timing in 11.5 due to routing delays (the top 5 > timing offenders are all > 80% route), so I tried it in 12.3. > > First pass MAP failed. It told me to add constraints to get it to > build. When I add the constraints, PAR reports un-routable nets. > > This from the usage of the GTX_DUAL module in a Virtex-5 > > Any ideas? What files would be interesting?Article: 149490
On Oct 29, 11:05=A0am, "MM" <mb...@yahoo.com> wrote: > First, make sure you clean the project well. What was the original MAP > error? Was it related to enabling idle GTX tiles for passing reference > clock? > > /Mikhail > I keep all the ISE files in a separate directory. For this migration, I copied the xise file from .../ise to .../ise.123 - just the xise and the ucf file. Then I let ISE have its way with the directory - I'm pretty sure this starts with a clean project. The map error message is: ERROR:Place:1040 - Unroutable Placement! An IPAD / GT component pair have been found that are not placed at a routable IPAD / GT site pair. The IPAD component <RX3_P> is placed at site <IPAD_X1Y25>. The corresponding GT component <MGT_RX3_RF/GTX_DUAL_DNA> is placed at site <GTX_DUAL_X0Y0>. The IPAD can route to the GT <RXP0> pin only if the load component is placed at an offset of (-2, -2) with respect to the driver component. This placement is UNROUTABLE in PAR and therefore, this error condition should be fixed in your design. You may use the CLOCK_DEDICATED_ROUTE constraint in the .ucf file to demote this message to a WARNING in order to generate an NCD file. This NCD file can then be used in FPGA Editor to debug the problem. A list of all the COMP.PINS used in this clock placement rule is listed below. These examples can be used directly in the .ucf file to demote this ERROR to a WARNING. The only placement constraint I have created is the pin number. Gary.Article: 149491
johnp <jprovidenza@yahoo.com> wrote: >On Oct 28, 12:53=A0pm, "salimbaba" ><a1234573@n_o_s_p_a_m.n_o_s_p_a_m.owlpic.com> wrote: >> >Have you checked your timing constraints? =A0You could be lucky that one >> >PHY interconnect >> >makes timing and the other doesn't. >> >> >John Providenza >> >> Exactly john, i figured out today that it was a timing constraints issue. >> One phy was meeting them and the other one wasn't. But xilinx wasn't >> reporting it so i guess i was operating on the boundary. But john its a >> funny world we live in, we placed some constraints and it started to work= >. >> Both ports working fine but then we added another thing in the design, a >> counter actually, and the design again stopped working on one end.Now, th= >e >> port was switched. So, we took out some signals in chipscope and the >> problem again switched ports :p funny, right ? :p =A0i don't know what's >> happening, i mean if it's a timing issue and xilinx isn't saying that >> timing failed, then i guess it should work each time we run. what do u ha= >ve >> to say on this ? =A0 =A0 =A0 =A0 =A0 >> >> --------------------------------------- =A0 =A0 =A0 =A0 >> Posted throughhttp://www.FPGARelated.com > >A suggestion - look at the timing report and make sure you have the >timing analyzer >report all unconstrained paths. I always try to eliminate them so I >know that I've >got a fully constrained design. Don't try to eliminate them. Make sure to eliminate them! It is also very important to constrain the IOB to flipflop and flipflop to IOB paths. Those are easely forgotten but may cause the OP's problems. -- Failure does not prove something is impossible, failure simply indicates you are not using the right tools... nico@nctdevpuntnl (punt=.) --------------------------------------------------------------Article: 149492
On Oct 29, 12:25=A0pm, ghelbig <ghel...@lycos.com> wrote: > On Oct 29, 11:05=A0am, "MM" <mb...@yahoo.com> wrote: > > > First, make sure you clean the project well. What was the original MAP > > error? Was it related to enabling idle GTX tiles for passing reference > > clock? > > > /Mikhail > > I keep all the ISE files in a separate directory. =A0For this migration, > I copied the xise file from .../ise to .../ise.123 - just the xise and > the ucf file. =A0Then I let ISE have its way with the directory - I'm > pretty sure this starts with a clean project. > > The map error message is: > > ERROR:Place:1040 - Unroutable Placement! An IPAD / GT component pair > have been found that are not placed at a routable > =A0 =A0IPAD / GT site pair. The IPAD component <RX3_P> is placed at site > <IPAD_X1Y25>. The corresponding GT component > =A0 =A0<MGT_RX3_RF/GTX_DUAL_DNA> is placed at site <GTX_DUAL_X0Y0>. The > IPAD can route to the GT <RXP0> pin only if the load > =A0 =A0component is placed at an offset of (-2, -2) with respect to the > driver component. This placement is UNROUTABLE in > =A0 =A0PAR and therefore, this error condition should be fixed in your > design. You may use the CLOCK_DEDICATED_ROUTE > =A0 =A0constraint in the .ucf file to demote this message to a WARNING in > order to generate an NCD file. This NCD file can > =A0 =A0then be used in FPGA Editor to debug the problem. A list of all th= e > COMP.PINS used in this clock placement rule is > =A0 =A0listed below. These examples can be used directly in the .ucf file > to demote this ERROR to a WARNING. > > The only placement constraint I have created is the pin number. > > Gary. If you constraining both the GTX instance and the TX/RX ports change to just constraining the GTX instance and the software will place the TX/RX ports in the one and only place that it can. Ed McGettigan -- Xilinx Inc.Article: 149493
On Oct 20, 1:10=A0pm, Gabor <ga...@alacron.com> wrote: > On Oct 20, 7:39=A0am, Thomas Heller <thel...@python.net> wrote: > > > > > Hello all, > > > I need to change a design that I have done years ago in Spartan XCS05 d= evices. > > > Unfortunately I have failed to install software that is capable to do t= his. > > I found an old carton containing ISE 4.1i, could install this but the F= PGA Express > > License that is included in it is expired (according to FLEX utility) i= n 2003. > > > Downloaded Webpack 4.1 and 4.2, but they do not support the Spartan dev= ice. > > Downloaded "Xilinx Spartan 4k 4.2", but that does require third party s= oftware > > for synthesis. > > > Does anyone know if it is still possible to synthesise for a Spartan de= vice? > > > Thanks, > > Thomas > > I just looked at my license file for Foundation Express 4.1i, and > although it > shows a date of 2002.12 in all the lines, I think it still works (I > have used > it within the past year). =A0My understanding is that these don't > expire, but > the software updates end at the date in the license file. =A0Do you > still have the > FPGA Express disk in your old 4.1i package? =A0That version should still > work with the license you have. =A0Make sure that the node it is locked > to > still matches your computer. =A0Mine is linked to the system hard drive > serial number which is easy enough to change if you have moved to > another computer. =A0This information should be apparent in the > license.dat > file. =A0I'm running Foundation 4.1i service pack 3. > > HTH, > Gabor Most of these old stuffs locked to hard drive serial number... that's the reason I still have a Pentium II under my deskArticle: 149494
On Oct 11, 3:51=A0pm, Gabor <ga...@alacron.com> wrote: > On Oct 11, 3:16=A0pm, "salimbaba" > > > > <a1234573@n_o_s_p_a_m.n_o_s_p_a_m.owlpic.com> wrote: > > Hi, > > I have a weird problem with my design. I am using xilinx 12.1 for its > > synthesis and implementation. > > The problem is that when i generate my bitstream with a chipscope core > > inserted in the design and program my FPGA, programming fails saying th= at > > "DONE did not go high" whereas when i take out the chipscope core or so= me > > signals from the core, programming succeeds but after that my JTAG stop= s > > working. If i try ti initialize JTAG chain in iMPACT it asks me whether= i > > have a BSDL or BIT file for this device or if i try to run chipscope,it > > also gives a warning and doesn't start. I checked the JTAG voltages and > > they were fine. > > > Rarely does my design work, so, i am kind of stuck here as i cannot deb= ug > > my system altogether. Is there something wrong with the Bit file or my = usb > > drivers? I tried reinstalling the drivers but didn't work. Then i > > reinstalled xilinx 12.1,still same problem. > > > Does it happen because of the size of the FPGA and the complexity of th= e > > logic we are inserting in it ? I mean that if the FPGA is not big enoug= h to > > hold the logic and it's a very tigh fit, can it lead to such behaviour = ? > > > Regards > > SalimBaba =A0 =A0 =A0 =A0 =A0 > > > --------------------------------------- =A0 =A0 =A0 =A0 > > Posted throughhttp://www.FPGARelated.com > > One obvious thing that can happen when you put a lot of logic in an > FPGA > is that the core power supply might not be strong enough to source the > required dynamic power. =A0You can get an estimate of the power > requirements > using Xpower and make sure your power source can handle the current. > You can also put an oscilloscope on the Vccint near an FPGA pin or > ball, > and trigger on a low-going spike. =A0This might either show that your > supply > cannot handle the current (usually when the spike goes very low or > stays > low for a long time) or that you have insufficient bypass caps to > handle > the sudden load increase. =A0Typically right after configuration there > is > a sudden large rise in Vccint supply current requirement. > > One thing you might see when the supply cannot handle the load is > that the FPGA starts up, gets a glitch in internal power, and then > goes back to its power-on reset state due to internal power > monitoring. > Then the power supply comes back up to voltage because in this > state the FPGA again takes much less current. > > Regards, > Gabor I've seen this before... I would suggest to turn off all of the clock sources/ oscillators on board first to see if the JTAG works any better ???Article: 149495
On Oct 29, 3:38=A0pm, n...@puntnl.niks (Nico Coesel) wrote: > johnp <jprovide...@yahoo.com> wrote: > >On Oct 28, 12:53=3DA0pm, "salimbaba" > ><a1234573@n_o_s_p_a_m.n_o_s_p_a_m.owlpic.com> wrote: > >> >Have you checked your timing constraints? =3DA0You could be lucky tha= t one > >> >PHY interconnect > >> >makes timing and the other doesn't. > > >> >John Providenza > > >> Exactly john, i figured out today that it was a timing constraints iss= ue. > >> One phy was meeting them and the other one wasn't. But xilinx wasn't > >> reporting it so i guess i was operating on the boundary. But john its = a > >> funny world we live in, we placed some constraints and it started to w= ork=3D > >. > >> Both ports working fine but then we added another thing in the design,= a > >> counter actually, and the design again stopped working on one end.Now,= th=3D > >e > >> port was switched. So, we took out some signals in chipscope and the > >> problem again switched ports :p funny, right ? :p =3DA0i don't know wh= at's > >> happening, i mean if it's a timing issue and xilinx isn't saying that > >> timing failed, then i guess it should work each time we run. what do u= ha=3D > >ve > >> to say on this ? =3DA0 =3DA0 =3DA0 =3DA0 =3DA0 > > >> --------------------------------------- =3DA0 =3DA0 =3DA0 =3DA0 > >> Posted throughhttp://www.FPGARelated.com > > >A suggestion - look at the timing report and make sure you have the > >timing analyzer > >report all unconstrained paths. =A0I always try to eliminate them so I > >know that I've > >got a fully constrained design. > > Don't try to eliminate them. Make sure to eliminate them! It is also > very important to constrain the IOB to flipflop and flipflop to IOB > paths. Those are easely forgotten but may cause the OP's problems. > > -- > Failure does not prove something is impossible, failure simply > indicates you are not using the right tools... > nico@nctdevpuntnl (punt=3D.) > -------------------------------------------------------------- I had a Lattice design with a global clock spec, global input spec and global output spec in addition to some more detailed specs... and still the timing analyzer reported unconstrained paths. When I asked the FAE about it he said you can never get rid of them all! If my constraints hadn't been pretty relaxed I would have pushed harder to get to the bottom of that. This is one of my beefs with static timing analysis. It is only valid if you have applied the constraints correctly. We can simulate and verify our design, but how do you verify the timing constraints? I think they should have a constraint reporting tool where you can pick specific end points and ask what the controlling timing spec is. Compare this to your intent and you have verification. The vendors seem to think it is ok to not verify constraints. RickArticle: 149496
On Oct 29, 1:28=A0pm, Ed McGettigan <ed.mcgetti...@xilinx.com> wrote: > > > The only placement constraint I have created is the pin number. > > > Gary. > > If you constraining both the GTX instance and the TX/RX ports change > to just constraining the GTX instance and the software will place the > TX/RX ports in the one and only place that it can. > > Ed McGettigan > -- > Xilinx Inc.- Hide quoted text - > > - Show quoted text - "The only placement constraint I have created is the pin number." It fails in MAP, before the GTX instance is placed. Unless I'm totally confused about how a GTX instance is constrained. Gary.Article: 149497
On Oct 29, 4:16=A0pm, ghelbig <ghel...@lycos.com> wrote: > On Oct 29, 1:28=A0pm, Ed McGettigan <ed.mcgetti...@xilinx.com> wrote: > > > > > > The only placement constraint I have created is the pin number. > > > > Gary. > > > If you constraining both the GTX instance and the TX/RX ports change > > to just constraining the GTX instance and the software will place the > > TX/RX ports in the one and only place that it can. > > > Ed McGettigan > > -- > > Xilinx Inc.- Hide quoted text - > > > - Show quoted text - > > "The only placement constraint I have created is the pin number." > > It fails in MAP, before the GTX instance is placed. =A0Unless I'm > totally confused about how a GTX instance is constrained. > > Gary. The error message says that the GTX is placed at site GTX_DUAL_X0Y0 and that it can't route the RXP0 pin to the site IPAD_X1Y25. You didn't say what part/package combo this is so I can't determine what the cause is. It could be that you used the RXP1 location in your constraints instead of RXP0. Ed McGettigan -- Xilinx Inc.Article: 149498
rickman <gnuarm@gmail.com> wrote: >On Oct 29, 3:38=A0pm, n...@puntnl.niks (Nico Coesel) wrote: >> johnp <jprovide...@yahoo.com> wrote: >> >On Oct 28, 12:53=3DA0pm, "salimbaba" >> ><a1234573@n_o_s_p_a_m.n_o_s_p_a_m.owlpic.com> wrote: >> >> >Have you checked your timing constraints? =3DA0You could be lucky tha= >t one >> >> >PHY interconnect >> >> >makes timing and the other doesn't. >> >> >> >John Providenza >> >> >> Exactly john, i figured out today that it was a timing constraints iss= >ue. >> >> One phy was meeting them and the other one wasn't. But xilinx wasn't >> >> reporting it so i guess i was operating on the boundary. But john its = >a > ha=3D >> >ve >> >> to say on this ? =3DA0 =3DA0 =3DA0 =3DA0 =3DA0 >> >> >> --------------------------------------- =3DA0 =3DA0 =3DA0 =3DA0 >> >> Posted throughhttp://www.FPGARelated.com >> >> >A suggestion - look at the timing report and make sure you have the >> >timing analyzer >> >report all unconstrained paths. =A0I always try to eliminate them so I >> >know that I've >> >got a fully constrained design. >> >> Don't try to eliminate them. Make sure to eliminate them! It is also >> very important to constrain the IOB to flipflop and flipflop to IOB >> paths. Those are easely forgotten but may cause the OP's problems. >> > >I had a Lattice design with a global clock spec, global input spec and >global output spec in addition to some more detailed specs... and >still the timing analyzer reported unconstrained paths. When I asked >the FAE about it he said you can never get rid of them all! If my Thats weird. IMHO you should be able to specify all the timing paths in a CPLD/FPGA design. >This is one of my beefs with static timing analysis. It is only valid >if you have applied the constraints correctly. We can simulate and >verify our design, but how do you verify the timing constraints? I >think they should have a constraint reporting tool where you can pick >specific end points and ask what the controlling timing spec is. IIRC the Xilinx tools can do this. -- Failure does not prove something is impossible, failure simply indicates you are not using the right tools... nico@nctdevpuntnl (punt=.) --------------------------------------------------------------Article: 149499
I'm just finishing up design of an analog data acquisition system (16 bits, 100 kHz sampling), and need to come up with a test / verification scheme. I've looked at some of the arbitrary waveform generators available, and they seem to be expensive, and not very accurate (13 or 14 bits). There seems to be a wide variety of inexpensive USB and firewire audio DACs available, and some of them are specified to 192 kHz sampling and 24 bits. If I could buy a DAC with 24 bits and 192 kHz (or higher) sampling I could write some code to generate a source file, play it through the DAC, capture the resultant signals in the test system, and analyze the system performance. Has anyone here done that? Can you offer any pointers? It's not clear from the specifications / manual of the DACs I've looked at whether filtering can be disabled. Most are specified from 20 Hz to 20 kHz, and seem intended to take in 44.1 kHz or 48 kHz, do a filtered up-conversion, and (presumably) have a sloppy output filter. Some specify that they can accept 192 kHz, but I've no idea what filters they use and whether they can be bypassed. Any thoughts / observations? Thanks Pete
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