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This isn't exactly VHDL, but here it goes... Check out http://www.microlet.com/yam/. Somewhere on that site they have the schematics for their early FPGA, which includes a Digital PLL implementation. You state you want to remove jitter in an incoming data stream... Without fully understanding your requirements, I'll go out on a limb and say that an all digital PLL is generally not a good choice to reduce jitter (unless your jitter's real bad to begin with). Jitter attenuators do the job, though http://www.dalsemi.com/DocControl/PDFs/2188.pdf... The Bell Labs tech journals from the mid 1970's have tons of articles on jitter in communication systems. The bible on PLLs theory is Phaselock Techniques by Gardner (1979-- good stuff, huh!!! I'd borrow this one from the library). Nothing on DPLLs though... http://www.amazon.com/exec/obidos/ASIN/0471042943/qid%3D930095120/002-958473 0-2474442 Phase Locked Loops : Design, Simulation, and Applications by Best has a very basic intro to DPLLs (I have the second edition, not the third). This one's pretty old too... http://www.amazon.com/exec/obidos/ASIN/0070060517/ref=sim_books/002-9584730- 2474442 Monolithic Phase-Locked Loops and Clock Recovery Circuits : Theory and Design from the IEEE is more current, and has a good PLL theory section. I'd buy this one, if nothing else but for the references. http://www.amazon.com/exec/obidos/ASIN/0780311493/ref=sim_books/002-9584730- 2474442 Good Luck JJ Mountain wrote in message <376FEE4C.AE377FD9@magenta.com>... >O.k. ... as a firm believer in RTFM, I have been searching all day for >digital PLL references / source code / models / book recomendations and >I have come up just about empty. I found a couple books on amazon.com >that are out of print .... (course I could check the library) ..... but >I am basically coming up empty. > >I am your basic hardware engineer who also does FPGA design (now in >VHDL) .... and I need to develop a Digital PLL for removing jitter in an >incoming datastream ..... so ... since I have never messed with any >PLL's .... I need a decent start point .... book references, web page >references, source code to start from, anything .... > >So, I come asking for any pointers any of you may have .... all help is >appreciated ..... > >Thanks, >John LedfordArticle: 17001
Stefan Wimmer wrote:
>
> Hi everybody,
>
> sorry for spreading this message into several newsgroups, but I'm looking for
> DS2 and E2 (yes, that's _2_!) framer chips (or FPGA cores) and don't really
> know where to start.
> Search engines didn't come up with something useful, but maybe someone out
> there in usenet land has a good tip (besides Transwich)?
You might try the traditional T1/E1 suppliers like Dallas and Crystal
Semi - they might be moving to second level or know who is. Boy, I
wonder if a 100 MIPS Scenix processor could do 8 Mbps E2? What a great
"virtual peripheral" that would make! (That's scenix.com in case you
want to check).
Good luck with it,
--
Gerry
@ Change "not_here" to "lsb"
##_/_\__[(
<0_0_0>
Article: 17002FPGAs are used all the time in wireless designs. In fact the majority of our APS-X208 and APS_X240 prototyping boards are used just for that. That is why we have features like direct digital synthesized clocks on the X208. You can see many examples of FPGA uses at our site: http://www.associatedpro.com Another great communications site which uses FPGAs is http://www.sigtek.com The products there are full full of XILINX and ORCA FPGAs. Anurag wrote: > Hi, > Can a FPGA's be used in Wireless Telecom applications ( e.g. 3G wireless, > software radios, wireless base-stations.....etc.) If yes, what specific > functions could the FPGA perform in these designs ? > > Any help/reference would be appreciated ! > Thanks in advance......... > AnuragArticle: 17003
> Actually, can't you just link the 3 .xnf files together?
> -Allen Middleton
> Dan Kuechle wrote:
> > I want to combine 3 xilinx designs (4005xl's) into a single 4013xl part.
> > The 3 designs are all done in foundation schematic entry, and are "flat".
XILINX software is quite weak in working with modules and linking, you
can
do so only on the netlist level or in EPIC but no linking of previously
mapped, placed and routed designs.
XILINX says it will improve this with version 2.1i expected in fall.
Andreas
--
---------------------------------------------------------------
Andreas C. Doering
Medizinische Universitaet zu Luebeck
Institut fuer Technische Informatik
Ratzeburger Allee 160
D-23538 Luebeck Germany
Tel.: +49 451 500-3741, Fax: -3687
Email: doering@iti.mu-luebeck.de
Home: http://www.iti.mu-luebeck.de/~doering
quiz, papers, VHDL, music
"The fear of the LORD is the beginning of ... science" (Proverbs 1.7)
----------------------------------------------------------------
Article: 17004
On Mon, 21 Jun 1999 07:40:44 GMT, "Jan Gray" <jsgray@acm.org.nospam>
wrote:
>Unfortunately, M1 does not allow you to constrain two FMAPs and an HMAP to a
>CLB, *if* none of the 3 H inputs is an F output, as is the case here. So
>"there ain't no such thing as a free mux."
I hadn't realised this - it will be interesting to see if M2.1 sorts
out the more more obscure mapper problems ("fixes previously unfixable
mapper bugs"... :) )
Cheers
Evan
Article: 17005Hi All, does anyone know of an online site where you can purchase small quantities ( say 10 ) Xilinx Spartan FPGAs with a delivery time of less than two weeks. Specifically interested in XCS30XL and XCS10XL. ThanksArticle: 17006
On Tue, 22 Jun 1999 13:25:04 -0700, Steven Casselman <sc@vcc.com> wrote: >A PCI target on an computer using an Intel PCI >bridge can expect 80MBytes/sec on transfers >going to a board and about 10-12MBytes/sec >comming from a board. > >These numbers vary. > >check out the work of Laurent Moll and Mark Shand >ftp://ftp.digital.com/pub/DEC/SRC/publications/shand/fccm97.pdf >It is one of the best papers on PCI performance out there. Thank you, This goes some way to answering the question, though the technology tested has been superseded, and the chipset bugs are (I hope!) a thing of the past. - Brian.Article: 17007
The company I work for is doing a prototype board using a Virtex to create a bunch of clocks for other chips on the board. We need to control skew very tightly and have been trying to find out what the internal skew on a given clock net is inside a Virtex array. I just downloaded the most recent PDF file of the Virtex data sheet (dated 5/13/99) and it has a table called "Virtex Clock Distribution Guidelines". This table is empty! While I really need more than "guidelines" - I need actual max skew data - these guidelines would be a start. Xilinx, when will you be filling in this table? There is another table on the same page (page 3-30) called "Virtex Clock Distribution Characteristics". I suspect this may be useful info but I do not understand what it means. It gives numbers for "Global clock PAD to output" and "IN input to OUT output". What are these referring to? I know all about Xilinx global clock buffers but it is unclear to me what they are trying to say here. Anyway what I really am after is skew data for an internal global clock net. Anybody know? TIA, Tom Liehe (work email: tom_liehe@stortek.com)Article: 17008
Steven Casselman <sc@vcc.com> wrote in article <376FF120.6A53D036@vcc.com>... > A PCI target on an computer using an Intel PCI > bridge can expect 80MBytes/sec on transfers > going to a board and about 10-12MBytes/sec > comming from a board. > > These numbers vary. Do you have more specific data? As you said, these numbers can be all over the place, so including a bit more about your 'results' would certainly be helpful... What was the size of the transfer? Sustained or burst? From where to where? What chip set? What CPU? Using the CPU to do the transfer, you might see that for a single (whose transfer size would be limited by the x86 instruction set) transfer, but certainly not sustained. AustinArticle: 17009
try http://www.em.avnet.com tom meany wrote: > Hi All, > does anyone know of an online site where you can purchase small quantities ( say 10 ) Xilinx > Spartan FPGAs with a delivery time of less than two weeks. Specifically interested in XCS30XL and > XCS10XL. > > Thanks -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 17010
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Graham- I'm sorry, but I do take offense to that "screw" comment. We've tried very hard to make enhance ease-of-use through IntelliFlow and IntelliFlow comes free with Workview Office software. However, we do have a service pack that enables IntelliFlow to work with Foundation FPGA Express. As for mixed schematic (for Xilinx) and language flows, there have been some serious problems with this flow using FPGA Express but these problems have been corrected via IntelliFlow in Workview Office 7.53. Viewlogic and Synopsys are working together to address these problems directly in FPGA Express in the future. If you have any more questions, please feel free to contact me directly. Regards, -Jim Graham Eastwood wrote: > Would designers who are using Viewdraw 7.5 and Foundation FPGA Express > 1.5i like to share there design flow methodology? I would like to hear > experiences for both VHDL and schematic as the top level. My own > design flow still centers around the Metamor compiler and schematic as > the top level and is as follows: > > 1) Setup the Foundation project manager to implement an XACT Step 6 > design using the appropriate target device. > 2) For each out of date VHDL source invoke the Metamor compiler and > compile > 3) From the project directory invoke a makefile which will run XNF2WIR > then VIEWGEN on each VHDL XNF file which is out of date with respect > to its schematic. > 4) From the project directory run "check -p projname" to ensure that > all the WIR files are derived from the schematics > 5) From Viewdraw and the top level schematic produce the Xilinx EDIF > listing > 6) Implement the design from the Xilinx design manager. > > This is cumbersome to say the least and evolved out of many XC5200 > series designs that I did. Now that I am targeting the Spartan series > I would like to use FPGA Express but I don't have the Viewlogic > version so I can't use Intelliflow (typical Viewlogic decision - screw > ease of use just make money) and I can't seem to marry buses between > Viewlogic and FPGA express when I invoke the tools manually. > > Please don't use this post as the start of yet another schematic only > versus VHDL only design entry flame war. Let's just assume for the > sake of discussion that a few people would like to use mixed entry > methods and limit the discussion to evaluating that flow. -- -------------------------------------------------------- James R. Kipps FPGA Marketing Manager jkipps@viewlogic.com Phone: (508) 303-5246 --------------------------------------------------------Article: 17012
Tibor- FPGA Express 3.2 is identical to FPGA Compiler II (3.2) with regard to language coverage and optimization algorithms. FPGA Compiler II is differentiated from FPGA Express in three ways: DC compatibility features, distribution channel, and price. With regard to DC compability features, FPGA Compiler II can read and write DC scripts and it can synthesize instantiated DesignWare components. While FPGA Express uses the same language front-end and is subset compatible with DC, it does not synthesize instantiated DesignWare components. With regard to distribution channel, FPGA Express is not sold directly by Synopsys. Rather, it is sold by Viewlogic and VeriBest as part of an FPGA-in-Systems design solution. FPGA Express can also be obtained in a vendor restricted form from Xilinx, Lattice, and Lucent. Viewlogic is the only channel that markets FPGA Express for both the windows and UNIX platform. With regard to price, FPGA Express can be purchased at several price points depending on which options you need. FPGA Compiler II comes with all options included, which makes its price higher than FPGA Express. However, if you are purchasing DC from Synopsys you might get a break on the price of FPGA Compiler II. As for which is best for Xilinx, FPGA Express 3.2 and FPGA Compiler II (3.2) deliver the exact same results (san the use of DesignWare). In all fairness, I should say that the two main competitors of FPGA Express/FPGA Compiler II also give good results for Xilinx. I will also admit to not doing so well for the Virtex family in the 3.1 release, but the 3.2 release has made tremendous improvements in its support of Virtex and I recommend it. All three tools (FPGA Express, Synplify, and Leonardo) can be evaluated at no charge. If you like, you can forward me your phone number and I'll see that you get an eval license for the Viewlogic FPGA design solution, which includes FPGA Express. Regards, -Jim Tibor Szolnoki wrote: > What is differences the Synopsys FPGA Express 3.2 and FPGA Compiler 3.2 ? > > Which is the best to Xilinx FPGA VHDL synthesize and optimize? > > Thank you: > > Tibor Szolnoki. > fpga@dartsgame.com -- -------------------------------------------------------- James R. Kipps FPGA Marketing Manager jkipps@viewlogic.com Phone: (508) 303-5246 --------------------------------------------------------Article: 17013
Hi. DC is meant for ASIC synthesis. I don't recommend it for FPGAs. I just posted another email about FPGA Compiler II verses FPGA Express, so you might want to refer to that. Basically, FPGA Compiler II is great if you have DC and are taking you design straight from the FPGA prototype to the ASIC. If you are not immediately going from prototype to ASIC, then you should consider FPGA Express or its competitors. At Viewlogic, we focus on design solutions for FPGA-on-board. We resell Synopsys' FPGA Express and automate the FPGA design flow, including place and route, using a tool called IntelliFlow. However, this is not the forum for a marketing pitch. If you'd like to talk further, email me directly. Regards, -Jim However, if you are designing vermon1055@my-deja.com wrote: > Hi, > I am a beginner for the FPGA synthesis. > I would very much appreciate your comments and > experiences on the following > question. > > The tools that we currently have is Synopsys DC > (design compiler)(UNIX) > and Altera MAX plus II (PC). > > I am trying to synthesis the verilog code by > using Synopsys DC targeting > to the library provided by Altera(flex10k.db, > max7000.db,....). And then > save it as an EDIF format for Altera to do the > place & route. > > What is the difference if I use the Synopsys FPGA > compiler instead of the DC? > (in turns of speed and area) > > Do we really need to have the Synopsys FPGA > compiler to do the job? > > Thanks! > > Sent via Deja.com http://www.deja.com/ > Share what you know. Learn what you don't. -- -------------------------------------------------------- James R. Kipps FPGA Marketing Manager jkipps@viewlogic.com Phone: (508) 303-5246 --------------------------------------------------------Article: 17014
Sven Beyer wrote: > > Utku Ozcan schrieb: > > > > > > I don't use the SPO's of some DP RAM's on XC40150XV. > > > > NGDBUILD and XNF2NGD give warnings. Do these warnings > > > > imply a possibly bad routing architecture? Shall I > > > > use the commands which ignore these pins? I have > > > > used following command but the warnings didn't go away: > > > > > > > > NET "dp_ram_spo<*>" TIG=TS01; > > > > > > > > Shall this TS01 be defined for write clock of the Dual > > > > Port RAM? Shall I use such a command to improve the > > > > performance? > > > > > > > > Utku > > > > The warnings can be safely ignored, but there is a way to get rid of > them (so finding the really interesting warnings in the report becomes > much, much easier): > You can just modify the XILINX DP-RAM Macros so they only contain the > DP-Output. Do not worry, you won't be able to change the macros in the > original XILINX library. Just save the modified macros in your own > library and use these instead of the original XILINX versions. > This little trick helped me very much since I got more than 300 warnings > just because of this single problem. > > Sven Sven, the macros are generated by Xilinx' LOGIBLOX. I don't use schematic or so. The synthesizer is Synplify. Pardon me I haven't understood the method of modification. I am using Verilog as design entry and Synplify requires black-boxed Verilog netlists of macros. Shall I drop out SPO ports inside Verilog netlists of macros? I really haven't understood in which stage of Top-Down design flow the SPO's shall be handled. UtkuArticle: 17015
In article <376EAE2E.15CB630F@bham.ac.uk> Steve Charlwood <s.m.charlwood@bham.ac.uk> writes: >Hi. > >Does anyone have, or could direct me towards, datasheets or other >information on the following XC4000-series variants? > >XC4000, XC4000A, XC4000D, XC4000H, XC4000L XC4000 The original version of the family XC4000A Same CLB architecture as XC4000, less routing : cheaper XC4000D Same as XC4000, no CLB RAM : cheaper XC4000H Same CLB architecture as XC4000, twice as many I/O XC4000L Same CLB architecture as XC4000, lower power > >I would like to be able to track the technological and architectural >changes made to the XC4000-series chronologically, and look at the >factors which influenced the changes. > >Any help would be appreciated. > >Regards, > >Steve > > >_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/ > >Digital Systems & Vision Processing Group >School of Electronic & Electrical Engineering >University of Birmingham, Edgbaston, Birmingham, B15 2TT >e-mail: s.m.charlwood@bham.ac.uk >tel: +44 (0)121-414-4340 (shared)/fax: +44 (0)121-414-4291 > >_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/Article: 17016
I'll humbly (ahem) submit my recent programmable logic benchmarking article for review. Three FPGAs (Xilinx Virtex, Lucent Orca3, Atmel AT40K) and three CPLDs (Vantis Mach5, Lattice ispLSI 5000V and Philips XPLA2). Feedback always appreciated! Article: http://www.ednmag.com/ednmag/reg/1999/052799/11cs.htm Addendum (with all the data): http://www.ednmag.com/ednmag/reg/1999/052799/downloads/11cs_add.htm >Hello, > >I am searching for benchmarks of circuit designs for FPGAs. Does anybody >know where I could get such benchmark data? > >The benchmarks will be analyzed in order to obtain statistical results >for my master thesis. My thesis is dealing with FPGA task arrangement. > >Thanks for each proposal > >cheers > >Bernd > Brian Dipert Technical Editor: Memory, Multimedia and Programmable Logic EDN Magazine: The Design Magazine Of The Electronics Industry http://www.ednmag.com 1864 52nd Street Sacramento, CA 95819 (916) 454-5242 (voice), (916) 454-5101 (fax) ***REMOVE 'NOSPAM.' FROM EMAIL ADDRESS TO REPLY*** mailto:bdipert@NOSPAM.pacbell.net Visit me at http://members.aol.com/bdipertArticle: 17017
Hi, I am trying to decide on a 0.25um ASIC standard cell library between Artisan and Avant! for a high speed 200K gate design. I am specifically concerned about the correlation between the simulation results and the silicon. I would greatly appreciated your personal opinions regarding anyone one of them. A comparison between the two will be great, but your personal good (or bad) experience would help as well. Thanks for your quick response. Sheila Sent via Deja.com http://www.deja.com/ Share what you know. Learn what you don't.Article: 17018
Hi, I am trying to decide on a 0.25um ASIC standard cell library between Artisan and Avant! for a high speed 200K gate design. I am specifically concerned about the correlation between the simulation results and the silicon. I would greatly appreciated your personal opinions regarding anyone one of them. A comparison between the two will be great, but your personal good (or bad) experience would help as well. Thanks for your quick response. Sheila Sent via Deja.com http://www.deja.com/ Share what you know. Learn what you don't.Article: 17019
I am trying to evaluate xc4000xv and virtex devices for a Verilog
design using synopsys design compiler 3.4b and fpga compiler.
Using virtex device the script flow through synopsys is smooth.
But for xc4085xl and xc40150xv devices, during compilation of some
modules synopsys issues messages
"...unable to resolve reference "AN2I" in..." (AN2I is just for
example many other symbols come up)
I tried to analyze problem for one module having FSM description and
3 simple sequential submodules in it.
Actually the top module receives 3 asynchronous reset signals, which
also goes to lower modules. According to requirement all of them or
some of them are logically ANDed and the resulting signal is
used as RESET signal.
In hope of using global nets in FPGA, I was giving
set_dont_touch_network for these three reset signals. But then
for 4000 series it gives the above mentioned message.
For virtex devices this problem is not there.
If I remove don't touch on this nets, the problem goes away.
Also during compilation of top level module the lower level
modules also gives this problem. But during compilation of
lower level module itself, the problem doesn't come.
Code fragment is given below.
// syntax is not exact
module
input reset_1_in_n;
input reset_2_in_n;
input reset_3_in_n;
wire reset_n = reset_1_in_n && reset_2_in_n;
sub_module s1(
.reset_1_in_n(reset_1_in_n),
.reset_2_in_n(reset_2_in_n),
.reset_3_in_n(reset_3_in_n),
.....
)
/* FSM logic with reset reset_n */
always @( posedge clk or negedge reset_n)
begin
...
end
endmodule
Can anybody help me!!!
Sent via Deja.com http://www.deja.com/
Share what you know. Learn what you don't.
Article: 17020
In article <37709264.2276263@news.dial.pipex.com>, ems@riverside-
machines.com.NOSPAM writes
>>Unfortunately, M1 does not allow you to constrain two FMAPs and an HMAP to a
>>CLB, *if* none of the 3 H inputs is an F output, as is the case here. So
>>"there ain't no such thing as a free mux."
>
>I hadn't realised this - it will be interesting to see if M2.1 sorts
>out the more more obscure mapper problems ("fixes previously unfixable
>mapper bugs"... :) )
I'd be interested to hear from people on this newsgroup whether this is
a bug in the tools or in the data sheets and devices (although I can't
believe the latter).
While the Xilinx UK help desk has normally been pretty helpful, all they
said on this one a while ago was "You can't use three inputs". Perhaps I
was a bit provocative, but they could not tell me whether it was the
tools which wantonly threw away the functionality or the data sheets
which lied about the devices (or perhaps my misreading the data sheets
but they seem pretty clear that the three inputs are available unless
you are using a Reset signal other than GSR).
Paul
--
Paul Walker 4Links phone/fax
paul@4Links.co.uk P O Box 816, Two Mile Ash +44 1908
http://www.4Links.co.uk Milton Keynes MK8 8NS, UK 566253
Article: 17021Does anyone know if Stan Baker's www.reconfig.com website is moved or just gone? -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 17022
I'm answering my own post since there's been no response. I'll try to be a little more specific. I did get an email (thanks) saying this problem is handled by the PLL in the Virtex but I don't think that addresses my real concern: What we really want to know is the skew BETWEEN individual clock pins, specifically output IOB flip-flop clock pins, on a single global clock net. I realize there is also a skew from the input pad to the internal global net, but that does not matter so much as long as we can control the timing of clocked output signals with respect to each other. Tom Liehe (moox@flatland.dimensional.com) wrote: : : I just downloaded the most recent PDF file of the Virtex data : sheet (dated 5/13/99) and it has a table called "Virtex Clock : Distribution Guidelines". This table is empty! While I really : need more than "guidelines" - I need actual max skew data - : these guidelines would be a start. Xilinx, when will you be : filling in this table? : : Anyway what I really am after is skew data for an internal : global clock net. Anybody know? Thanks, Tom LieheArticle: 17023
Tom Liehe wrote: > > I'm answering my own post since there's been no response. > I'll try to be a little more specific. I did get an > email (thanks) saying this problem is handled by the > PLL in the Virtex but I don't think that addresses my > real concern: > > What we really want to know is the skew BETWEEN individual > clock pins, specifically output IOB flip-flop clock pins, > on a single global clock net. I realize there is also a skew > from the input pad to the internal global net, but that does > not matter so much as long as we can control the timing of > clocked output signals with respect to each other. > > Tom Liehe (moox@flatland.dimensional.com) wrote: > : > : I just downloaded the most recent PDF file of the Virtex data > : sheet (dated 5/13/99) and it has a table called "Virtex Clock > : Distribution Guidelines". This table is empty! While I really > : need more than "guidelines" - I need actual max skew data - > : these guidelines would be a start. Xilinx, when will you be > : filling in this table? > : > : Anyway what I really am after is skew data for an internal > : global clock net. Anybody know? > > Thanks, > Tom Liehe The vendors are not prone to provide such data since there is little need for it. Most FPGA vendors will guaranty the hold time requirement is met within their parts. Because the internal clock skew normally has little effect on any other synchronous function, they don't bother characterizing it. But it is odd that they have a table in the data sheet but don't bother to fill in the data. I would guess that they plan to provide the data, but haven't gotten around to pinning down the exact numbers. I am suprized that you haven't heard from one of the Xilinx FAEs that post in this newsgroup. -- Rick Collins rick.collins@XYarius.com remove the XY to email me. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 17024
Its a bug in the tools (well M1.4 at least)! I was down that road
several years ago. The only way I could use the H-LUT (at that time) as
a three input device (with F,G and both FFs used) was to make a hard
macro and use the PCF (Physical Constraints File) for their placement.
It wasn't fun but I had no other choice but to make it work.
Maybe it's fixed in the newer M1 versions? There are probably more
eloquent solution out there than mine. I feel your pain man...
Steve "bear skins and stones" Swearingen
Paul Walker wrote:
>
> In article <37709264.2276263@news.dial.pipex.com>, ems@riverside-
> machines.com.NOSPAM writes
> >>Unfortunately, M1 does not allow you to constrain two FMAPs and an HMAP to a
> >>CLB, *if* none of the 3 H inputs is an F output, as is the case here. So
> >>"there ain't no such thing as a free mux."
> >
> >I hadn't realised this - it will be interesting to see if M2.1 sorts
> >out the more more obscure mapper problems ("fixes previously unfixable
> >mapper bugs"... :) )
>
> I'd be interested to hear from people on this newsgroup whether this is
> a bug in the tools or in the data sheets and devices (although I can't
> believe the latter).
>
> While the Xilinx UK help desk has normally been pretty helpful, all they
> said on this one a while ago was "You can't use three inputs". Perhaps I
> was a bit provocative, but they could not tell me whether it was the
> tools which wantonly threw away the functionality or the data sheets
> which lied about the devices (or perhaps my misreading the data sheets
> but they seem pretty clear that the three inputs are available unless
> you are using a Reset signal other than GSR).
>
> Paul
> --
> Paul Walker 4Links phone/fax
> paul@4Links.co.uk P O Box 816, Two Mile Ash +44 1908
> http://www.4Links.co.uk Milton Keynes MK8 8NS, UK 566253
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