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I have used Quickswitch for 3.3/5V xlation and it works great. P/n: QS34X2245. I had to interface altera max7032aelc 3.3v part to 5v ttl logic. -Dalip. myself wrote: > Hi I will need to interface the spartan-II 3.3V I/O to 5V standard > logic levels. eg address lines out of the FPGA to a older 5v dram. > > What ic's ore out there that could perforn this function? > > I looked at the old 4050 that converts cmos to ttl but it was ment to > step higher voltage cmos down to ttl 5v levels. > > Any suggestions or part #'s appreciated > > MartinArticle: 22951
I would suggest that you will get a better, more reliable answer to your question by running a test rather than by running a Spice analysis. If you do the test properly you can extend the results to the actual application. I have done thousands of hours of SPICE work and usually with good results but extreme care must be taken to assure that the models you are using adequately simulate the effects you need to study. Unless the models you are using specifically are known to accurately represent the effects you need to simulate, you would be better off to look at the product spec sheet, determine the operating mode most likely to give the worst case results, construct a test cicuit to exercise these modes and instrument your test for the appropriate measurements. Spice models usually do a totally inadequate job of simulating ANYTHING other than the simplest functional features. Even then, they sometimes fail this job. Spice in the hands of an inexperienced user is likely to produce a ton of computerized garbage. The results are likely to be believed by managers however. Especially if you can get some nice looking color charts of your output :--) JK Password Recovery Software http://www.crak.com Joe Wetstein <yose@wam.umd.edu> wrote in message news:8hgnoj$ptt@rac6.wam.umd.edu... > > Hello. I am trying to do some analysis on parts of a custom board that we > are designing. Specifically, I am trying to analyze a Virtex FPGA > connected to a few banks of SDRAM, and want to model the current draw from > the memories during an autorefresh cycle, as well as the current draw (to > make sure that the fpga can provide the drive) for both registered > (buffered) and unregistered memory modules. I have the spice models for > the memory, and the IBIS models for the Xilinx part. > > Problem is that I haven't used SPICE in about 10 years. > > Has anyone done anything like this before? > > Does anyone have any (non flame) recommendations for me? > > Does anyone have any book recommendations to get up to speed on SPICE VERY > VERY quickly? > > IS there a better group to post to? > > Any advice or solutions would be appreciated. > > Thanks, > Joe > > yose@wam.umd.edu >Article: 22952
steveh@link-comm.com (Steve Holle) writes:
> I like your Perl script. Sorry I couldn't find it earlier. I have
> two questions.
> 1) Can it be compiled so that I don't need to run an interpreter every
> time.
now, this is going to be far off topic: no, it cannot be compiled (*),
but I consider this no disadvantage. This way, the program is portable
and can be run in windows and linux.
(*) Yes, there is a perl compiler, but it is not really an option
for small scripts like these.
> 2) Is it relatively easy to add to a make file so that the conversion
> is done automatically when built?
Sure. I see no difference between
file.c file.h: file.bit
BIT2C.EXE file.bin
and
file.c file.h: file.bit
PERL.EXE bit2c.pl file.bin
regards,
chm.
--
cmautner@ - Christian Mautner
utanet.at - Vienna/Austria/Europe
Article: 22953In general the answer to your question is that an FPGA doen't compare well to a purpose built processor for value or MIPs. You would put a processor in FPGA for prototyping, or homemade special purpose designs, etc, "one-of" kinds of things where engineering costs far outweight part costs. Another application might be if you had a large amount of assembly or binary code for a discontinued processor, but even then you could probably emulate in software with a new processor cheaper and easier than recreating a legacy design. Regards! In article <8h42k1$f08$1@bagan.srce.hr>, "Domagoj" <domagoj@engineer.com> wrote: > Hi, > Does anybody have any data about cost/performance as a function > of performance (MIPS) for microprocessors in FPGA ? > > Any information about processors in fpga would be highly appreciated. > > thanks, > ------------------------------------------- > - Domagoj - > - Domagoj@engineer.com - > ------------------------------------------- > > Sent via Deja.com http://www.deja.com/ Before you buy.Article: 22954
Leinonen Mika wrote: > > I need a program that converts PLA description to ABEL HDL. > Where can I find such (or maybe I'll have to program it myself)? > The PLA description looks like this: > AAAA AAAA OOOO > 7654 3210 4321 > --------------- > 0000 0000 1011 > .... .... .... > 0111 0111 1011 > 0111 1000 1010 > .... .... .... > 0111 1111 1010 > > 1000 0000 0110 > 1000 0001 0111 > 1000 0010 1111 > 1000 0011 1111 > 1000 0100 0010 > 1000 0101 0011 > 1000 0110 1010 > 1000 0111 1011 > 1000 1000 0110 > ... Continues > -- > mika.leinonen"at"cc.tut.fi > http://www.students.tut.fi/%7Eleinone3/ I am not familar with the format above, but the Berkley tabular PLD format is very similar, and the Philips/Xilinx Coolrunner XPLA designer SW ( free on WEB ) has a mode that allows Compile of a .TT2 file, and one of the reports produced is a .PHD source code file. This is very close to Abel HDL. -jg -- ======= 80x51 Tools & PLD IP Specialists ========= = http://www.DesignTools.co.nzArticle: 22955
When you say "5V standard logic levels", do you mean TTL or CMOS? I believe most memory devices work with TTL levels. In that case you will not need logic level conversion since 3.3 volt IOs (including Spartan II LVTTL) is compatible with 5 volt TTL. The logic low output is 0.4v max, input 0.8v max. Logic high is 2.4v output min, 2.0v input min (IIRC). Most 3v devices support this unless they are CMOS where you need to drive their inputs to about 0.7 Vdd or 3.3 x 0.7 x 1.05 (vdd max range) or 2.4255v which is just ever so slightly out of spec. If your memory has CMOS logic level inputs, then you will need a logic conversion device. Most any 74AHCT device should do the job. Or you should be able to get away with 5 volt pullups on the Spartan II outputs. Nothing is needed on the Spartan II inputs. IIRC there is an appnote on this on the Xilinx web site. Try http://support.xilinx.com/techdocs/8654.htm. This appnote refers to the Virtex devices, but the Spartan II parts are the same as Virtex. myself wrote: > > Hi I will need to interface the spartan-II 3.3V I/O to 5V standard > logic levels. eg address lines out of the FPGA to a older 5v dram. > > What ic's ore out there that could perforn this function? > > I looked at the old 4050 that converts cmos to ttl but it was ment to > step higher voltage cmos down to ttl 5v levels. > > Any suggestions or part #'s appreciated > > Martin -- Rick Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 22956
As the data sheet describes, Spartan-II outputs are 5-V tolerant ( given the appropriate I/O standard). That means, you only need a pull-up resistor to 5 V on each output ( 470 Ohm may be a good value) You can improve the rise time significantly ( or dramatically, depending on the capacitive load ) by using the feedback trick that I have described several times in this newsgroup. Peter Alfke, Xilinx Applications. myself wrote: > Hi I will need to interface the spartan-II 3.3V I/O to 5V standard > logic levels. eg address lines out of the FPGA to a older 5v dram. > > What ic's ore out there that could perforn this function? > > I looked at the old 4050 that converts cmos to ttl but it was ment to > step higher voltage cmos down to ttl 5v levels. > > Any suggestions or part #'s appreciated > > MartinArticle: 22957
I answered this question a few minutes ago, assuming that CMOS levels ( Vih = 70% of Vcc ) are required. Regarding the infamous 0.4 V, 0.8 V, 2.0 V and 2.4 V : these are numbers that T.I. established in the mid-sixties for bipolar TTL logic. They have been copied mindlessly ever since, even for CMOS complementary outputs. In reality, the pull-up p-channel transistor, when on, is a <30 Ohm resistor, and the pull-down n-channel transistor, when on, is <20 Ohm. No offset whatsoever. So, at negligible dc load ( when driving CMOS inputs) the output swings rail-to-rail, without any measurable dc offset. CMOS is nice, much nicer than bipolar TTL with its saturation offset and relatively high input currents. Peter Alfke, Xilinx Applications =============================================== Rickman wrote: > When you say "5V standard logic levels", do you mean TTL or CMOS? I > believe most memory devices work with TTL levels. In that case you will > not need logic level conversion since 3.3 volt IOs (including Spartan II > LVTTL) is compatible with 5 volt TTL. The logic low output is 0.4v max, > input 0.8v max. Logic high is 2.4v output min, 2.0v input min (IIRC). > Most 3v devices support this unless they are CMOS where you need to > drive their inputs to about 0.7 Vdd or 3.3 x 0.7 x 1.05 (vdd max range) > or 2.4255v which is just ever so slightly out of spec. > > If your memory has CMOS logic level inputs, then you will need a logic > conversion device. Most any 74AHCT device should do the job. Or you > should be able to get away with 5 volt pullups on the Spartan II > outputs. Nothing is needed on the Spartan II inputs. IIRC there is an > appnote on this on the Xilinx web site. Try > http://support.xilinx.com/techdocs/8654.htm. This appnote refers to the > Virtex devices, but the Spartan II parts are the same as Virtex. > > myself wrote: > > > > Hi I will need to interface the spartan-II 3.3V I/O to 5V standard > > logic levels. eg address lines out of the FPGA to a older 5v dram. > > > > What ic's ore out there that could perforn this function? > > > > I looked at the old 4050 that converts cmos to ttl but it was ment to > > step higher voltage cmos down to ttl 5v levels. > > > > Any suggestions or part #'s appreciated > > > > Martin > > -- > > Rick Collins > > rick.collins@XYarius.com > > Ignore the reply address. To email me use the above address with the XY > removed. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design > > Arius > 4 King Ave > Frederick, MD 21701-3110 > 301-682-7772 Voice > 301-682-7666 FAX > > Internet URL http://www.arius.comArticle: 22958
I don't get it, maybe I am dense. But: For 3.3 V outputs to drive 5-V TTL-level inputs, you need nothing whatsoever in-between. And worse: I cannot see how the QuickSwitch circuit below can provide the voltage boost you do need for driving CMOS-level inputs. Forget the solution given below. Peter Alfke ====================================== "Dalip K. Singh" wrote: > I have used Quickswitch for 3.3/5V xlation and it works great. > P/n: QS34X2245. I had to interface altera max7032aelc 3.3v part to 5v > ttl logic. > > -Dalip. > [Image] > > myself wrote: > >> Hi I will need to interface the spartan-II 3.3V I/O to 5V standard >> logic levels. eg address lines out of the FPGA to a older 5v dram. >> >> What ic's ore out there that could perforn this function? >> >> I looked at the old 4050 that converts cmos to ttl but it was ment >> to >> step higher voltage cmos down to ttl 5v levels. >> >> Any suggestions or part #'s appreciated >> >> Martin >Article: 22959
"Joe Wetstein" <yose@wam.umd.edu> wrote in message news:8hgnoj$ptt@rac6.wam.umd.edu... > > Hello. I am trying to do some analysis on parts of a custom board that we > are designing. Specifically, I am trying to analyze a Virtex FPGA > connected to a few banks of SDRAM, and want to model the current draw from > the memories during an autorefresh cycle, as well as the current draw (to > make sure that the fpga can provide the drive) for both registered > (buffered) and unregistered memory modules. I have the spice models for > the memory, and the IBIS models for the Xilinx part. > > Problem is that I haven't used SPICE in about 10 years. > > Has anyone done anything like this before? > > Does anyone have any (non flame) recommendations for me? > Your current consumption will be hard to get accurate in a simulator. Anyhow, proper decoupling of the memories should make this short current spike "invisible" to the rest of the board (dimensioned by C * dV = I * t), typically ~100 nF per SDRAM (use 3x 33nF, 5x 22nF or similar per SDRAM, not 1x 100nF. 100nF ceramics are usually too slow for 100+ MHz systems) On the signal integrity check I can recommend using BoardSim for HyperLynx (http://www.hyperlynx.com) You feed it IBIS models of your ICs (available on the web) and PCB geometries. You can then simulate signal propagation and crosstalk. It will also give you recommendations on signal termination, e.g. for bussed clock signals. I'm not sure whether you'll find IBIS for memory *modules* as well though...... Regards, - OlafArticle: 22960
Sorry if this post is inappropriate, but I have a friend and client who is looking for an experienced Director of Engineering for his pre-IPO FPGA/ASIC design and consulting firm, with offices in Silicon Valley and Tokyo. Anyone with interest please see the following link: http://www.asia-net.com/show_job.php3?id=7397 Thanks! Sent via Deja.com http://www.deja.com/ Before you buy.Article: 22961
Dave Try embeddedsol.com website they have boards that will fully match your criteria Tony In article <8gse2r$ejk$1@nnrp1.deja.com>, dave_admin@my-deja.com wrote: > Hi, > > I am looking for a VirtexE prototype board with at least 1 million > gates capability (1 VirtexE1000 or bigger) and PCI interface. > > regards, > Dave. > > Sent via Deja.com http://www.deja.com/ > Before you buy. > Sent via Deja.com http://www.deja.com/ Before you buy.Article: 22962
Hi
generating a CORE with a pre-placement can be done by adding some placement
attributes to the primitives. But how can someone put also some pre-routing to
the CORE to ensure that some timing constrains are retained?
Additionally how can a component be locked to a specified block that is normally
not used by the design. We have one case where we want to use a IBUF and a OBUF
Element and simply connect them together. We don't want to waste a IOB with PAD
for doing that. Therefore we want to lock the buffers to a IOB that has not PAD
attached. The destination architecture is Vitrex V400-BG560.
It works fine in the FPGA Editor but we found no way to do that with normal
constrains.
Thanks for your help.
Harald
Ray Andraka wrote:
> Unless you intend to package and sell the CORE, there is really no need to
> put it under coregen. Coregen is not much more than a pretty wrapper for
> edif netlist files. Instead, just instantiate your code as a component in a
> hierarchical VHDL design. If you are trying to do placement as well, I've
> found the best way to do it hierarchically is to put placement attributes
> right into the VHDL, which means you build the components from the
> structural level (I think this is probably why you want to create a
> component under the COREGEN). Alternatively, you can instantiate your core
> as a blackbox in VHDL under which you have an edif netlist (that is all
> coregen does with it). Look under the design guides for mixed schematic/HDL
> design methodology for details on instantiating black boxes in your design.
>
>
> --
> -Ray Andraka, P.E.
> President, the Andraka Consulting Group, Inc.
> 401/884-7930 Fax 401/884-7950
> email ray@andraka.com
> http://www.andraka.com or http://www.fpga-guru.com
---------------------------------------------------------------------------
Harald Simmler Lehrstuhl fuer Informatik V
Universitaet Mannheim
eMail: simmler@ti.uni-mannheim.de Germany
Article: 22963visit the OpenCores site there is a DCT project http://www.opencores.org Seb C wrote: > I've a small problem, i don't know how to perform a DCT (Discrete cosine > transform) implementation using FPGA for a picture for example, i can > compute DCT on a paper but not in XILINX for an FPGA, if some one can help > me, don't hesitate to do it !! > > Thx in advance > > SEBArticle: 22964
Hi, Are you looking for free tools? Do you want free open hw designs? You can find the most known Free tools and open hw designs on a single cdrom For more information visit the OpenTech cdrom page at http://www.opencores.org/OIPC/projects/cdrom.shtml Jamil KhatibArticle: 22965
Thanks for the information I will checkout that app note Peter could you repost your feedback trick? Martin On Tue, 06 Jun 2000 03:03:14 GMT, Peter Alfke <palfke@earthlink.net> wrote: >As the data sheet describes, Spartan-II outputs are 5-V tolerant ( given >the appropriate I/O standard). >That means, you only need a pull-up resistor to 5 V on each output ( 470 >Ohm may be a good value) >You can improve the rise time significantly ( or dramatically, depending >on the capacitive load ) by using the feedback trick that I have >described several times in this newsgroup. > >Peter Alfke, Xilinx Applications. > >myself wrote: > >> Hi I will need to interface the spartan-II 3.3V I/O to 5V standard >> logic levels. eg address lines out of the FPGA to a older 5v dram. >> >> What ic's ore out there that could perforn this function? >> >> I looked at the old 4050 that converts cmos to ttl but it was ment to >> step higher voltage cmos down to ttl 5v levels. >> >> Any suggestions or part #'s appreciated >> >> Martin >Article: 22966
Peter Alfke <palfke@earthlink.net> wrote in message news:393C69E8.7679BABD@earthlink.net... > As the data sheet describes, Spartan-II outputs are 5-V tolerant ( given > the appropriate I/O standard). > That means, you only need a pull-up resistor to 5 V on each output ( 470 > Ohm may be a good value) > You can improve the rise time significantly ( or dramatically, depending > on the capacitive load ) by using the feedback trick that I have > described several times in this newsgroup. When doing input and output on the same pin, do you think it's better to put a pull up + a serie resistor than an active voltage translator (a 74AHCT like Rickman said)? It's between a Spartan XL and a non TTL tolerant 5V CMOS. Marc BattyaniArticle: 22967
Dan Kuechle <dan_kuechle@i-tech.com> wrote in message news:01bfcf02$87f61980$c4f262d1@Dan.i-tech.com... > Does anyone know if the new Virtex-E LVDS differential I/O will work > with a SCSI LVD bus? I'm interested in monitoring the SCSI bus, so I > would only be inputing SCSI signals. I'm interested in Ultra160 and > Uttra320 speeds. > > Thanks > > Dan Hi Dan, The Virtex has the classic LVDS interface levels, whereas SCSI LVD is asymmetric. As near as I can work out, the only impact would be noise immunity. I plan to try it out one of these days to see what it does. If you want a good side-by-side comparison of the two voltage levels, compare the following TI parts: SN75976ADGG which is RS-485 LVDS, and SN75LVDM976A which is SCSI LVD. I'd appreciate any info you may discover on this topic. One caveat -- I don't think you'll be able to bugger the Virtex into being multimode compatible. -- Gary Watson gary@nexsan.sex (Change dot sex to dot com to reply!!!) Nexsan Technologies Ltd. Derby DE21 7BF ENGLAND http://www.nexsan.comArticle: 22968
More chips, more packages, more speeds,
but no production until September, oh my!
VQ100C TQ144C CS144C PQ208C FG256C FG456C
XC2S15-5 $7.10 $8.15 $10.20
XC2S30-5 $10.05 $11.55 $12.55 $13.90
XC2S50-5 $12.85 $14.75 $16.65
XC2S100-5 $17.60 $19.55 $24.65 $31.00
XC2S150-5 $21.60 $27.00 $35.10
XC2S200-5 $26.25 $32.45 $39.10
I have updated http://recycle.lbl.gov/xc2search.html with this
info. If anyone from Xilinx (or with better spies than me) can
replace these rumors with real schedule info, please do so.
- Larry Doolittle <LRDoolittle@lbl.gov>
Article: 22969The quickswitch part is used when you have 3 volt parts that are not 5 volt tolerant. I don't remember the exact details of voltage levels, etc., but they have an appnote on their website showing how this can be used this way. I think if you power the quickswitch part from the low side, it will not pass the higher voltage since the gate drive level is too low to keep the pass transistor turned on. As you know, for the Spartan II parts, you don't need anything since the parts are 5 volt tolerant. But I don't believe his memory parts are 5 volt CMOS anyway. So as you say, he does not need any circuitry for the interface function. Peter Alfke wrote: > > I don't get it, maybe I am dense. But: > For 3.3 V outputs to drive 5-V TTL-level inputs, you need nothing > whatsoever in-between. > And worse: I cannot see how the QuickSwitch circuit below can provide > the voltage boost you do need for driving CMOS-level inputs. Forget > the solution given below. > > Peter Alfke > ====================================== > > "Dalip K. Singh" wrote: > > > I have used Quickswitch for 3.3/5V xlation and it works great. > > P/n: QS34X2245. I had to interface altera max7032aelc 3.3v part to > > 5v ttl logic. > > > > -Dalip. > > [Image] > > > > myself wrote: > > > >> Hi I will need to interface the spartan-II 3.3V I/O to 5V standard > >> > >> logic levels. eg address lines out of the FPGA to a older 5v dram. > >> > >> What ic's ore out there that could perforn this function? > >> > >> I looked at the old 4050 that converts cmos to ttl but it was ment > >> to > >> step higher voltage cmos down to ttl 5v levels. > >> > >> Any suggestions or part #'s appreciated > >> > >> Martin > > -- Rick Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 22970
myself wrote: > Thanks for the information > I will checkout that app note > Peter could you repost your feedback trick? > Martin > Here it comes, an awkward verbal description: For the conventional 3-state output, you connect (internally to the I/O) the data signal not only to the data input of the output driver, but also to its 3-state control, so that a High data will automatically disable the output. Everybody knows this. Poor RC rise time. Now the trick: use the same device pin also as an input, connect the output of this IBUF together with the internal data signal to a 2-input AND gate ( located in a CLB) and let the output of this AND drive the 3-state control pin. Result: when the internal data goes High, it drives the output active High, until the level is High enough to be recognized by the IGUF as High ( about 1.4 V), which then activates the AND gate and disables the output. From then on, it's up to the pull-up to pull all the way to 5 V. Any delay in the AND gate works in your favor, since it lengthens the time that the active driver keeps pulling High and thus makes it pull higher, at best all the way to 3.3 V. Effectively, this uses the 20 Ohm active pull-up, instead of the 470 Ohm resistor, so the rise time is about 25 times better, down to 1 ns ! If the pin is really used in a bi-directional way, you need a third input to the gate ( an OR after the AND, but that's what LUTs are good at ) to force the output into 3-state. That's all. You already have the IBUF ro receive the data. The 470 Ohm resistor may be a bit strong, so go to a kilohm or two. Peter Alfke, Xilinx Applications ( answering from home)Article: 22971
Simmler Harald wrote: > Hi > > generating a CORE with a pre-placement can be done by adding some placement > attributes to the primitives. But how can someone put also some pre-routing to > the CORE to ensure that some timing constrains are retained? The router does a pretty good job if the placement it starts with is good. In the vast majority of cases, a placement plus timing constraints will be sufficient. If you want , you can embed timing constraints in your code too, but I think it is easier to just put them in a ucf file. > > Additionally how can a component be locked to a specified block that is normally Use LOC constraints. > > > not used by the design. We have one case where we want to use a IBUF and a OBUF > Element and simply connect them together. We don't want to waste a IOB with PAD > for doing that. Therefore we want to lock the buffers to a IOB that has not PAD > attached. The destination architecture is Vitrex V400-BG560. > It works fine in the FPGA Editor but we found no way to do that with normal > constrains. > > Thanks for your help. > > Harald > > Ray Andraka wrote: > > > Unless you intend to package and sell the CORE, there is really no need to > > put it under coregen. Coregen is not much more than a pretty wrapper for > > edif netlist files. Instead, just instantiate your code as a component in a > > hierarchical VHDL design. If you are trying to do placement as well, I've > > found the best way to do it hierarchically is to put placement attributes > > right into the VHDL, which means you build the components from the > > structural level (I think this is probably why you want to create a > > component under the COREGEN). Alternatively, you can instantiate your core > > as a blackbox in VHDL under which you have an edif netlist (that is all > > coregen does with it). Look under the design guides for mixed schematic/HDL > > design methodology for details on instantiating black boxes in your design. > > > > > > -- > > -Ray Andraka, P.E. > > President, the Andraka Consulting Group, Inc. > > 401/884-7930 Fax 401/884-7950 > > email ray@andraka.com > > http://www.andraka.com or http://www.fpga-guru.com > > --------------------------------------------------------------------------- > Harald Simmler Lehrstuhl fuer Informatik V > Universitaet Mannheim > eMail: simmler@ti.uni-mannheim.de Germany -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com or http://www.fpga-guru.comArticle: 22972
Dalip K. Singh wrote in message <393C0819.DDDED147@hns.com>...
>I have used Quickswitch for 3.3/5V xlation and it works great.
>P/n: QS34X2245. I had to interface altera max7032aelc 3.3v part to 5v
>ttl logic.
>
>-Dalip.
>[Image]
Please don't post data sheets here. It's annoying. Post a link to a web
site instead.
--
-----------------------------------------
Andy Peters
Sr Electrical Engineer
National Optical Astronomy Observatories
950 N Cherry Ave
Tucson, AZ 85719
apeters (at) noao \dot\ edu
"A sufficiently advanced technology is indistinguishable from magic"
--Arthur C. Clarke
Article: 22973Peter Alfke wrote: > > myself wrote: > > > Thanks for the information > > I will checkout that app note > > Peter could you repost your feedback trick? > > Martin > > > > Here it comes, an awkward verbal description: > > For the conventional 3-state output, you connect (internally to the I/O) the > data signal not only to the data input of the output driver, but also to its > 3-state control, so that a High data will automatically disable the output. > Everybody knows this. Poor RC rise time. > > Now the trick: use the same device pin also as an input, connect the output > of this IBUF together with the internal data signal to a 2-input AND gate ( > located in a CLB) and let the output of this AND drive the 3-state control > pin. > Result: when the internal data goes High, it drives the output active High, > until the level is High enough to be recognized by the IGUF as High ( about > 1.4 V), which then activates the AND gate and disables the output. From then > on, it's up to the pull-up to pull all the way to 5 V. Q: What about the reverse PFET CMOS diode - does this not clamp to Vccio+0.6v ? > Any delay in the AND gate works in your favor, since it lengthens the time > that the active driver keeps pulling High and thus makes it pull higher, at > best all the way to 3.3 V. For a good example of this structure, see any 80c51 datasheet. They use a CLOCK delay in the AND path. Besides being good for level shift, this port structure is also good for Keypad scan, where it is possible for multiple IO to be shorted. -jg -- ======= 80x51 Tools & IP Specialists ========= = http://www.DesignTools.co.nzArticle: 22974
Hi, Even tho' I'm not looking for any free tool/hw/sw etc I was still wondering why should a CD be made which for sure will mean a certain cost. If the intension was to make those kind of thing free the way I would think should be used is simple putting all the "staff" on the web maybe on several server and than it will really be free. just a though have a nice day Illan In article <393CE0D2.651C3992@opencores.org>, khatib@ieee.org wrote: > Hi, > Are you looking for free tools? > Do you want free open hw designs? > > You can find the most known Free tools and open hw designs on a single > cdrom > > For more information visit the OpenTech cdrom page at > http://www.opencores.org/OIPC/projects/cdrom.shtml > > Jamil Khatib > > Sent via Deja.com http://www.deja.com/ Before you buy.
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