Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Just leaves the plain-text pin lists to be dealt with... Peter Alfke wrote in message <395EE570.BFCB052C@earthlink.net>... >Two weeks ago, some of you posted strong opinions about the >user-unfriendliness of our Applinx CD-ROM. >These were your main objections: > >1. "I don't want to see the Hollywood opening" >2. "I refuse to add anything to my pc-installation. Windoze is fragile >enough. I just want to read the data sheets and app notes." >3."Spartan files should not be locked. I want to cut and paste" >4."The CD-ROM should not expire" >5."I hate marketing" > >We took a serious look at these complaints and came up with the >following solutions: > >1. As I posted already: Just hit ESCAPE > >2. As I posted already: Open the CD with Explorer. >Then you can either double-click on the databook.htm file, and open it >with Explorer, >or you double-click on the databook.pdf files and open them with >Acrobat. > >3. Never again will we copy-protect a data sheet or app note. Spartan >info on the web is now unprotected, thanks to your comments. > >4. The CD-ROM does not "expire". Bad choice of word on our part. You can >use any Applinx CD-ROM until your Pentium turns to dust. After six >months we just remind you that you might be better off getting a new >CD-ROM. Ignore that, if you really feel like it. The same goes for our >software. You will then be without updates and support, but nothing will >evaporate or die or explode. > >5. Marketing is a necessary function. You may dislike the style ( as I >do I sometimes), but without marketing, there would be no new products. >Somebody has to coordinate the introduction, promotion, pricing, >production, sales etc. Learn to accept marketing, life without them >would be worse. > >Greetings, and keep designing with Virtex and Spartan. Neat parts! > >Peter Alfke, Xilinx Applications > > > >Article: 23601
Burch Electronic Designs FPGA Prototyping kits are now 25% cheaper. Xilinx kits are now US$66 ! The price rollback is due to the abolition of the crippling "Wholesale Sales Tax" in Australia, plus the recent streamlining of our production process. Xilinx, Altera, Atmel, Lucent and Actel kits are available. For product details, secure online shop and subscription to our free online newsletter please go to www.BurchED.com.au International orders are very welcome. Best regards Tony Burch www.BurchED.com.auArticle: 23602
hey all i am just wondering why you are all worrying about that since all the informations are available on xilinx web site. why is the need for data book + cd room+...they are all online ? ---Erika Sent via Deja.com http://www.deja.com/ Before you buy.Article: 23603
Having written software for many years, I'm about to start my first chip design. It consists of a cpu core, cache controller, dram controller and video generator. Here's how I plan to go about prototyping and testing it (with a view to eventual asic conversion). If anyone can tell me if I'm going about things the wrong way, please let me know. I've chosen the Altera route (because the MaxPlus baseline software is available on free evaluation). I've found to my dismay that the altera parts (or fpgas in general?) won't run a cpu core very fast because of slow propogation through a full adder. A 32-bit add takes about 29ns on a ACE1K (in simulation). This places a fundamental speed restriction on how fast the core can run (unless I'm missing something : can the adders be speeded up). This is no problem in itself, I can simply prototype the whole thing at a lower clock speed. Once tested and verified, preparing for asic should be a matter of adjusting some timing constants (such as number of wait cycles on the dram interface). Is this route, simulation of fpga followed implementation in fpga, the correct way to go about things. Any advice would be greatly appreciated. Steve Logue.Article: 23604
Hello, I am looking for 16 bit integer division. (I need to calculate averages) I just hope for a tip on technique. I do not need high speed. I use Xilinx. Sincerely Dan DeConinckArticle: 23605
We have an FPGA design that will be targeting an Actel 1200 series FPGA (antifuse, one-time-programmable). It will be coded in Verilog, simulated w/ Model Tech's ModelSim PE simulator (PC Win 95/NT), synthesized in Synopsys FPGA Compiler II (Unix), and P&R done w/ Actel's backend tools (Unix). The systems people are making serious noise about requiring this design to have Built-In Self-Test (yes, we know about the gate & speed penalty we pay for this, and that it may be bigger for FPGAs than it is for ASICs because of the granularity difference), meaning: (1) the mission-logic registers must be turned into scan-able registers (2:1 mux in front of D-input) and assembled into N chains, where N is typically 2 <= N <= 64. plus the following (w/ non-scan-able registers) would need to be stitched into the design: (2.1) LFSR-based pattern generator (2.2) LFSR-based signature analyzer / response compressor (2.3) control logic (wired back w/ hooks to the "CPU bus" or whatever other communications port reports BIST pass/fail status) to do M scan sequences. Has anyone done these things for an FPGA? If so, what tools? I know that the EDA industry has tools that routinely do step (1) for ASICs, but does anyone do this for FPGAs? Can any EDA tool take an EDIF netlist produced by an FPGA synthesis tool, insert scan registers & wire chains [adding ports for the scan in(s), scan out(s), scan enable control(s)], and have the new modified netlist accepted by the FPGA P&R tools? Can any EDA tool automate steps (2.1-2.3), at all, let alone for FPGAs? We are interested in finding out how much, if any, of these tasks are automatically done by EDA tools for FPGAs. Naturally we can build all this testability explicitly into the HDL source code if we have to, but we want to avoid that. Even if we can only do step (1) but not steps (2.1-2.3), we may still be able to do some scan-based test, perhaps with an external microcontroller performing steps (2.1-2.3). -- ============================== William Lenihan lenihan3weNO@SPAMearthlink.net ==============================Article: 23606
Looks to me like a strong argument for SRAM-based FPGAs, where such issues can be resolved by re-configuration, and the user-design need not be burdened with BIST, because everything can be pre-tested in a separate configuration. Please no flames... Peter Alfke, Xilinx Applications =============================== Bill Lenihan wrote: > We have an FPGA design that will be targeting an Actel 1200 series FPGA > (antifuse, one-time-programmable). It will be coded in Verilog, > simulated w/ Model Tech's ModelSim PE simulator (PC Win 95/NT), > synthesized in Synopsys FPGA Compiler II (Unix), and P&R done w/ Actel's > backend tools (Unix). > > The systems people are making serious noise about requiring this design > to have Built-In Self-Test (yes, we know about the gate & speed penalty > we pay for this, and that it may be bigger for FPGAs than it is for > ASICs because of the granularity difference), meaning: > > (1) the mission-logic registers must be turned into scan-able registers > (2:1 mux in front of D-input) and assembled into N chains, where N is > typically 2 <= N <= 64. > > plus the following (w/ non-scan-able registers) would need to be > stitched into the design: > > (2.1) LFSR-based pattern generator > (2.2) LFSR-based signature analyzer / response compressor > (2.3) control logic (wired back w/ hooks to the "CPU bus" or whatever > other communications port reports BIST pass/fail status) to do M scan > sequences. > > Has anyone done these things for an FPGA? If so, what tools? > > I know that the EDA industry has tools that routinely do step (1) for > ASICs, but does anyone do this for FPGAs? Can any EDA tool take an EDIF > netlist produced by an FPGA synthesis tool, insert scan registers & wire > chains [adding ports for the scan in(s), scan out(s), scan enable > control(s)], and have the new modified netlist accepted by the FPGA P&R > tools? > > Can any EDA tool automate steps (2.1-2.3), at all, let alone for FPGAs? > > We are interested in finding out how much, if any, of these tasks are > automatically done by EDA tools for FPGAs. Naturally we can build all > this testability explicitly into the HDL source code if we have to, but > we want to avoid that. > > Even if we can only do step (1) but not steps (2.1-2.3), we may still be > able to do some scan-based test, perhaps with an external > microcontroller performing steps (2.1-2.3). > > -- > ============================== > William Lenihan > lenihan3weNO@SPAMearthlink.net > ==============================Article: 23607
Peter Alfke wrote: > Looks to me like a strong argument for SRAM-based FPGAs, where such issues > can be resolved by re-configuration, and the user-design need not be > burdened with BIST, because everything can be pre-tested in a separate > configuration. To expand just a bit, there would be a load controller that would load a test design into the FPGA on powerup or whenever selftest was required, and once selftest completed the load controller would load in the real design. This is a good board bring up strategy as well: the FPGA is loaded with a design that just checks some simple stuff and/or flashes an LED. The idea is to quickly verify that the FPGA has a clock, has power and can be loaded. > Please no flames... Not a flame, but there are reasons why antifuse parts have a market. -- Phil Hays Clues for sale or rent. Hints for just 50 cents.Article: 23608
On Sun, 02 Jul 2000 06:47:32 GMT, Peter Alfke <palfke@earthlink.net> wrote: >Two weeks ago, some of you posted strong opinions about the >user-unfriendliness of our Applinx CD-ROM. >These were your main objections: > >1. "I don't want to see the Hollywood opening" >2. "I refuse to add anything to my pc-installation. Windoze is fragile >enough. I just want to read the data sheets and app notes." >3."Spartan files should not be locked. I want to cut and paste" >4."The CD-ROM should not expire" >5."I hate marketing" > >We took a serious look at these complaints and came up with the >following solutions: > >1. As I posted already: Just hit ESCAPE > >2. As I posted already: Open the CD with Explorer. >Then you can either double-click on the databook.htm file, and open it >with Explorer, >or you double-click on the databook.pdf files and open them with >Acrobat. > >3. Never again will we copy-protect a data sheet or app note. Spartan >info on the web is now unprotected, thanks to your comments. > >4. The CD-ROM does not "expire". Bad choice of word on our part. You can >use any Applinx CD-ROM until your Pentium turns to dust. After six >months we just remind you that you might be better off getting a new >CD-ROM. Ignore that, if you really feel like it. The same goes for our >software. You will then be without updates and support, but nothing will >evaporate or die or explode. > >5. Marketing is a necessary function. You may dislike the style ( as I >do I sometimes), but without marketing, there would be no new products. >Somebody has to coordinate the introduction, promotion, pricing, >production, sales etc. Learn to accept marketing, life without them >would be worse. > >Greetings, and keep designing with Virtex and Spartan. Neat parts! > >Peter Alfke, Xilinx Applications > > > Peter, even though we hurl abuse at you now and then, we know that you are an engineer, and we know that you are on our side. Thanks, JohnArticle: 23609
On Sun, 02 Jul 2000 12:59:59 GMT, erika_uk@my-deja.com wrote: >hey all > >i am just wondering why you are all worrying about that since all the >informations are available on xilinx web site. > >why is the need for data book + cd room+...they are all online ? > > >---Erika > > >Sent via Deja.com http://www.deja.com/ >Before you buy. Erika, the online stuff is indeed easy to use, and absolutely up to date. My personal concern is having all design tools, datasheets and appnotes still available five or more years from now when I may have to upgrade a product. I just had to do exactly that to an old Actel design (had to add one nor gate to implement a new function) and it was a pretty fair nightmare. The dongle wouldn't work on modern parallel ports, the software install on Win95 was a mess, and on and on. Ultimately, an applications engineer from Pioneer did it for us, but he had to cheat bigtime, and the fix, though it works, is a kluge. *IF* any of the data or tools were to expire (apparently the Xilinx's do not, thank goodness) and the data (or worse, web-enabled tools!) was no longer available online, I'd be up FPGA creek. JohnArticle: 23610
mmmm, I though that this was where the idea came from. "the latest version of the Virtex libraries are supposed to be able to simulate ROMs with init=xxxx attributes attached", as Philip indicated. Or am I missing something. Does the simulation work on something other than the EDIF file? Simon wrote: > > You could add the equation as an attribute, then write a small > program to scan the EDIF and convert the equation to an INIT. > This would still leave the simulation to be dealt with... > > Rickman wrote in message <395ED46E.D072C66A@yahoo.com>... > > > >Now if I can just get them to let me enter a single equation for the LUT > >instead of having to calculate the hex contents myself. -- Rick Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 23611
I am not a test expert, but I don't think it is very common to build in scan test for the internal parts of a chip design. The internal parts of a chip are so reliable, that it is very, very seldom that they ever stop working once built correctly. With that said there are two reasons that you (I will speek for myself as "you") might want to do scan based test. One is that you want to test that the part is connected correctly and there is no damage to the IOs which is much more common than internal problems. The other is that you may have a design that is hard to do factory test by observing the IO pins. Sometimes it takes a very long test to be sure that you have toggled every node in the chip and observed all possible outcomes. It is also possible that there is NO test (without scan based testing) that can tell you if a given node has an error. (Makes you wonder if the error matters!) So if you are doing scan test for the second reason, then go for it. But if you don't have problems generating test vectors to adequately test your chip, then scan based test of internals is likely overkill. But if you are designing for space or some military applications, then the initial assumption is incorrect and you may have to detect internal failures in the field. I don't have any info on how to implement scan test, but I just thought I would point out that this is rarely needed for internal logic. Bill Lenihan wrote: > > We have an FPGA design that will be targeting an Actel 1200 series FPGA > (antifuse, one-time-programmable). It will be coded in Verilog, > simulated w/ Model Tech's ModelSim PE simulator (PC Win 95/NT), > synthesized in Synopsys FPGA Compiler II (Unix), and P&R done w/ Actel's > backend tools (Unix). > > The systems people are making serious noise about requiring this design > to have Built-In Self-Test (yes, we know about the gate & speed penalty > we pay for this, and that it may be bigger for FPGAs than it is for > ASICs because of the granularity difference), meaning: > > (1) the mission-logic registers must be turned into scan-able registers > (2:1 mux in front of D-input) and assembled into N chains, where N is > typically 2 <= N <= 64. > > plus the following (w/ non-scan-able registers) would need to be > stitched into the design: > > (2.1) LFSR-based pattern generator > (2.2) LFSR-based signature analyzer / response compressor > (2.3) control logic (wired back w/ hooks to the "CPU bus" or whatever > other communications port reports BIST pass/fail status) to do M scan > sequences. > > Has anyone done these things for an FPGA? If so, what tools? > > I know that the EDA industry has tools that routinely do step (1) for > ASICs, but does anyone do this for FPGAs? Can any EDA tool take an EDIF > netlist produced by an FPGA synthesis tool, insert scan registers & wire > chains [adding ports for the scan in(s), scan out(s), scan enable > control(s)], and have the new modified netlist accepted by the FPGA P&R > tools? > > Can any EDA tool automate steps (2.1-2.3), at all, let alone for FPGAs? > > We are interested in finding out how much, if any, of these tasks are > automatically done by EDA tools for FPGAs. Naturally we can build all > this testability explicitly into the HDL source code if we have to, but > we want to avoid that. > > Even if we can only do step (1) but not steps (2.1-2.3), we may still be > able to do some scan-based test, perhaps with an external > microcontroller performing steps (2.1-2.3). > > -- > ============================== > William Lenihan > lenihan3weNO@SPAMearthlink.net > ============================== -- Rick Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 23612
Hello, How can I search this newsgroup archive? (or just peruse older subject lines) Currently the oldest message is just 18 days old. My newsgroup reader is MS outlook express. Sincerely Dan DeConinckArticle: 23613
Hi Gary, I don't know the answer for the first question, but I'm pretty sure a MPEG algorithm implementation is not for free. What do you think about a ready MPEGI Layer II,III (known as mp2,mp3) Chip for about $50? BYE LarsArticle: 23614
http://www.deja.com/home_ps.shtml Dan wrote: > > Hello, > > How can I search this newsgroup archive? (or just peruse older subject > lines) > > Currently the oldest message is just 18 days old. > > My newsgroup reader is MS outlook express. > > Sincerely > Dan DeConinckArticle: 23615
Phil Hays wrote: > <snip> but there are reasons why antifuse parts have a market. Yes, instant-on, security, and better radiation tolerance. But at what a price! PeterArticle: 23616
Thanks, John. As I have said, I walk a fine line between engineering honesty and loyalty to my employer. But that's a fun challenge. I have been with Xilinx for over 12 years, have a certain respect there, and I am also a protected species: >65 years old. I'll be on vacation most of July, meeting old friends and sipping wine in small towns and villages in the south of France. Tough job, but somebody has to do it! :-) Greetings Peter >Article: 23617
> the online stuff is indeed easy to use, and absolutely up to date. My > personal concern is having all design tools, datasheets and appnotes > still available five or more years from now when I may have to upgrade > a product. I suggest making a copy of any online documentation you consider important. Or print it out and file the paper next to your other paperwork. Perhaps a CD would be appropriate. I'm not sure how to solve the software problem. You might consider retiring the whole machine - disconnect it from the net and put it in a safe place. Perhaps just saving the disk would be good enough. This is a tough problem. Even if your dongle still works, you have to make sure the software still works after you upgrade the OS or various utilities. Did a virus checker break something? Did your setup depend upon some obscure patch? -- These are my opinions, not necessarily my employers. I hate spam.Article: 23618
On Fri, 30 Jun 2000 23:55:41 -0400 Rickman <spamgoeshere4@yahoo.com> wrote: >BTW, I have never heard of IV3NWV YAM. I take it this is an acronym for >something? Yes, IV3NWV is the radioamateur callsign of Nico Palermo, author of the popular YAM 9k6/1k2bps packet radio modem with an XC5202 FPGA. Some links I've just ran across, just if you are curious. Yet Another 9k6 Modem by Nico Palermo IV3NWV. http://jupiter.web-hosting.com/~nicopal/yam/ Decoding (C)HRPT and HRI (PDUS) weather satellites by Rob Alblas. PCBs, schematics with FPGAs. http://www.alblas.demon.nl/wsat/index.html Game Boy FLASH cartridge programmer with Xilinx EPLD by Andrew March. http://www.icenet.com.au/~amarch/xcartio.htm 73's de Luis mail: melus0(@)teleline(.)es Ampr: eb7gwl.ampr.org http://www.terra.es/personal2/melus0/ <- PCBs for Homebrewed HardwareArticle: 23619
You can pipeline arithmetic functions to increase the clock speed of your core. There are many ways to do this.Article: 23620
Dan, www.deja.com has a good newsgroup search facility. --Phil. Dan wrote: > > Hello, > > How can I search this newsgroup archive? (or just peruse older subject > lines) > > Currently the oldest message is just 18 days old. > > My newsgroup reader is MS outlook express. > > Sincerely > Dan DeConinckArticle: 23621
hi, has anyone a vhdl source for a 3 1/2 digit lcd controller ? thanx Sent via Deja.com http://www.deja.com/ Before you buy.Article: 23622
> From some experiments with a controllable power supply, I came to have a > mere conjecture that the 2.5V power supply from a linear regulator(LT1076) > is not really tracking fast enough to meet the changes in Virtex' current > consumption. When the 2.5V power is supplied from power supply, the card > kept working over night. Are you completely sure your card fails because of power supply problems ? You could propably check this with a dummy design for your virtex with a lot of noise (toggle-flip-flops etc.) In "massive test operation" a lot of systems fail after a undefinable time (minutes to days). Ours did, too. But at last it was an interrupt handling problem which was caused by an extremely rare combination of things happening at the same time. Your problem may be of this nature, too. TobiasArticle: 23623
Hi Dan Take two binary numbers. Divide one by the other using pencil and paper. Turn what you just did into logic. Last time I did it there was a compare, a subtract and a shift. How long you keep going round the loop depends on how much accuracy you need. Of course there may be better ways! Kate Dan <daniel.deconinck@sympatico.ca> wrote in message news:2xI75.21849$W35.537179@news20.bellglobal.com... > Hello, > > I am looking for 16 bit integer division. (I need to calculate averages) > > I just hope for a tip on technique. I do not need high speed. > > I use Xilinx. > > Sincerely > Dan DeConinck > > >Article: 23624
Technology Hi, I have looked at the application note XAPP132 of Xilinx and there is DLL de-skew of board clock with the clock output feedback which has the same speed as the board clock. This application is shown on pages 10 and 11. Due to some board restrictions, I want to use divided clock feedback instead of clock feedback for de-skewing. Divided clock has half the frequency board clock has. I can not use f/2 instead of f frequency for board clock. If it had been, then the application would have been in page 10 and 11. But I have no right to change the board clock frequency. The de-skew Virtex-E must drive many Virtex-E and some peripherals with divided clock, so I thought divided clock can be de-skewed with a technique similar to in pp 10-11. I cannot figure out any solution, maybe you have one? Thank you in advance. Utku -- I feel better than James Brown.
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z