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Forgot to say: the de-skew device is a Virtex-E XCV1000E. UtkuArticle: 23626
The rivalry between Xilinx and Altera reminds me of the rivalry in the
early days between Intel and AMD. I think that Xilinx should look at adding
some dedicated logic to its FPGA's -- I for one would love to use an FPGA
with an onboard microprocessor.
<<START QUOTE>>
SAN JOSE, Calif.--(BUSINESS WIRE)--June 30, 2000 via NewsEdge Corporation -
Altera Corporation (Nasdaq:ALTR) today announced shipment of the
programmable logic industry's largest device, establishing integration
density leadership for system designers, and a 35 percent density advantage
over the nearest industry competitor. The new 1.5-million gate (2.5-million
system gates) APEX(TM) EP20K1500E allows implementation of complete
system-on-a-programmable-chip (SOPC) solutions, and expands Altera's
offering of high-density 1.8-volt CMOS programmable logic devices (PLDs)
built using a 0.18-micron, eight-layer-metal process. The EP20K1500E device
is ideal for leading-edge communications applications such as Layer 3
Routers and Switches, Wideband CDMA, Baseband Signal Processing, ATM Cell
Processing, Traffic Management, Terabit Routers, Switch Fabrics, and
Enterprise Storage Network Equipment.
Altera's APEX EP20K1500E device contains 51,840 logic elements (LEs), the
basic building block of programmable logic commonly used to judge device
density. Together, Altera's new EP20K1500E and the 1-million gate
(1.8-million system gates) EP20K1000E devices make the industry's two
largest PLDs available for development today.
<<END QUOTE>>
-EKC
Article: 23627I know what you mean, but this would make the complexity of inventory very much harder. This is especially a big problem for micros, you need to vary not only the RAM/ROM and all the usual things that micros tailor, but you also need to vary the size of the FPGA and the package pins (much more so than on a micro). They would have to do a sparse matrix implementation of that N dimensional array. I do that Lucent is selling FPGAs not much different from Xilinx parts that have an on board PCI bus interface. I don't know how well it is selling though. Lucent seems to be very tight on information on new products and sales. I also believe there is a startup company selling micros with FPGAs in them. I think the company name is Triscend, http://www.Triscend.com/. EKC wrote: > > The rivalry between Xilinx and Altera reminds me of the rivalry in the > early days between Intel and AMD. I think that Xilinx should look at adding > some dedicated logic to its FPGA's -- I for one would love to use an FPGA > with an onboard microprocessor. > > <<START QUOTE>> > > SAN JOSE, Calif.--(BUSINESS WIRE)--June 30, 2000 via NewsEdge Corporation - > > Altera Corporation (Nasdaq:ALTR) today announced shipment of the > programmable logic industry's largest device, establishing integration > density leadership for system designers, and a 35 percent density advantage > over the nearest industry competitor. The new 1.5-million gate (2.5-million > system gates) APEX(TM) EP20K1500E allows implementation of complete > system-on-a-programmable-chip (SOPC) solutions, and expands Altera's > offering of high-density 1.8-volt CMOS programmable logic devices (PLDs) > built using a 0.18-micron, eight-layer-metal process. The EP20K1500E device > is ideal for leading-edge communications applications such as Layer 3 > Routers and Switches, Wideband CDMA, Baseband Signal Processing, ATM Cell > Processing, Traffic Management, Terabit Routers, Switch Fabrics, and > Enterprise Storage Network Equipment. > > Altera's APEX EP20K1500E device contains 51,840 logic elements (LEs), the > basic building block of programmable logic commonly used to judge device > density. Together, Altera's new EP20K1500E and the 1-million gate > (1.8-million system gates) EP20K1000E devices make the industry's two > largest PLDs available for development today. > > <<END QUOTE>> > > -EKC -- Rick Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 23628
On Mon, 03 Jul 2000 19:51:54 GMT, "EKC" <NOSPAMalpha3.1@ix.netcom.com> wrote: > The rivalry between Xilinx and Altera reminds me of the rivalry in the >early days between Intel and AMD. I think that Xilinx should look at adding >some dedicated logic to its FPGA's -- I for one would love to use an FPGA >with an onboard microprocessor. > ><<START QUOTE>> > >SAN JOSE, Calif.--(BUSINESS WIRE)--June 30, 2000 via NewsEdge Corporation - > >Altera Corporation (Nasdaq:ALTR) today announced shipment of the >programmable logic industry's largest device, establishing integration >density leadership for system designers, and a 35 percent density advantage >over the nearest industry competitor. The new 1.5-million gate (2.5-million >system gates) APEX(TM) EP20K1500E allows implementation of complete >system-on-a-programmable-chip (SOPC) solutions, and expands Altera's >offering of high-density 1.8-volt CMOS programmable logic devices (PLDs) >built using a 0.18-micron, eight-layer-metal process. The EP20K1500E device >is ideal for leading-edge communications applications such as Layer 3 >Routers and Switches, Wideband CDMA, Baseband Signal Processing, ATM Cell >Processing, Traffic Management, Terabit Routers, Switch Fabrics, and >Enterprise Storage Network Equipment. > >Altera's APEX EP20K1500E device contains 51,840 logic elements (LEs), the >basic building block of programmable logic commonly used to judge device >density. Together, Altera's new EP20K1500E and the 1-million gate >(1.8-million system gates) EP20K1000E devices make the industry's two >largest PLDs available for development today. > ><<END QUOTE>> > >-EKC > Hmmm... my trusty Xilinx 2000 databook shows the XCV3200E as having 73,008 logic cells, claimed equivalent to a tad over 4M 'system gates'. Are LEs and LCs comparable gadgets? Well, it's a mess of logic either way. JohnArticle: 23629
"EKC" <NOSPAMalpha3.1@ix.netcom.com> writes: > The rivalry between Xilinx and Altera reminds me of the rivalry in the > early days between Intel and AMD. I think that Xilinx should look at adding > some dedicated logic to its FPGA's -- I for one would love to use an FPGA > with an onboard microprocessor. Atmel has some chips which are FPGA plus an AVR running at 30MHz. Zoltan -- +------------------------------------------------------------------+ | ** To reach me write to zoltan in the domain of bendor com au ** | +--------------------------------+---------------------------------+ | Zoltan Kocsi | I don't believe in miracles | | Bendor Research Pty. Ltd. | but I rely on them. | +--------------------------------+---------------------------------+Article: 23630
In article <395714B0.F9A192B6@opencores.org>, Jamil Khatib <khatib@opencores.org> wrote: >Hi, >Could you please mention some good universites in Canada "English >speekers area" to continue my graduate studies in the Reconfigurable >Computing and its EDA feilds. > >Please email me at khatib@opencores.org > >Thanks in advance >Jamil Khatib > University of Toronto is the default high-profile Canadian university, and they do have cool stuff going on in EDA and reconfigurable computing. UBC has great EDA research (including reconfigurable computing), too, plus we have better weather, better skiing, better hiking, ... :-) --Alan HuArticle: 23631
Hi, Sorry if this has been covered before....I did a search but didn't come up with much other than an old article in Circuit Cellar. I'd like to interface a small graphic lcd panel (upto 240x128 - mainly 128x64) to a Xilinx FPGA. The design simply needs to display a bitmap stored in SRAM and allow simultaneous access to the SRAM from the CPU. Any pointers would be appreciated. Regards, PJEArticle: 23632
Hello from the Master Jedi Levine Given the fact that there is an explosion of such garbage on this newsgroup, I am entitled to agree. That without any fourletter words. Especially since those <expletive deleted!> binaries were attached to messages that were pure spam! Gregg C Levine yodathejediknight(at)att(dot)net <This sig is for rent, contact Lando Calrissian> <Spammers beware! This address is protect by the Jedi Knights.> In article <TzleOTLlM2zemtQj724kcumU3y7L@4ax.com>, jjlarkin@highlandSNIPTHIStechnology.com says... > >On Sat, 01 Jul 2000 18:05:53 GMT, "~Mike Turco" <miketurco@yahoo.com> >wrote: > >>Fuck. Fuck fuck fuck fuck fuck. >> >>Hmmmm . . . seems a bit off topic. But its nice to get it out of my system. >>System? Hmmmm . . . maybe it is on topic. I can fix that. Fucking system. >>Fuck fuck fuck fuck fuck. >> >>(No binary attached.) >> > >Hey, Mike, great vocabulary. Where did you learn so many expressive >words? > >John >Article: 23633
I need to implement a pn generator. I have been through all of the Xilinx ap notes, and other materials that I can find, and I have been able to generate the verilog code to generate a shift register that almost does what I want. However, it, like all lsfr's, puts out 2^n-1 states before it repeats. I need to augment or stall that output so that I add a 0 to the end of every sequence, so as to create sequences with a length of 2^n. I see all sorts of mention of how easy that is to do, but I can't figure it out, and nowhere is it explained. Does anyone know how to do what I want to do? TIA, EdArticle: 23634
> almost does what I want. However, it, like all lsfr's, puts out 2^n-1 > states before it repeats. I need to augment or stall that output so > that I add a 0 to the end of every sequence, so as to create sequences > with a length of 2^n. I see all sorts of mention of how easy that is > to do, but I can't figure it out, and nowhere is it explained. Does > anyone know how to do what I want to do? What are you really trying to do? Note that the LFSR type circuits generate 1 bit at a time, not a sequence of n bit wide words. It's pretty hard to distinguish the output of an LFSR from the corresponding system that does include the all-0s state. (It's just a single 0 bit in the output sequence.) If you are worried about the missing 0 unbalancing your statistics, the simple fix is probably to use a bigger LFSR. If you want the all-zero word output, your first problem is to get a clean sequence of words. I think the output of an LFSR is good if you step it N cycles to get an N bit word. If you can't wait that long, you can use independent LFSRs for each bit. (You need to make sure they don't run in lock step, perhaps by making them different lengths.) Using the bottom N bits of an N+k bit LFSR clocked N bits between samples will give you (2^k)-1 all 0 words compared to (2^k) samples of all other values. If it helps, you can turn things upside down with an inverter in the right place and make the all 1s state the missing one. -- These are my opinions, not necessarily my employers. I hate spam.Article: 23635
If, for whatever strange reason, you want to lengthen the sequence by its one missing count, you have no alternative but to have a wide AND gate that detects the state where all but the rightmost bit are zeros, and then, during this 2-bit event, inverts (XORs) the feedback, so that it includes the all-zero state. (I prefer to exclude the all-ones state, since Xilinx FPGAs naturally reset to zero, but this may be irrelevant nowadays). So, the cost is a wide parallel gate, which you, of course, can emulate with a sequential state machine, if you prefer. But again: why all this? Peter Alfke ========================================================== Hal Murray wrote: > > almost does what I want. However, it, like all lsfr's, puts out 2^n-1 > > states before it repeats. I need to augment or stall that output so > > that I add a 0 to the end of every sequence, so as to create sequences > > with a length of 2^n. I see all sorts of mention of how easy that is > > to do, but I can't figure it out, and nowhere is it explained. Does > > anyone know how to do what I want to do? > > What are you really trying to do? > > Note that the LFSR type circuits generate 1 bit at a time, not > a sequence of n bit wide words. > > It's pretty hard to distinguish the output of an LFSR from > the corresponding system that does include the all-0s state. > (It's just a single 0 bit in the output sequence.) > > If you are worried about the missing 0 unbalancing your > statistics, the simple fix is probably to use a bigger LFSR. > > If you want the all-zero word output, your first problem is > to get a clean sequence of words. I think the output of an > LFSR is good if you step it N cycles to get an N bit word. > If you can't wait that long, you can use independent LFSRs > for each bit. (You need to make sure they don't run in > lock step, perhaps by making them different lengths.) > > Using the bottom N bits of an N+k bit LFSR clocked N bits > between samples will give you (2^k)-1 all 0 words compared > to (2^k) samples of all other values. > > If it helps, you can turn things upside down with an inverter > in the right place and make the all 1s state the missing one. > -- > These are my opinions, not necessarily my employers. I hate spam.Article: 23636
If, for whatever strange reason, you want to lengthen the sequence by its one missing count, you have no alternative but to have a wide AND gate that detects the state where all but the rightmost bit are zeros, and then, during this 2-bit event, inverts (XORs) the feedback, so that it includes the all-zero state. (I prefer to exclude the all-ones state, since Xilinx FPGAs naturally reset to zero, but this may be irrelevant nowadays). So, the cost is a wide parallel gate, which you, of course, can emulate with a sequential state machine, if you prefer. But again: why all this? Peter Alfke ========================================================== Hal Murray wrote: > > almost does what I want. However, it, like all lsfr's, puts out 2^n-1 > > states before it repeats. I need to augment or stall that output so > > that I add a 0 to the end of every sequence, so as to create sequences > > with a length of 2^n. I see all sorts of mention of how easy that is > > to do, but I can't figure it out, and nowhere is it explained. Does > > anyone know how to do what I want to do? > > What are you really trying to do? > > Note that the LFSR type circuits generate 1 bit at a time, not > a sequence of n bit wide words. > > It's pretty hard to distinguish the output of an LFSR from > the corresponding system that does include the all-0s state. > (It's just a single 0 bit in the output sequence.) > > If you are worried about the missing 0 unbalancing your > statistics, the simple fix is probably to use a bigger LFSR. > > If you want the all-zero word output, your first problem is > to get a clean sequence of words. I think the output of an > LFSR is good if you step it N cycles to get an N bit word. > If you can't wait that long, you can use independent LFSRs > for each bit. (You need to make sure they don't run in > lock step, perhaps by making them different lengths.) > > Using the bottom N bits of an N+k bit LFSR clocked N bits > between samples will give you (2^k)-1 all 0 words compared > to (2^k) samples of all other values. > > If it helps, you can turn things upside down with an inverter > in the right place and make the all 1s state the missing one. > -- > These are my opinions, not necessarily my employers. I hate spam.Article: 23637
Good day, folks. I'm trying to think up a not-too-difficult way of adding a serial number to the Serial PROM used to program a Xilinx Spartan FPGA. The intent would be to use this as the Card Serial number, and once the FPGA was initialized, it would then go and read the PROM itself. I've thought of haveing the serila number the last 48 bits, or something like that. If I'm not mistaken, the serial stream for programming the FPGA, including the CRC and everything else, is finished before the actual end of the PROM. Can anybody confirm that this is doable, or does anybody have a better way to do it? Thanks. -Kent Sent via Deja.com http://www.deja.com/ Before you buy.Article: 23638
One way to make an 2^n-cycle lfsr is to use an n+1 bit lfsr and arrange it
to cycle with a length of 2^n by complementing the shift-in at the right
time (counter pattern) so as to generate a 2^n count cycle.
My lfsr design program finds such things, as well as bit patterns of
arbitrary counter taps in arbitrary m-cycle n-bit lfsrs.
To design an m-cycle lfsr in an n-bit lfsr, n > 2 and 1 < m < 2^n - 1, build
a table w[] of lfsr counter bit patters. w[0] is the initial bit pattern
0000...0. w[i+1] is w[i] after shifting in (at the lsb) the next 0 or 1
(the xor-of-taps input) and shifting out (discarding) w[i]'s msb.
If after some number of cycles i, w[i] ^ w[i-m] == 0000...1, we can form an
m-cycle counter by complementing the xor-of-taps input when the counter is
at bit pattern w[i-1].
Conjecture: for m, n, and w[] as above, there always exists an i such that
w[i] ^ w[i-m] == 0000...1
For example, if you want an 8-cycle counter using a 4-bit LFSR, we have:
% lfsr -v 4 8
n w 8-back
- - ------
0 0
1 1
2 3
3 7
4 E
5 D
6 B
7 6
8 C 0
9 9 1
10 2 3 8-cycle [2-9]: complement d0 when w==9 maps 2=>3
lfsr 4-bits 8-cycle=9
lfsr 4-bits 8-cycle: d0=xnor(q3,q2, /*9*/and(q3,~q2,~q1,q0));
Here w[2]=3, w[9]=9, and w[10]=2. If we complement the lfsr input bit shift
into w[10], we would have w'[10]=3 and the lfsr would cycle
3,7,E,D,B,6,0,1,3,...
The lfsr design program (verbose mode) therefore reports that the logic
required is:
d0=xnor(q3,q2, /*9*/and(q3,~q2,~q1,q0));
Here are some more examples.
% lfsr 6 32
lfsr 6-bits 32-cycle=23
lfsr 6-bits 32-cycle: d0=xnor(q5,q4, /*23*/and(q5,~q4,~q3,~q2,q1,q0));
% lfsr 7 64
lfsr 7-bits 64-cycle=07
lfsr 7-bits 64-cycle: d0=xnor(q6,q5,
/*07*/and(~q6,~q5,~q4,~q3,q2,q1,q0));
% lfsr 8 128
lfsr 8-bits 128-cycle=43
lfsr 8-bits 128-cycle: d0=xnor(q7,q5,q4,q3,
/*43*/and(~q7,q6,~q5,~q4,~q3,~q2,q1,q0));
You can also build an 8-cycle counter in something larger than a 4-bit lfsr.
Here is one in a 6-bit lfsr:
% lfsr 6 8
lfsr 6-bits 8-cycle=0B
lfsr 6-bits 8-cycle: d0=xnor(q5,q4, /*0B*/and(~q5,~q4,q3,~q2,q1,q0));
I used this tool to design area-efficient horizontal and vertical
sync/blanking counters in the VGA controller in XSOC. (There's not too much
space left in a XC4005x after you've implemented a pipelined RISC processor
and the rest of the SoC -- every 4-LUT is precious.) For XSOC, with a 25
MHz dot clock, we need a 397-cycle horizontal counter with events at 288,
315, and 362cycles, and a 528-cycle vertical counter with events at 455,
486, and 488 cycles. To keep things simple, both are implemented with
10-bit lfsrs:
% lfsr 10 397 288 315 362
lfsr 10-bits 397-cycle=31D 288=1C4 315=122 362=3B6
lfsr 10-bits 397-cycle: d0=xnor(q9,q6,
/*31D*/and(q9,q8,~q7,~q6,~q5,q4,q3,q2,~q1,q0));
% lfsr 10 528 455 486 488
lfsr 10-bits 528-cycle=27D 455=01D 486=3F5 488=3D7
lfsr 10-bits 528-cycle: d0=xnor(q9,q6,
/*27D*/and(q9,~q8,~q7,q6,q5,q4,q3,q2,~q1,q0));
This is how I used this in the Verilog version of XSOC/xr16:
/* vga.v -- XSOC bilevel VGA controller synthesizable Verilog model
*
* Copyright (C) 1999, 2000, Gray Research LLC. All rights reserved.
* The contents of this file are subject to the XSOC License Agreement;
...
module vga(clk, rst, vack, pixels_in, vreq, vreset, hsync_n, vsync_n, r, g,
b);
...
// Horizontal and vertical sync and enable timings, 12.5 MHz
wire [9:0] hc, vc;
wire h0 = hc == 10'h31D;
wire v0 = vc == 10'h27D;
...
lfsr10 hctr(.clk(clk), .rst(rst), .ce(1'b1), .cycle(h0), .q(hc));
lfsr10 vctr(.clk(clk), .rst(rst), .ce(h0), .cycle(v0), .q(vc));
...
endmodule
// lfsr10 -- 10-bit linear feedback shift register counter
//
module lfsr10(clk, rst, ce, cycle, q);
input clk; // global clock
input rst; // global async reset
input ce; // counter clock enable
input cycle; // toggle LFSR input to force short cycle
output [9:0] q; // counter output
reg [9:0] q;
always @(posedge clk or posedge rst) begin
if (rst)
q <= 0;
else if (ce)
q <= { q[8:0], ~(q[9] ^ q[6] ^ cycle) };
end
endmodule
The 152-line lfsr.c, and its Win32 binary, are available as part of the XSOC
kit, available under the XSOC License Agreement, at www.fpgacpu.org/xsoc
Jan Gray
Gray Research LLC
Reference
"Efficient Shift Registers, LFSR Counters, and Long Pseudo-Random Sequence
Generators", Peter Alfke, Xilinx App Note, Aug. 1995
Article: 23639For simple applications, you can make sure you always have a number of samples that is devisible by two. A shift right is equivalent to a divide by 2. A divide by 4 is two shift rights etc. Good Luck, bkk In article <962637629.2771.0.nnrp-08.9e98b847@news.demon.co.uk>, "Kate Atkins" <kate.atkins@siraeo.noldckspam.co.uk> wrote: > Hi Dan > > Take two binary numbers. > Divide one by the other using pencil and paper. > Turn what you just did into logic. > > Last time I did it there was a compare, a subtract and a shift. How long you > keep going round the loop depends on how much accuracy you need. > > Of course there may be better ways! > > Kate > > Dan <daniel.deconinck@sympatico.ca> wrote in message > news:2xI75.21849$W35.537179@news20.bellglobal.com... > > Hello, > > > > I am looking for 16 bit integer division. (I need to calculate averages) > > > > I just hope for a tip on technique. I do not need high speed. > > > > I use Xilinx. > > > > Sincerely > > Dan DeConinck > > > > > > > > Sent via Deja.com http://www.deja.com/ Before you buy.Article: 23640
I installed Foundation 2.1i and all service packages ,but the placement and routing results are worse in comparision to 1.5 . I used the same table seed entry ,routing effort ,ucf files . The parts are XC5204 and XS20 . Did anybody get similar results?Article: 23641
EKC a crit : > > The rivalry between Xilinx and Altera reminds me of the rivalry in > the early days between Intel and AMD. I think that Xilinx should look > at adding some dedicated logic to its FPGA's -- I for one would love > to use an FPGA with an onboard microprocessor. From what I've heard, they plan to do it. We just couldn't know which uP they'll use (ARM? MIPS? Sparc? ...) -- Nicolas MATRINGE DotCom S.A. Conception electronique 16 rue du Moulin des Bruyeres Tel +33 1 46 67 51 11 92400 COURBEVOIE Fax +33 1 46 67 51 01 FRANCEArticle: 23642
Hello, I start working in VHDL and i purchase a free PCB programmer for FPGA or CPLD chip (Altera, xillinx, Cypress...) Thank you for you answer bertrand@olfac.univ-lyon1.frArticle: 23643
Hi, Another manufacturer of ęC and FPGA on one chip (call it FPGA with a CPU or ęC with a programmable part, as you like it) is Atmel. They have (at least announce for a quite long time) their so called FPSLIC AT94xx with an AVR core, 32k SRAM and 10..40K Gates of their AT40K FPGA. So, it is possible and it is possibly already done. Jens Rickman wrote: > > I know what you mean, but this would make the complexity of inventory > very much harder. This is especially a big problem for micros, you need > to vary not only the RAM/ROM and all the usual things that micros > tailor, but you also need to vary the size of the FPGA and the package > pins (much more so than on a micro). They would have to do a sparse > matrix implementation of that N dimensional array. > > I do that Lucent is selling FPGAs not much different from Xilinx parts > that have an on board PCI bus interface. I don't know how well it is > selling though. Lucent seems to be very tight on information on new > products and sales. > > I also believe there is a startup company selling micros with FPGAs in > them. I think the company name is Triscend, http://www.Triscend.com/. > > EKC wrote: > > > > The rivalry between Xilinx and Altera reminds me of the rivalry in the > > early days between Intel and AMD. I think that Xilinx should look at adding > > some dedicated logic to its FPGA's -- I for one would love to use an FPGA > > with an onboard microprocessor. > > > > <<START QUOTE>> > > > > SAN JOSE, Calif.--(BUSINESS WIRE)--June 30, 2000 via NewsEdge Corporation - > > > > Altera Corporation (Nasdaq:ALTR) today announced shipment of the > > programmable logic industry's largest device, establishing integration > > density leadership for system designers, and a 35 percent density advantage > > over the nearest industry competitor. The new 1.5-million gate (2.5-million > > system gates) APEX(TM) EP20K1500E allows implementation of complete > > system-on-a-programmable-chip (SOPC) solutions, and expands Altera's > > offering of high-density 1.8-volt CMOS programmable logic devices (PLDs) > > built using a 0.18-micron, eight-layer-metal process. The EP20K1500E device > > is ideal for leading-edge communications applications such as Layer 3 > > Routers and Switches, Wideband CDMA, Baseband Signal Processing, ATM Cell > > Processing, Traffic Management, Terabit Routers, Switch Fabrics, and > > Enterprise Storage Network Equipment. > > > > Altera's APEX EP20K1500E device contains 51,840 logic elements (LEs), the > > basic building block of programmable logic commonly used to judge device > > density. Together, Altera's new EP20K1500E and the 1-million gate > > (1.8-million system gates) EP20K1000E devices make the industry's two > > largest PLDs available for development today. > > > > <<END QUOTE>> > > > > -EKC > > -- > > Rick Collins > > rick.collins@XYarius.com > > Ignore the reply address. To email me use the above address with the XY > removed. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design > > Arius > 4 King Ave > Frederick, MD 21701-3110 > 301-682-7772 Voice > 301-682-7666 FAX > > Internet URL http://www.arius.comArticle: 23644
Hello Rick,
Rickman wrote:
> I am not a test expert, but I don't think it is very common to build in
> scan test for the internal parts of a chip design. The internal parts of
> a chip are so reliable, that it is very, very seldom that they ever stop
> working once built correctly.
It's true that scan-based testing is commonly found in ASICs and much less in
FPGAs. However, I just want to emphasize that reliability (not only in FPGAs
but in all VLSI chips) is unfortunately going down as time passes and thus, I
can't blame anyone that wants to add more testability to designs which
traditionally were not prone to failure.
As it is mentioned in a lot of specialized litterature or in various
test-oriented conferences (such as last year's ITC), reliability for older
processes (i.e. larger geometries) was well defined and could be made quite
high for many designs via process improvements. As we're going deeper in
submicron technology (0.18um, 0.15um and less), the VLSI folks are getting
problems in predicting failures since the fault model is changing; the net
result is that reliability is decreasing. If you assume that today's chips
(including FPGAs) will not be a problem because they never were in the past,
think again 'cause you may get a surprise...
And for Bill:
> Bill Lenihan wrote:
> >
> > The systems people are making serious noise about requiring this design
> > to have Built-In Self-Test
<snip snip>
> > Has anyone done these things for an FPGA? If so, what tools?
While I haven't used their tools, you might wanna check a company called
LogicVision (http://www.lvision.com). I know their software is geared to add
BIST to ASICs, but perhaps it can also be done with FPGAs.
Regards,
tienne.
--
______ ______
*****/ ____// _ \_\*************************************************
* / /_/_ / /_/ / / Etienne Racine, Hardware Designer *
* / ____// __ /_/ Visual Systems Engineering *
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Article: 23645In my Virtex design (written in VHDL) I have a reset signal (N_RST). This signal is active low and resets all the FFs of the design, excluding a few of them (which haven't a set/reset signal). My question is: can I use the Global Set Reset resource? The problems I see are two: - the GSR net is active high, but my N_RST signal is active low; - the GSR net reaches all the FFs: what happens to the FFs of my design that have not a S/R signal? Thanks, SteVeArticle: 23646
Bill Lenihan wrote: > We have an FPGA design that will be targeting an Actel 1200 series FPGA > (antifuse, one-time-programmable). It will be coded in Verilog, > simulated w/ Model Tech's ModelSim PE simulator (PC Win 95/NT), > synthesized in Synopsys FPGA Compiler II (Unix), and P&R done w/ Actel's > backend tools (Unix). > > The systems people are making serious noise about requiring this design to > have Built-In Self-Test (yes, we know about the gate & speed penalty we > pay for this, and that it may be bigger for FPGAs than it is for ASICs > because of the granularity difference), meaning: > > (1) the mission-logic registers must be turned into scan-able registers > (2:1 mux in front of D-input) and assembled into N chains, where N is > typically 2 <= N <= 64. > > plus the following (w/ non-scan-able registers) would need to be > stitched into the design: > > (2.1) LFSR-based pattern generator > (2.2) LFSR-based signature analyzer / response compressor > (2.3) control logic (wired back w/ hooks to the "CPU bus" or whatever > other communications port reports BIST pass/fail status) to do M scan > sequences. > > Has anyone done these things for an FPGA? If so, what tools? > > I know that the EDA industry has tools that routinely do step (1) for > ASICs, but does anyone do this for FPGAs? Can any EDA tool take an EDIF > netlist produced by an FPGA synthesis tool, insert scan registers & wire > chains [adding ports for the scan in(s), scan out(s), scan enable > control(s)], and have the new modified netlist accepted by the FPGA P&R > tools? > > Can any EDA tool automate steps (2.1-2.3), at all, let alone for FPGAs? > > We are interested in finding out how much, if any, of these tasks are > automatically done by EDA tools for FPGAs. Naturally we can build all > this testability explicitly into the HDL source code if we have to, but we > want to avoid that. > > Even if we can only do step (1) but not steps (2.1-2.3), we may still be > able to do some scan-based test, perhaps with an external > microcontroller performing steps (2.1-2.3). Perhaps you wish to growl back at your systems people. :-) If you're using an Actel 1200 series device, you don't get very much real estate to fool around with. Things like LFSR's are compact, fast, and can easily be done. However, you may wish to combine those techniques with elements of the system design to make the system testable; perhaps what you should tell your system engineers instead of having the systems engineers telling you to make your chip testable. Of course, things depend on the architecture of your system and if testability was designed into it. It's always good to separate requirements from implementation. Naturally, it depends on what they are trying to accomplish with their tests. Another thing to consider for an FPGA of that class is that you get, for free, 100% observability via the PRA and PRB pins (using MODE, SDI and DCLK for control) if your design hasn't used those pins in a way that would prevent you from using them. Often the observability can satisfy a particular set of requirements and an ASIC-like approach is not needed. Good luck! ---------------------------------------------------------------------- rk The world of space holds vast promise stellar engineering, ltd. for the service of man, and it is a stellare@erols.com.NOSPAM world we have only begun to explore. Hi-Rel Digital Systems Design -- James E. Webb, 1968Article: 23647
Peter Alfke wrote: > Phil Hays wrote: > > > <snip> but there are reasons why antifuse parts have a market. > > Yes, instant-on, security, and better radiation tolerance. But at what a price! > > Peter I would disagree that "instant-on" is inherent in antifuse-based FPGA designs. Peter, I think you have fell victim to your competitor's marketeers. :-) By the way, screw the environmentalists, asbestos, flame-proof suit is going on now! ---------------------------------------------------------------------- rk stellar engineering, ltd. Once again, we were lucky - but luck stellare@erols.com.NOSPAM has no business in spaceflight. Hi-Rel Digital Systems Design -- Gene KranzArticle: 23648
In article <395F75F2.1088FCE7@earthlink.net>, palfke@earthlink.net wrote: > Looks to me like a strong argument for SRAM-based FPGAs, where such issues > can be resolved by re-configuration, and the user-design need not be > burdened with BIST, because everything can be pre-tested in a separate > configuration. (snip) I'm not sure that this would be valid from a test perspective. How do you know if your test bitstream tests all of the logic and interconnect that is used for the mission bitstream? This is very P&R dependent. The purpose of BIST is to test the logic paths that are in use, and I'm not convinced that a separate test bitstream could be made to do this. Each bitstream will use different CLB inputs and outputs, CLB configurations, interconnect switches, etc. -- Greg Neff VP Engineering *Microsym* Computers Inc. greg@guesswhichwordgoeshere.com Sent via Deja.com http://www.deja.com/ Before you buy.Article: 23649
That would probably work fine, but how would you read it? AFAIK, some of the pins used for reading the PROM during configuration are not usable as IOs during normal operation (CCLK, DONE-). I guess you could attach extra pins to the signals which are not accessable by your FPGA design during configuration. I am looking at taking a different tact. I have been thinking about using a small (very small) micro to boot my board. I may have it do some other things like monitor power supply voltages and replace a board control register, but the main fuction is to boot the initial FPGA load. But once you have done this, you can implement many other functions in the micro, including the serial number you mentioned. In fact, this was the function that initially got me thinking about using a micro. My current board has a Dallas one wire part on it to provide a serial number and some non-volatile storage for board configuration data. Using a small micro costs no more, fits about the same foot print and adds fuctionality. Of course adding more functions changes the cost and size, but that is icing on the cake. korthner@my-deja.com wrote: > > Good day, folks. > > I'm trying to think up a not-too-difficult way of adding a serial > number to the Serial PROM used to program a Xilinx Spartan FPGA. > > The intent would be to use this as the Card Serial number, and once the > FPGA was initialized, it would then go and read the PROM itself. > > I've thought of haveing the serila number the last 48 bits, or > something like that. If I'm not mistaken, the serial stream for > programming the FPGA, including the CRC and everything else, is > finished before the actual end of the PROM. > > Can anybody confirm that this is doable, or does anybody have a better > way to do it? > > Thanks. > > -Kent > > Sent via Deja.com http://www.deja.com/ > Before you buy. -- Rick Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.com
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