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jimmy75@my-deja.com wrote in <8mjom3$6vc$1@nnrp1.deja.com>: >Spartan-II is a cheap version of Virtex devices with some features >removed (e.g. assynchronous BlockRAMs). But you probably do not need >these features anyway. I believe that the prices are < $10 a unit. >Check it out with Xilinx. ack! I thought that the functionality of the BlockRAMs in the Spartan-II were exactly the same as the Virtex. Can someone please explain to me the differences? Thanks! -KentArticle: 24401
I'm working on a design where I have two clock domains. I've decided to implement everything crossing the two domains using FIFOs, both BlockRAM-based, and distributed RAM based. I've looked at two application notes that deal with this, One aimed at the Spatan-II, and one for the 4000 series. In the appnote for the 4000 series (XAPP051, 1996, Peter Afke), Grey counters are used to improve speed and to simplify the generation of the FULL and EMPTY signals to prevent "weird" states. The new appnote for Spartan-II (XAPP175, 11/99) discusses pretty much the same thing, using grey counters and what-not, as well as keeping copies of "next_pointer"s make full and empty synchronous signals. The new appnote doesn't seem to consider how to prevent problems arising from using the two clock domains, however. I've copied what it said below, for anyone who wants to read it. In the old appnote, it suggested using latches, to latch the empty/fuill signal that was generated in the other clock domain, and then re-clocking the output of the latch with the desired clock. So, my question is, is it really suggested to use a latch at the output of simple combinatorial logic to "stretch" the full/empty signal and then re- clock it? I'm somewhat new to working in two clock domains, and I would rather figure it all out now, as I'm doing my design, then later when I'm dabugging it. Thanks a million. -Kent From XAPP175: "To solve this problem, and to maximize the speed of the control logic, additional logic complexity is accepted for increased performance. There are primary 9-bit Read and Write binary address counters, which drive the address inputs to the Block RAM. The binary addresses are converted to Gray-code, and pipelined for a few stages to create several address pointers (read_addrgray, read_nextgray, read_lastgray, write_addrgray, write_nextgray) which are used to generate the Full and Empty flags as quickly as possible. Gray-code addresses are used so that the registered Full and Empty flags are always clean, and never in an unknown state due to the asynchronous relationship of the Read and Write clocks. In the worst case scenario, Full and Empty would simply stay active one cycle longer, but this would not generate an error."Article: 24402
"K. Orthner" wrote: > jimmy75@my-deja.com wrote in <8mjom3$6vc$1@nnrp1.deja.com>: > > >Spartan-II is a cheap version of Virtex devices with some features > >removed (e.g. assynchronous BlockRAMs). But you probably do not need > >these features anyway. I believe that the prices are < $10 a unit. > >Check it out with Xilinx. > > ack! > I thought that the functionality of the BlockRAMs in the Spartan-II were > exactly the same as the Virtex. > You are right, there is no functional difference at all, but the speed parameters are slightly different. And the temperature-measuring diode has been traded for a power-down input in Spartan-II. And the available packages are quite different. Peter Alfke, Xilinx ApplicationsArticle: 24403
"K. Orthner" wrote: > jimmy75@my-deja.com wrote in <8mjom3$6vc$1@nnrp1.deja.com>: > > >Spartan-II is a cheap version of Virtex devices with some features > >removed (e.g. assynchronous BlockRAMs). But you probably do not need > >these features anyway. I believe that the prices are < $10 a unit. > >Check it out with Xilinx. > > ack! > I thought that the functionality of the BlockRAMs in the Spartan-II were > exactly the same as the Virtex. > You are right, there is no functional difference at all, but the speed parameters are slightly different. The LUT-RAM writing became synchronous in the olden days of XC4000-E. Much nicer, so you don't have to time the write pulse so tightly. The Virtex temperature-measuring diode has been traded for a power-down input in Spartan-II. And the available packages are quite different. Peter Alfke, Xilinx ApplicationsArticle: 24404
If there's no functional difference at all, does that mean that jimmy75 was mistaken? -Kent >You are right, there is no functional difference at all, but the speed >parameters are slightly different. > >Peter Alfke, Xilinx Applications > >Article: 24405
"K. Orthner" wrote: > I'm working on a design where I have two clock domains. Always remember that flipflops clocked by one domain and receiving data from the other domain can be metastable -- for more detail see application note 97, which gives data for 4000 series. (Peter Alfke, when can we expect that some more modern devices will get measured?) A gotcha that needs checking for is that Xilinx PAR can and will duplicate FF's for it's own purposes, such as to improve routing or timing. The answer below discusses this for the xc4000, but I would assume that PAR is still guilty until proven innocent. This is fine for most of the designs, most of the time, but not for signals that cross clock domains. http://support.xilinx.com/techdocs/3813.htm -- Phil HaysArticle: 24406
I must design asynchronous circuit on FPGA and I must know Gate-delay and interconnection delay for create Complete signal check (the signal which have delay longest than another in circuit). I design by RTL-VHDL code and synthesis by Xilinx Foundation 2.1i, my synthesis output is VHDL and SDF code. So can i use delay report from SDF code to be a Gate-delay?? and Where i can see interconection-delay of each signal??Article: 24407
In article <398B3965.8BA09BD3@ic.unicamp.br>, Rodolfo Jardim de Azevedo wrote: >I need SRAM modules (I think some >PCs use them as cache memory, that would be the best choice). Where can >I get some specification of such modules? How to make an interface? >(pinouts, time diagrams, ...) http://www.idt.com/products/pages/SRAM-PL101_Sub244_Dev215.html , for example. I am sure other SRAM vendors sell modules also. -- Gary Tse, gstse@home.com "Will write Verilog for food."Article: 24408
hey, what are the advantages from using Johnston counters in FIFO design --Erika Thanks In article <01bffffb$fa063c10$8c0af7a5@drt1>, "Austin Franklin" <austin@d44arkroom.com> wrote: > > Clocks are not very fast BTW, one is 40MHz and another > > just 10MHz... > > You're welcome. > > clocks, eh? Does that mean the FIFO has one clock for its input address > counter/flags and one for its output address counter/flags? Are you using > gray coded counters, and have a single point of synchronization between > time domains? Your flags must be referenced in the time domain you are > using them in... > > What is your input tool, Verilog/Synplicity or > Schematics/Viewdraw....perhaps? > > Sent via Deja.com http://www.deja.com/ Before you buy.Article: 24409
Hi, Does anybody know of any third party drivers for the Fujitsu MB87Y237 USB Core ? -- Shlomo K -------------------------------------------------- Shlomo Kut Vyyo Ltd PO Box 45017 Jerusalem 91450 Tel 972-2-5889715 Home 02-5618098 email: skut@vyyo.co.ilArticle: 24410
Is it worth upgrading from 2.1iSP6 to the new s/w ? Any experiences good or bad ? Considering that I now have to pay the ``time based license'' fee aka `the shareholders are complaining and chip prices are competitive so lets make more money out of the s/w' I want to know what the benefits are, if any. I don't actually mind paying a fair bit for Xilinx s/w - our original total outlay up to XCV1000 was about UKP3500 - since in general its pretty good. But I do strongly object to it timing out after a year. I want to buy the s/w, not rent it. Note for the lawyers: Normally if you are renting something and it goes wrong its the responsibility of the owner to get it fixed or replaced. Does this mean I can demand an instant fix for any serious bug I trip over ?Article: 24411
Rick Filipkiewicz a écrit : > I don't actually mind paying a fair bit for Xilinx s/w - our original > total outlay up to XCV1000 was about UKP3500 - since in general its > pretty good. But I do strongly object to it timing out after a year. > I want to buy the s/w, not rent it. Hi Rick From what I've heard, you don't rent it and it won't timeout, you just won't be able to use new chips if you don't buy the new version (in fact, you buy maintenance for one year) I hope I got it right... -- Nicolas MATRINGE DotCom S.A. Conception electronique 16 rue du Moulin des Bruyeres Tel +33 1 46 67 51 11 F-92400 COURBEVOIE - FRANCE Fax +33 1 46 67 51 01 http://www.dotcom.fr/Article: 24412
On Sat, 05 Aug 2000 21:04:08 -0500, Jack Lai <jwlai@mmmpcc.org> wrote: >Does anyone know who pickup the ABEL product line Dataio? > >Thanks, in advance for your help. > >Jck I'm pretty sure Xilinx bought it, but I don't know the details...Article: 24413
Mikhail Matusov wrote: > I believe you are right and it is a timing problem. There is a problem with Foundation/Alliance and the FIFO cores in the Xilinx app notes (which I assume is the same as what's in coregen). This problem manifests itself as a very over-optimistic timing report. Look at the Xilinx "answer" #6450 at http://support.xilinx.com/techdocs/6450.htm What this "answer" is saying is that the timing analyzer and the timing stuff in PAR doesn't, by default, analyze a timing path through an async set/reset input to a flip flop (FF). Let's say that there are three flip flops, A B and C. The output of A feeds the async reset of B, which outputs to the D input of C. If A and C use the same clock then the path through B is really just a combinatorial path-- however Foundation doesn't see it as a single path. Instead, it breaks it up into two paths, A-B and B-C. The net result is that the true path A-C isn't analyzed. If you look at some of the Xilinx app notes, you'll see this exact logic structure used to generate the full/empty flags. So, when you run the FIFO fast, you will be violating setup and hold time requirements and those flags will no longer work properly. The true speed is approximately 50% slower than what's reported by the timing analyzer. It also appears that the speeds reported in the Xilinx app notes are based on the same bad timing data. So, when they are reporting speeds of 150 MHz, reality is closer to 100 MHz (adjust for your own design constraints). I found this problem recently when debugging my own FIFO design. I used the same type of async reset system that Xilinx used and had the same type of timing problems. I have recently rewritten my FIFO to not use async resets while keeping the high speeds. This FIFO will soon be released as an upgrade to the Free-RAM core on the Free-IP Project web site. If this FIFO would be useful for you now, email me directly. Hope that helps! David Kessner davidk@free-ip.com http://www.free-ip.comArticle: 24414
"K. Orthner" wrote: > > I'm working on a design where I have two clock domains. > > I've decided to implement everything crossing the two domains using FIFOs, > both BlockRAM-based, and distributed RAM based. > > I've looked at two application notes that deal with this, One aimed at the > Spatan-II, and one for the 4000 series. ...snip... > I'm somewhat new to working in two clock domains, and I would rather figure > it all out now, as I'm doing my design, then later when I'm dabugging it. > > Thanks a million. > > -Kent There is more than one way to skin a cat. Sorry fluffy... The FIFO described in the appnote is the one that is the hardest to design and is used in the most stringent conditions. But you don't always have to do it that way. I don't remember the details of the FIFO in the app note, but it used some slightly tricky stuff to make sure that any timing "issues" with the flags always erred on the safe side of telling you it was full when it was not, etc... This circuitry made it a little harder to extend the size of the FIFO and just was not my cup of tea if I didn't have to use it. If your design is not pumping data on every clock cycle, you can put the FIFO entirely in one clock domain and cross the clock domains using a data register and a pair of FFs for the "data avail" signal. The pair of FFs are clocked by the "TO" domain and will keep the control signal from being metastable (within the reliablity requirements). The data register is clocked by the "FROM" domain but will not cause any problems because of the control signal delay. If you need to bring the FULL signal or an ACK signal back to the "FROM" domain, you will need to double FF it in the "FROM" clock domain. Keep in mind that the FULL signal needs to compensate for the FF delay, so set it high one or two samples early depending on your requirements. Because your counters are all in one domain, you can use regular counters. I used three; read addr, write addr and count. I think this is easier than comparing the addr counters. This can be a little complicated, but it is much simpler than the two clock FIFO. You just have to make sure that the limitations of this circuit fit your requirements. -- Rick Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 24415
Nicolas Matringe wrote: > > Rick Filipkiewicz a écrit : > > > I don't actually mind paying a fair bit for Xilinx s/w - our original > > total outlay up to XCV1000 was about UKP3500 - since in general its > > pretty good. But I do strongly object to it timing out after a year. > > I want to buy the s/w, not rent it. > > Hi Rick > From what I've heard, you don't rent it and it won't timeout, you just > won't be able to use new chips if you don't buy the new version (in > fact, you buy maintenance for one year) > I hope I got it right... They used to say... "We are selling you the routing and you get the gates for free!" Now they say, "We are selling you the maintenance and you get the software for free!" -- Rick Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 24416
erika_uk@my-deja.com wrote: > > hey, > > what are the advantages from using Johnston counters in FIFO design > > --Erika A Johnson ring counter uses N/2 FFs to encode N states. It is not nearly as efficient as a binary counter, but can be more easily decoded and has the Gray counter property of glitch free decoding. But the only way I have seen a counter like this used in FIFOs is as the high order counter which selected the bank of CLB rams. The Johnson counter would allow 2 input gates to decode the select signals for the banks. Or you could just use another N/2 FFs and design a standard ring counter with *no* decoding. -- Rick Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 24417
jimmy75@my-deja.com wrote: > > > comparison is that the value of a LUT varies tremendously depending on > > how it is used. As a logic element it's only worth aproximately 3 > gates, > > in an ASIC a two wide AOI and a couple of inverters would do much the > > same job. As memory it's worth a lot more, at least 16 ASIC gates, if > > you compare it to an ASIC RAM, or maybe as many as 64 gates if the > > equivalent structure was built out of random gates. > > That's what I do not understand. How does Xilinx count the system > gates? I understand the logic cell count (number of 4-LUTs). Now, what > does 4-LUT give in terms of gates? I mean do they take it as <=> 3 > gates (simple LUT) or 16, 64 gates -as you said- for an equivalent > RAM??? it seems it is ~12 gates. Anyone from Xilinx can help me here??? Why does this matter? The gate count is a very poor indicator of anything useful. Even the LUT count is a marketing number which does not even count LUTs! They count 4.5 LUTs per CLB when there are only 4 LUTs in a CLB! So why would you expect the gate count to be anything other than marketing fluff? The gate counting that they do is a little complicated since they have to make some assumptions for how much of the block ram to count as well as what modes you will use the other features in. So I don't think you will be able to figure it out without contacting them directly. -- Rick Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 24418
This is a multi-part message in MIME format. --------------53812157A4FB52AEF0F98E11 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit --------------53812157A4FB52AEF0F98E11 Content-Type: text/x-vcard; charset=us-ascii; name="jeff.carter.vcf" Content-Transfer-Encoding: 7bit Content-Description: Card for Jeff Carter Content-Disposition: attachment; filename="jeff.carter.vcf" begin:vcard n:Carter;Jeff tel;work:408.879.6961 x-mozilla-html:FALSE url:http://www.xilinx.com org:Xilinx Inc;W2C web | workflow | collaboration adr:;;2100 Logic Drive;San Jose;CA;95124; version:2.1 email;internet:jeff.carter@xilinx.com title:Sr. Information Systems Analyst fn:Jeff Carter end:vcard --------------53812157A4FB52AEF0F98E11--Article: 24419
Christian Mautner wrote in message ...
>Btw, I was looking for memory chip models some weeks again, and had to
learn
>that most vendors stopped giving them away for free, now you have to pay
for
>a software license of some denali (?) memory model software. I wouldn't be
>surprised if this is going to happen with the 74xx ICs too.
AMD's models are all in the Denali format, and the Denali stuff is
EXPENSIVE. Hence, a Real Good Reason not to use AMD parts.
AMD -- are you listening? Free models beget parts sales. Expensive models
beget alternate sources.
-- a
-----------------------------------------
Andy Peters
Sr Electrical Engineer
National Optical Astronomy Observatories
950 N Cherry Ave
Tucson, AZ 85719
apeters (at) noao \dot\ edu
"A sufficiently advanced technology is indistinguishable from magic"
--Arthur C. Clarke
Article: 24420
peter dudley wrote in message <8mk3gg$9gg$1@abq-news-01.ihighway.net>...
>Last December I bought the Xilinx Alliance Base software for some home
>projects that I had to do. Since then 3.1i has come out.
>
>Does anyone know if I should receive a free update on this software?
If you've paid the maintenance ransom, you should receive the 3.1i software.
At least, that's what I'm told. I'm still waiting for the software.
-- a
-----------------------------------------
Andy Peters
Sr Electrical Engineer
National Optical Astronomy Observatories
950 N Cherry Ave
Tucson, AZ 85719
apeters (at) noao \dot\ edu
"A sufficiently advanced technology is indistinguishable from magic"
--Arthur C. Clarke
Article: 24421On Mon, 07 Aug 2000 13:36:30 +0100, Rick Filipkiewicz <rick@algor.co.uk> wrote: >Is it worth upgrading from 2.1iSP6 to the new s/w ? Any experiences good >or bad ? I've used it for a few minutes, and it didn't crash. It gave poorer results for a 4085XLA that is 95% full and totally floorplanned. The design still meets all timespecs, but the safety margin ( -d 5) is not as good. Of course this might also be explained by new speed files that are not as optimistic. Since we dont have detailed routing timing information in the data sheet, how would we know? Run time was insignificantly faster. Certainly nothing like the claimed halving of runtime promised by marketing for 3.1i . Maybe the improvements are only for virtex designs. >Considering that I now have to pay the ``time based license'' fee aka >`the shareholders are complaining and chip prices are competitive so >lets make more money out of the s/w' I want to know what the benefits >are, if any. No you dont. The second paragraph of the license is: "IF YOU HAVE OBTAINED THIS SOFTWARE AS AN UPDATE TO SOFTWARE FOR WHICH YOU HAVE PREVIOUSLY OBTAINED A LICENSE, THE TERMS OF THAT PRIOR LICENSE WILL CONTINUE TO CONTROL YOUR USE OF THE SOFTWARE. IF YOU ARE A QUALIFIED UNIVERSITY USER, YOU MAY OBTAIN AN EXTENSION OF THIS LICENSE BY REGISTERING WITH THE XILINX UNIVERSITY PROGRAM." >I don't actually mind paying a fair bit for Xilinx s/w - our original >total outlay up to XCV1000 was about UKP3500 - since in general its >pretty good. But I do strongly object to it timing out after a year. I >want to buy the s/w, not rent it. The software does not time out. You just wont be able to get updates after a year unless you pay more maintainance. I suspect that access to the service packs will be controlled by your license registration (and its date), rather than the current system where you can download service packs without a check of whether you are in maintainance. Basically, just enforcing the terms of the license >Note for the lawyers: Normally if you are renting something and it goes >wrong its the responsibility of the owner to get it fixed or replaced. >Does this mean I can demand an instant fix for any serious bug I trip >over ? Sure you can demand. The results I suspect will be no different. Philip Freidin Mindspring that acquired Earthlink that acquired Netcom has decided to kill off all Shell accounts, including mine. My new primary email address is philip@fliptronics.com I'm sure the inconvenience to you will be less than it is for me.Article: 24422
Austin,
You can run ngdbuild on your design, which will merge all your netlists
together (including the coregen multiplier), then run ngd2ver to get a verilog
simulation file. This simulation will not have routing delays- it's purely
functional.
Mike
Austin Franklin wrote:
> Torbjörn Stabo <etxstbo@kk.ericsson.se> wrote in article
> <398A8153.6E265E32@kk.ericsson.se>...
> > > Anyone have any Verilog code they'd be willing to share for a 'decent'
> > > multiplier? I am looking for something that can do a 24 x 24
> multiply...it
> > > can take quite a few cycles, and it's for a Virtex architecture.
> >
> > Have you tried Coregen? No source, but it sounds like it's the result
> that matters to you..
> >
>
> Thanks for the suggestion, I did look at it, but it doesn't appear to have
> a Verilog output mode.
> If I don't get the Verilog source (or a protected model) then how do I unit
> delay simulate it?
Article: 24423rickman wrote: <The gate counting that they do is a little complicated since they have > to make some assumptions for how much of the block ram to count as well > as what modes you will use the other features in. So I don't think you > will be able to figure it out without contacting them directly. Peter answers: Here is what I explained more than a year ago. The numbers refer to an XC4000-XL part, but the concept is similar for Virtex. Gate count is a borderline meningless number when applied to LUT-based FPGAs, with large amounts of RAM on-chip, plus dedicated ( hidden and un-counted ) carry logic, sophisticated clock manipulation, and multi-standard I/Os. But as amanufacturer we have to come up with a number, and market the devices in a competitive environment. Anyhow, here is the old explanation from early 1999: Let me explain the 10,982 Logic Cells, 147 k bits of RAM and 265000 max logic gates claimed for the XC40125XV. This is a mixture of engineering specifications and marketing. Engineering specifications: The XC40125XV has a 68 x 68 array of CLBs = 4624 CLBs Each of these CLBs has 32 RAM bits = 147 968 RAM bits total. No ifs and no buts. Now we get into marketing: Since this is a competitive world, our users want to compare different manufacturers, but the structures are not the same. Altera puts eight LUTs in a block, Lucent puts four, and we put two LUTs into a CLB, but everybody's LUTs are more or less identical. So Xilinx decided to standardize the nomenclature and emphasize not CLBs but rather Logic Cells, as a lingua franca for FPGAs. Good idea! Then marketing saw the third LUT in our CLB and gave it a value of 3/8 of a Logic Cell, so the whole CLB is worth 2.375 LCs. Obviously, we can argue about this addition, but it is true that one can use the third LUT for some really nice and efficient solutions. :-) Multiply the 4624 CLBs by 2.375 and you get 10 982 Logic Cells. What is that in ASIC gates? There is no scientific answer, because it depends on the design. What is the LUT being used for, is the flip-flop being used at all, and what if you use the LUT as RAM ? Assume that every LUT is worth 6 gates and every flip-flop is worth 6 gates, then every Logic Cell is worth 12 gates (sometimes more, sometimes less). 12 gates times 10 982 LCs makes a bare-bone gate-count of 131 784, and that is reflected in the name of the device. We are conservative and round it down a little. :-) But there is the RAM in the LUT, and if only 25% of them are really used as RAM, these LUTs are not worth 6 gates, but rather 64 gates (16 bits with 4 bits per RAM cell, again, very conservative, ignoring the select structure and the read/write circuitry). That means, we must add another 58 gates times 25% of 9248 LUTs, which means another 134 096 gates, for a total of 265 880 logic gates. And we say explicitly that this assumes 20 to 30 % of the CLBs being used as RAM. That's how the XC40125XV got its name and its gate-count range of 125,000 to 265,000 gates. It is an attempt to bring some sanity to the gate-count confusion. Users will never agree about these assumption, and if you don't want to compare different manufacturers, then you can forget the whole thing and just stick with CLBs and RAM bits, for they are physical and thus non-controversial. Peter Alfke February 27, 1999Article: 24424
Hi Xilinx Freaks, I'm doing my first Spartan2(XC2S50) design with Foundation 2.1i_sp6. In my incremental design-process in vhdl, i want to check up the left resources in the fpga after each design-step. The Place&route report only informs me about the used I/O's, 'slices' and tbufs. In my design are lots of shiftregisters which do not need any lut, but if only 1 FF is used in a slice, the report seems to mark it as used. So the slice-count could not help me to estimate the free resources. In former Xilinx fpga families, the report gave me the exact information about used flipflops, 4input-luts, 3input-luts and so on. Is there any other simple way to check the resources ? I don't want to count the used luts in the fpga-editor, or in a netlist. Is Foundation 3.1 a solution ? Thanks in advance MIKE
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