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On Sun, 1 Oct 2000 20:45:18, Rick Filipkiewicz <rick@algor.co.uk> wrote: > > > Ray Andraka wrote: > > > Like I said, lots of bells and whistles, but nothing that I can see to justify > > the extra $$$. > > > > It's the special IPO release. The investors just got a bit freaked by the number > of amateurs using the tool. Yikes. I can be considered a newbie here, but at $20K for a license, plus $3K a year to keep the tool working, I don't think I qualify as an "amateur". I agree though. I don't see the bux for Pro. ..Amplify is another issue altogether. I'd like some information from anyone with experience with it. ---- KeithArticle: 26051
Hi, I have encountered a strange problem with Cypress PLL ICD2061A. The problem that I have is I couldn't get the Cypress part to program up to my desired frequency when I divide down a clock before it is output to the PLL. However, when I replace the divider circuit with a multiplexer, then the whole thing works. (Of course the parameters to program the PLL in these two cases are different). I am using Altera part EPF10K30E. So what could FPGA causes the PLL not to work well? Jitter or something else. Any clue? SherdynArticle: 26052
hi, for my designs, i have never introduced a placement information( apart from the ones related to the mapping) when my synchronous deisgn works as expected, i push the timing constraint up, to know what speed i can achieve from your experience( and hopefully from other experts ones), apart from the time saved from implementation process, have you beat timing driven design with a pre-placement one ? --Erika In article <39D77C9B.2CFEF178@andraka.com>, Ray Andraka <ray@andraka.com> wrote: > Absolutely! If you look at it carefully, the architecture is actually quite > regular. Put the first level adders on every other column, then insert the > second layer on every other interleaved column, the third on every other between > them and so on. This is quite fast for small trees. When the tree gets large > enough that the interconnect between levels is too long, you can add an extra > register at the inputs of the next layer to break up the long critical path from > the previous level through the carry chain. In the case of an FIR filter, using > the partially transposed architecture to absorb the delays, you use an adder > chain rather than a tree. That structure is good for an SDA filter with bit > rates of more than 150 MHz in a Virtex-4 (slow speed grade). > > erika_uk@my-deja.com wrote: > > > > hi ray, > > > > for the case of an adder tree do you still believe that building the > > adders using carry logic is wise ?. The architecture is irregular and > > the adders are all vertical > > > > --Erika > > > > In article <39D6B380.3383A152@andraka.com>, > > Ray Andraka <ray@andraka.com> wrote: > > > Ahh, but in the FIR filter you can go to a partially transposed > > architecture and > > > thereby absorb the delays as part of the sample delays you need > > anyway. There > > > is **no_latency_penalty** if you do it right! It is not the > > intuitively obvious > > > approach, though. > > > > > > Muzaffer Kal wrote: > > > > > > > > I am implementing a programmable FIR and latency is a very big > > > > problem. So my definition of best is the fastest design with at most > > > > one pipeline in the adder tree. Size of no importance. > > > > > > > > > > > > > > -- > > > -Ray Andraka, P.E. > > > President, the Andraka Consulting Group, Inc. > > > 401/884-7930 Fax 401/884-7950 > > > email ray@andraka.com > > > http://www.andraka.com or http://www.fpga-guru.com > > > > > > > Sent via Deja.com http://www.deja.com/ > > Before you buy. > > -- > -Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email ray@andraka.com > http://www.andraka.com or http://www.fpga-guru.com > Sent via Deja.com http://www.deja.com/ Before you buy.Article: 26053
Dear Friends: I would like to know that how to multiply e.g. 1100 with 0.0011. I already have an array multplier to multiply e.g. 1100 with 0110. But, now I want to multiply fractions (i.e. .0011) using the same multiplier, so what modifications should I do in the existing multiplier. RegardsArticle: 26054
> These parts are long over the hill (They were announced as end of life parts > some 7 or 8 years ago). None of the current generation tools support it. The > last xilinx tool set to support them was XACT6, which was replaced about 3 years > ago (and in my case 2 machines ago) by the M1 tools. If you can find someone > with a copy, and who is willing to give up the accompanying dongle you may still > not be able to use the tools unless you resurrect an old machine too. XACT6 was > a dos/windows3.1 toolset. It didn't work very well under windows95. At this > point, if your goal is learning, I'd recommend spending the $200 or so for the > XESS board plus the student edition of the current tools. The kit comes with > labs and a text. In the end, I think you'll wind up spending less and you'll > have current device experience. It's my job to keep up with these things so I'll make a slight correction here: the XESS XSK-40 kit has been reduced from $199 to $154. Prentice Hall no longer includes the labs and hardcopy text in the Xilinx Student Edition so XESS will provide its own version of these materials at www.xess.com in November. > > > "news.gate.net" wrote: > > > > I'm a rather "advanced" hobbyist, looking to get into some FPGA design (for > > starters, as some glue logic for an ISA PC Card). I recently stripped an > > old videoconferencing system and it had about 50 XC2018-P84C chips on it > > (also some XC3042's and a pair of XC3090's). It also has a lot of GALs, > > 57C291's, 57C45's, and some various Altera stuff. In short, it is a > > reprogrammable logic goldmine. > > > > But, many of the parts are out of production and finding development support > > for them is difficult. I have Protel 99 SE and have a simple design input > > into it (schematic). But, when I compile it, I get a message about missing > > PLA2XNF.EXE. I'm assuming this is part of the Xilinx XACT tools? > > > > The problem I have is that nothing currently available from Xilinx seems to > > support my XC2018 chips. I prefer to use the Xilinx stuff at this point, > > because I can store the programming in an EPROM (I have a burner) rather > > than having to program the actual chip (I don't have a burner capable of > > doing any programmable logic burning). > > > > Does anyone have some pointers as to where I can find support for these > > devices? (It appears that the student [and even professional] editions of > > Xilinx' stuff are geared toward their newer parts). > > > > Thanx in advance! > > Robert Garito > > rgarito@gate.net > > -- > -Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email ray@andraka.com > http://www.andraka.com or http://www.fpga-guru.com -- || Dr. Dave Van den Bout XESS Corp. (919) 387-0076 || || devb@xess.com 2608 Sweetgum Dr. (800) 549-9377 || || http://www.xess.com Apex, NC 27502 USA FAX:(919) 387-1302 ||Article: 26055
"Keith R. Williams" wrote: > On Sun, 1 Oct 2000 20:45:18, Rick Filipkiewicz <rick@algor.co.uk> > wrote: > > > > > > > Ray Andraka wrote: > > > > > Like I said, lots of bells and whistles, but nothing that I can see to justify > > > the extra $$$. > > > > > > > It's the special IPO release. The investors just got a bit freaked by the number > > of amateurs using the tool. > > Yikes. I can be considered a newbie here, but at $20K for a > license, plus $3K a year to keep the tool working, I don't think > I qualify as an "amateur". I agree though. I don't see the bux > for Pro. > > ..Amplify is another issue altogether. I'd like some information > from anyone with experience with it. > > ---- > Keith I'm sorry the ``amateur'' comment was meant as a joke about the meaningless addition of things like ``PRO'' to tools just to make them sound more serious & heavyweight.Article: 26056
David Forbes wrote > That AMP connector is a board-to-board 0.8mm pitch job, so you will not > find a cable that fits it. > > This sounds like a good time to vent some steam in the direction of > whoever designed a prototypng board with a 0.8mm pitch connector on it. > You might try looking in the Samtec catalogue. They have some 0.8 mm stuff that might be suitable for a bodge. And you can generally get their stuff within a few days or max 5-6 if its a custom special. Contrast AMP and or their distis: MOQ = 10-20 GUnits, lead time after your design has qualified for museum status. Company connector rules after much bitter experience: (1) If its not a PC world connector and its not in the Samtec book it doesn't get used. (2) If a client insists on some AMP special they source it.Article: 26057
"Xilinx, Inc. today announced full support of the entire Spartan-II FPGA family as well as the 300,000 system gate Virtex XCV300E FPGA in the WebPACK ISE tool suite. The free downloadable software, previously available only for Xilinx CPLDs, now offers a zero-cost-of-entry point for designing with Xilinx FPGAs." See http://www.xilinx.com/prs_rls/webfpga.html. (Yippee!) Jan Gray Gray Research LLC www.fpgacpu.orgArticle: 26058
Yes, in some cases by a factor of 2. One case for which I have become somewhat famous for is the one I presented at the FPGA'00 panel where an FIR filter (same one we've been discussing here) placed and routed automagically for a 95 MHz bit clock (missed the time spec which was for 120 MHz). The exact same design, when hand placed achieves 147 MHz. Don't let anyone convince you the tools can do as good a job with placement as the human brain. Placement can be done entirely from within the floorplanner, but if you are going to be reusing pieces, then it is often worth the effort to include the placement in the design itself so that you don't waste time repeating the layout on the same macro. erika_uk@my-deja.com wrote: > > hi, > > for my designs, i have never introduced a placement information( apart > from the ones related to the mapping) > when my synchronous deisgn works as expected, i push the timing > constraint up, to know what speed i can achieve > > from your experience( and hopefully from other experts ones), apart > from the time saved from implementation process, have you beat timing > driven design with a pre-placement one ? > -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com or http://www.fpga-guru.comArticle: 26059
No hardware changes needed in the multiplier itself. All you have to do is change the interpretation of the position of the radix point. It is equivalent to scaling your input and output by 32 in your case. Vipan Kakkar wrote: > > Dear Friends: > > I would like to know that how to multiply e.g. 1100 with 0.0011. I > already have an array multplier to multiply e.g. 1100 with 0110. But, > now I want to multiply fractions (i.e. .0011) using the same multiplier, > so what modifications should I do in the existing multiplier. > > Regards -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com or http://www.fpga-guru.comArticle: 26060
Someone should tell the Xilinx product people about this. Looking at the website shows no indication of any of this on the web pages that describe the WebPack ISE software. I also noticed that there are big differences other than just the chips targeted. The existing WebPack does not include FPGA Express synthesis, (not sure about XST, whatever that is) but the press release indicates that it now includes a full HDL capability. "WebPACK ISE is an Integrated Synthesis Environment?, which includes VHDL, Verilog and ABEL synthesis, HDL simulation and test vector generation..." Opps, reading the full press release says, "is scheduled for release in mid-October 2000". So I guess we will have to wait a few more weeks... Now if we can just get support for numeric_std! :) Jan Gray wrote: > > "Xilinx, Inc. today announced full support of the entire Spartan-II FPGA > family as well as the 300,000 system gate Virtex XCV300E FPGA in the WebPACK > ISE tool suite. The free downloadable software, previously available only > for Xilinx CPLDs, now offers a zero-cost-of-entry point for designing with > Xilinx FPGAs." > > See http://www.xilinx.com/prs_rls/webfpga.html. > > (Yippee!) > > Jan Gray > Gray Research LLC > www.fpgacpu.org -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 26061
Hey, believe it or not, FPGA Express v3.4 is not the ONLY target for this bitch-moan. Synplify Pro v6 fails, too. Target: Spartan XCS20XL. I instantiate (and also, with Synplify, infer) a bunch of 16x1 dual-port RAMs. The gotcha is that these RAMs need to be clocked on the falling edge. Now, after reading the Xilinx Libraries docs, I think that there's no such library part (falling-edge clocked RAM) for SpartanXL. But, looking at the CLB with the FPGA Editor, there's a clock-polarity-select mux right in front of the RAM clock input, soooooooo.... Anyways, according to Xilinx tech support, the clock inverter should be pushed into the CLB. But BOTH synthesis tools invert the clock in an LUT, then BUFG the inverted clock. Therefore, there's no way that the inverter can be absorbed into the CLB. This is a bug, plain and simple. -- a ---------------------------- Andy Peters Sr. Electrical Engineer National Optical Astronomy Observatory 950 N Cherry Ave Tucson, AZ 85719 apeters (at) n o a o [dot] e d uArticle: 26062
"Keith R. Williams" wrote: > > On Sun, 1 Oct 2000 20:45:18, Rick Filipkiewicz <rick@algor.co.uk> > wrote: > > > > > > > Ray Andraka wrote: > > > > > Like I said, lots of bells and whistles, but nothing that I can see to justify > > > the extra $$$. > > > > > > > It's the special IPO release. The investors just got a bit freaked by the number > > of amateurs using the tool. > > Yikes. I can be considered a newbie here, but at $20K for a > license, plus $3K a year to keep the tool working, I don't think > I qualify as an "amateur". I agree though. I don't see the bux > for Pro. Wow! I didn't realize the tool was $20K. I'll pass, thank you very much. -- a ---------------------------- Andy Peters Sr. Electrical Engineer National Optical Astronomy Observatory 950 N Cherry Ave Tucson, AZ 85719 apeters (at) n o a o [dot] e d uArticle: 26063
Seems to me that once the "next generation" of Xilinx' tools are released, the previous generation becomes the Student Edition. What an interesting way to keep selling the old stuff! -- a ---------------------------- Andy Peters Sr. Electrical Engineer National Optical Astronomy Observatory 950 N Cherry Ave Tucson, AZ 85719 apeters (at) n o a o [dot] e d uArticle: 26064
The efficacy of floorplanning (pipelined) adder trees (a 34% speed improvement, 78% PAR runtime savings) and other circuit types (constant coeff multipliers, filters, and butterfly networks), is explored in Satnam Singh's FCCM'00 paper "Death of the RLOC?", which is available at www.xilinx.com/labs/satnam. Jan Gray Gray Research LLCArticle: 26065
Sherdyn wrote: > > Hi, > > I have encountered a strange problem with Cypress PLL ICD2061A. I've used these successfully several times - they're great, but not always obvious. Have you used the bitstream generation proglet, or hand-cranked the calculations? Things I've got wrong in the past:- * Bitstream backwards, (the datasheet used to be rather ambigous) * non-monotonic serial clock, <- this was the real problem, use a fast, fast scope , or a few pF just to take the edge off anyway. * looking at the wrong output pin. (D'oh!) I'd pay good money for one of these devices, in a regular 14-pin oscmod case, with a watch LCD and up-down buttons for frequency, sometimes, just to see how close to the edge a design is running. Only the non-availability of watch LCDs has stopped me doing this myself...) > So what could FPGA causes the PLL not to work well? Jitter or something > else. Any clue? The don't seem too vulnerable to jitter, but I generally never hung them off anything other than other oscmods, or used their internal crystal drivers. Good luck - SteveArticle: 26066
rickman wrote: > I also noticed that there are big differences other than just the chips targeted. The existing > WebPack does not include FPGA Express synthesis, (not sure about XST, whatever that is) but the > press release indicates that it now includes a full HDL capability. > -- > XST, Xilinx's own Verilog & VHDL synth tool, is now just about useable since the 3.1i release has a decent-ish manual. It also runs nicely from the command line. I'm going to try & benchmark it against Synplify fairly soon. Now, Xilinx, how about actually getting some SpartanII's out the door so we can use the new free s/w.Article: 26067
Replying to myself: > Anyways, according to Xilinx tech support, the clock inverter should be > pushed into the CLB. > > But BOTH synthesis tools invert the clock in an LUT, then BUFG the > inverted clock. Therefore, there's no way that the inverter can be > absorbed into the CLB. I just got off the phone with Synplicity tech support (kudos to them: human beings answer the phone, and I was immediately transferred to tech support, and no one asked me for a User ID or anything!) and confirmed that it's a bug. It was reported for Virtex2; I mentioned that I'm using SpartanXL (and XC4KXLA, which is essentially the same thing). Falling edge clocks are dealt with by inverting the clock and buffering it, not by using the CLB clock-polarity mux resources. How long has that mux been in the architecture, anyways? No one uses the falling edge of the clock? The workaround is to instantiate the falling-edge triggered flops. That's not a solution when it's a counter I'm dealing with. -- a ---------------------------- Andy Peters Sr. Electrical Engineer National Optical Astronomy Observatory 950 N Cherry Ave Tucson, AZ 85719 apeters (at) n o a o [dot] e d uArticle: 26068
This seems very odd that both FPGA Express and Synplify have the same bug that I assume worked correctly at one time. It would be hard to imagine that this problem has been there from the start and no one noticed it. So how could two vendors develop the same bug at the same time? Andy Peters wrote: > > Replying to myself: > > > Anyways, according to Xilinx tech support, the clock inverter should be > > pushed into the CLB. > > > > But BOTH synthesis tools invert the clock in an LUT, then BUFG the > > inverted clock. Therefore, there's no way that the inverter can be > > absorbed into the CLB. > > I just got off the phone with Synplicity tech support (kudos to them: > human beings answer the phone, and I was immediately transferred to tech > support, and no one asked me for a User ID or anything!) and confirmed > that it's a bug. It was reported for Virtex2; I mentioned that I'm > using SpartanXL (and XC4KXLA, which is essentially the same thing). > > Falling edge clocks are dealt with by inverting the clock and buffering > it, not by using the CLB clock-polarity mux resources. How long has > that mux been in the architecture, anyways? No one uses the falling > edge of the clock? > > The workaround is to instantiate the falling-edge triggered flops. > That's not a solution when it's a counter I'm dealing with. > > -- a > ---------------------------- > Andy Peters > Sr. Electrical Engineer > National Optical Astronomy Observatory > 950 N Cherry Ave > Tucson, AZ 85719 > apeters (at) n o a o [dot] e d u -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 26069
rickman wrote: > > This seems very odd that both FPGA Express and Synplify have the same bug that I assume worked > correctly at one time. It would be hard to imagine that this problem has been there from the start > and no one noticed it. So how could two vendors develop the same bug at the same time? It's not so much a 'bug' that has developed, but a short comming, that wastes silicon. Attitude : Since it works the way they do it now, why fix it ? Falling edge clocks are a blind spot industry wide - they have only just recently become 'std' on CPLD's -- ======= 80x51 Tools & IP Specialists ========= = http://www.DesignTools.co.nzArticle: 26070
On Mon, 2 Oct 2000 17:46:50, Andy Peters <"apeters <"@> n o a o [.] e d u> wrote: > "Keith R. Williams" wrote: > > > > On Sun, 1 Oct 2000 20:45:18, Rick Filipkiewicz <rick@algor.co.uk> > > wrote: > > > > > > > > > > > Ray Andraka wrote: > > > > > > > Like I said, lots of bells and whistles, but nothing that I can see to justify > > > > the extra $$$. > > > > > > > > > > It's the special IPO release. The investors just got a bit freaked by the number > > > of amateurs using the tool. > > > > Yikes. I can be considered a newbie here, but at $20K for a > > license, plus $3K a year to keep the tool working, I don't think > > I qualify as an "amateur". I agree though. I don't see the bux > > for Pro. > > Wow! I didn't realize the tool was $20K. I'll pass, thank you very > much. Be careful here. I first bought Synplify for DynaChip (no laughing out there folks ;-). It was considerably less than $20K for a single vendor (though I can't remember). After Xilinx vaporized DynaChip (no, I never saw a DY8000 part, but have some pretty DY6000s that I may mount on a plaque, just to keep me humble) I had no choice to go for the to the Xilinx license, and Synplicity required me to go to the full-vendor license. The point being that a single-vendor license may be far cheaper than the circutious route I went through. ,,,I certainly hope so. It's a *great* tool, but it *is* expensive. Amplify is even more expen$ive, but it looks to be another winner. I put the $$ in the budget, but we'll see if anyone salutes when I try to spend the money. That said, I'm still confused about the process, but that's for their FAE's to straighten out (at $30K/WinLicense, I think they'll talk - when I'm ready ;-). ---- Keith P.S. I'm not threatened by being called an "amateur". I understood the comment. I am a relative newbie though (25+ years as a hardware designer, 1+ years doing this *neat* stuff). Just to be clear, I am also rather new to synthesis (good grief, I've been dreaming *in* VHDL recently), so treat me kindly. ;-) ---- KeithArticle: 26071
On Mon, 2 Oct 2000 17:48:51, "Jan Gray" <jsgray@acm.org> wrote: > The efficacy of floorplanning (pipelined) adder trees (a 34% speed > improvement, 78% PAR runtime savings) and other circuit types (constant > coeff multipliers, filters, and butterfly networks), is explored in Satnam > Singh's FCCM'00 paper "Death of the RLOC?", which is available at > www.xilinx.com/labs/satnam. Ok, I've tried to get this discussion going a time or two... What about HDL generated floor-planning? I'm specificly looking for *real* information about Synplicity's Amplify. I can read their Power-Point-Ware and I'm impressed. Anyone that has actually used it would be very helpful. Before I write the check for this widget ($30K + 20% forever) I'd like to be sure it does what I need. ---- KeithArticle: 26072
Jim Granville wrote: > > rickman wrote: > > > > This seems very odd that both FPGA Express and Synplify have the same bug that I assume worked > > correctly at one time. It would be hard to imagine that this problem has been there from the start > > and no one noticed it. So how could two vendors develop the same bug at the same time? > > It's not so much a 'bug' that has developed, but a short comming, that > wastes silicon. > Attitude : Since it works the way they do it now, why fix it ? > > Falling edge clocks are a blind spot industry wide - they have only just > recently become > 'std' on CPLD's Are you sure that this is not a new bug. I used both rising and falling edge clocks in a VHDL design I did using FPGA Express and Xilinx M1.5 about two years ago. There were no inverters in any of my clock paths. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 26073
> > P.S. I'm not threatened by being called an "amateur". I > understood the comment. I am a relative newbie though (25+ years > as a hardware designer, 1+ years doing this *neat* stuff). Just > to be clear, I am also rather new to synthesis (good grief, I've > been dreaming *in* VHDL recently), so treat me kindly. ;-) I had a dream that I was debugging a VHDL simulation! Now that's not right. Must be some type of recursion thing. Bob Sent via Deja.com http://www.deja.com/ Before you buy.Article: 26074
Hi Friends Here I have Xilinx demo board, but I dont know how to use it. Where can I find some information? Also Who can tell me how to generate bit file so that I can download to demo board? Thank you very much! Qian
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