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http://groups.yahoo.com/group/EEJOBS I like that one better. "A1A Computer Professionals" <tekjobs@a1acomputerpros.net> wrote in message news:3ab101ba.4509378@news.earthlink.net... > Find the latest electrical/electronic engineering jobs > > http://groups.yahoo.com/group/a1a-EEjobs > > > Use our archives to find your next job.. Easy keyword search engine. > > ASIC,RF,DSP,FPGA VHDL etc.. > > thanks for letting us post here.. >Article: 29901
Hi,
I'm trying to compile the WebPACK ISE example project,
but the translator exits with the message:
The XML Parser environment is incorrectly set up, preventing it from
finding its text transcoding files. Normally these will be located
via the ICU_DATA environment variable, or located relative to the
XML4C2 DLL (or SharedLib.) Please check your installation
EXEWRAP detected a return code of '9999' from program 'ngdbuild'
Done: failed with exit code: 9999.
What's going wrong?
Regards,
Mirek
Article: 29902
Hi,
It is straight forward, please find an example here:
-- Code starts -------
entity readstr is
end;
architecture behave of readstr is
procedure print_str (
signal in_str : in string) is
begin
report "Within Procedure" severity note;
report "String is " & in_str & LF severity note;
end procedure print_str;
signal str1 : STRING(1 to 100) := (others => ' ');
begin
str1(1 to 5) <= "Srini", "Test1" after 10 ns, "End.." after 100
ns;
print_str (str1);
end architecture behave;
-- Code Ends ----
HTH,
Srini
P.S. This message was better suited to comp.lang.vhdl NG, I guess!
Dave Glenton wrote:
>
> Anybody know how you can pass a text string to a VHDL procedure ?
> Idealy of variable length ?
>
> Cheers
>
> Dave Glenton
--
Srinivasan Venkataramanan (Srini)
ASIC Design Engineer,
Chennai (Madras), India
Article: 29903Clemens and Dennis, Can you list some of the more popular cores ? I really want to start a company writing cores. It's a dream I want to realize. Which area should I concentrate in ? Does that mean I will have to compete with the big guys like Altera and Xilinx ? Can I ask them to buy my IP cores ? Are there a lot of core providers out there who could make out quite well in this arena ? Or should I just concentrate in being a good engineer working for a nice company and retire there ? :-) I wish there is a way you can encrypt your code. Somehow, I think your unprotected source code will end up on the net somewhere. :-) ----- Original Message ----- From: "Zimba" <zimba@zamba.com> Newsgroups: comp.arch.fpga Sent: Friday, March 16, 2001 12:05 AM Subject: Re: IP Cores, Megacores > As I said before, the protection is as with other software since a core is > just software. You can't say Microsoft isn't making money selling software > even while it is obvious that everybody is giving it away to all of there > friends (without sources). > > If you sell a core to a company then there is no reason that the company > will give it away. Why would they give it away? And to who? A competitor? > Or, take me for instance, I don't even know somebody who might be interested > in a core I bought. Even if I would, I couldn't give it away. > > And even if people would give it away, as long as your market is large > enough and your product good enough you will still find customers and make > money. People that give your core away are like competitors. You just cannot > hope for selling your core to everybody that needs it. But then again, you > don't need everybody, a (small) percentage is enough. If your product is > good and your price is right, the customer will buy and you will make money. > > Did you ever try to use/modify somebody else's code? And without > documentation? This is one of the reasons why people pay for software: it > makes them save (a lot of) time. We paid happily $5000 for a core instead of > trying to develop it ourselves or looking for a free one. The core we got > was tested and working, with specialist support and we had it in just one > day! Now how can you beat that? > > Your biggest problem is probably finding the customers for your product and > not how to protect it. So stop worrying about it. > > Clemens > >Article: 29904
> Can you list some of the more popular cores ? I really want to That's an easy one. Look here for example http://www.opencores.org/ to get an idea of what is popular. (So maybe you shouldn't develop popular cores but develop custom cores instead.) Be a consultant, that's always good. > Does that mean I will have to compete with the big guys like Altera and > Xilinx ? Can I ask them to buy my IP cores ? Of course. They need cores to sell their products and they'll probably buy what they can get. > I wish there is a way you can encrypt your code. Somehow, I think your > unprotected source code will end up on the net somewhere. :-) IP cores are not like computer games. The market is much much smaller and populated by professionals who don't mind paying because they have the money. There are not a lot of (wizz)kids out there that enjoy cracking FPGA code. (Did you ever find a crack for say VisualDSP or Modelsim?) You are being paranoid for nothing: 1. You have to develop a core; 2. You have to sell it; 3. The buyer has to give it away; 4. The receiver needs web space to put it somewhere; 5. People have to find it. Where are you in this list? Get started and stop worrying. ClemensArticle: 29905
This is a basic problem, and has little to do with the Xilinx implementation.
When you change the length of a shift register dynamically: where do you throw
away bits when you shorten, and where do you pick up extra bits when you
lengthen ? At the beginning? at the end?
That's why it is safest to say the content is undefined for the next n clock
periods.
But if you know what you want to do, you can always design for that particular
situation, but first you must define your objective.
Peter Alfke
==============================
Heinrich Fonfara wrote:
> Hello,
>
> the RAM-based shift register created by the CoreGen for Virtex or
> SpartanII can be configured as variable length SR. This is a very
> usefull feature for my application, but in the product specification
> this module is referred to a "lossy" ("because when the Address is
> changed the output cannot be quaranteed to be correct for C clock cycles
> where C is the new value for the address").
> How to use the variable length feature of this module? Can someone tell
> me where
> can I get some more information about the operation in the variable
> length mode, perhaps some timing diagrams?
>
> Thanks in advance
>
> Heinrich Fonfara
Article: 29906Hi I just downloaded the Webpack and I tried to open a Virtex 300 design in the floorplanner. I get an error message "missing or invalid speed grade -6". The Floorpplanner doesn't have any speedgrade info on Virtex chips bigger than XCV200, although it is said to support all the Virtex family. What's missing? Thanks in advance -- Nicolas MATRINGE IPricot European Headquarters Conception electronique 10-12 Avenue de Verdun Tel +33 1 46 52 53 11 F-92250 LA GARENNE-COLOMBES - FRANCE Fax +33 1 46 52 53 01 http://www.IPricot.com/Article: 29907
Title: Senior I/O Designer Position Type: Permanent Location: Canada ( Markham, Ontario) Contact Name: Victoria Lee Contact E-mail: vickil@thepeoplewebinc.com ** All Moving expenses are fully covered** We are looking for an aggressive individual that will work within an integrated design team to craft leading edge I/O design for the next generation of Rage 3D graphics and multimedia products. A thorough understanding of the IC design process and tools. Must have a strong knowledge base in one of the following: memory interfaces (LVTTL/SSTL), PCI/AGP interfaces, GTL interfaces. Knowledge of ESD, latchup, and flipchip technology would be an asset. Responsibilities: Schematic capture, schematic simulation and analysis, layout design. Experience with HSPICE or any other CAD tools for schematic simulation; physical and electrical verification and DRC/LVS/LPE procedures. Master's or PhD degree in Electrical Engineering or equivalent with a minimum of 4 or 5 years related work experience. A Bachelor Degree in EE or equivalent with a minimum of 6 to 8 years related work experience will also be accepted. This opportunity comes with a very competitive salary and great stock options! Please forward your resume and salary expectations to: vickil@thepeoplewebinc.com -- The PeopleWeb Inc. Our business philosophy is based on our belief that "people deal with people they can RELY on" The PeopleWeb Inc. is a full service technology recruiting firm, that is recognized as a premier supplier of Internet Multi-Media professionals. We provide placements in all areas of technology, including Sales & Marketing. Our mandate encompasses permanent and contract positions. At the PeopleWeb Inc., we pride ourselves on our in-depth technology experience, which has resulted in a "web" of skilled technology professionals, and Fortune 500 clients. Through our experience, we have developed what we believe to be the best recruiting formula-"the Perfect Fit" - matching the right skill set and personality, with the right technical position, and corporate culture. Send your resume to: Victoria Lee Technical Recruiter Email: vicki@thepeoplewebinc.com Phone: (416) 483-5615 ext. 2109 Fax: (416) 483-6211 See our website at www.thepeoplewebinc.com for other postings.Article: 29908
ASIC Designer Position Type: Permanent Location: Toronto, Ontario Contact Name: Victoria Lee Contact E-mail: vicki@thepeoplewebinc.com ** All Moving expenses are fully covered** The duties of the designer can encompass all the activities of ASIC design including: VHDL/Verilog coding, synthesis, simulation & verification for deep sub micron designs test bench creation ASIC partitioning and floor planning continuous improvement of ASIC design flow ASIC integration into the system Qualifications: experience with the ASIC design flow, including HDL methods and tools experience with RTL coding in Verilog and/or VHDL experience with test development and debug strategies experience debugging silicon, boards, and systems must have a "hands on" mentality - a desire to identify and solve problems at the hardware level familiarity with one or more of CDMA, IS95, cdma2000 and/or WCDMA 2 to 4 years of relevant experience excellent written and oral communications skills, a team player Excellent opportunity for this digital wireless organization. Great compensation and stock options! This opportunity comes with a very competitive salary and great stock options! Please forward your resume and salary expectations to: vickil@thepeoplewebinc.com -- The PeopleWeb Inc. Our business philosophy is based on our belief that "people deal with people they can RELY on" The PeopleWeb Inc. is a full service technology recruiting firm, that is recognized as a premier supplier of Internet Multi-Media professionals. We provide placements in all areas of technology, including Sales & Marketing. Our mandate encompasses permanent and contract positions. At the PeopleWeb Inc., we pride ourselves on our in-depth technology experience, which has resulted in a "web" of skilled technology professionals, and Fortune 500 clients. Through our experience, we have developed what we believe to be the best recruiting formula-"the Perfect Fit" - matching the right skill set and personality, with the right technical position, and corporate culture. Send your resume to: Victoria Lee Technical Recruiter Email: vicki@thepeoplewebinc.com Phone: (416) 483-5615 ext. 2109 Fax: (416) 483-6211 See our website at www.thepeoplewebinc.com for other postings.Article: 29909
Graphics Board Design Engineers Position Type: Permanent Location: Markham, Ontario Contact Name: Victoria Lee Contact E-mail: vicki@thepeoplewebinc.com ** All Moving expenses are fully covered** Join the team that develops industry-leading board-level graphics products. Design and optimize high-speed, full-function Graphics products that take advantage of the latest 3D graphics accelerator ASICs. Use your solid understanding of digital hardware design, memory and PC bus interfaces and analog design to help develop new and exciting graphics products. We have career opportunities from Technician to Senior Engineers This opportunity comes with a very competitive salary and great stock options! Please forward your resume and salary expectations to: vickil@thepeoplewebinc.comArticle: 29910
ASIC Continuation Engineer Position Type: Permanent Location: Markham, Ontario Contact Name: Victoria Lee Contact E-mail: vickil@thepeoplewebinc.com ** All Moving expenses are fully covered** Join our ASIC design group to evaluate our leading edge graphics chips. Use your analytical skills to evaluate the functionality of our latest graphics chips and boards. Responsibilities: You will debug problems with the use of the latest electronic test equipment and coordinate Credence test vectors and test programs. Use your excellent communication and organizational skills to drive yield improvement, dpm reduction and assist FAE and foundry communications. You should be a college or university graduate or have equivalent work experience. Key skills include: analog electronics; digital electronics; experience with oscilloscopes and logic analyzers; PC bus interfaces such as PCI and AGP and PC architecture; ASICs This opportunity comes with a very competitive salary and great stock options! Please forward your resume and salary expectations to: vickil@thepeoplewebinc.com .Article: 29911
Senior Engineer, Process & Technology Position Type: Permanent Location: Markham, Ontario Contact Name: Victoria Lee Contact E-mail: vickil@thepeoplewebinc.com ** All Moving expenses are fully covered** As a key member of the highly skilled Process Technology team you will be involved in providing engineering support to product, test, and design engineers. Your contribution will be in analyzing and understanding yield and reliability issues and methods of improvements. As a representative you will correspond with the foundry on new technology processes : 1) to gather and disseminate information; 2) to recommend specific requirements for our leading edge designs; 3) to strategize migration paths to different fabs or processes. Requirements: Master's or PhD degree in Electrical Engineering or equivalent with a minimum of 5 years related work experience will be required or a Bachelor Degree in EE or equivalent with a minimum of 8 years related work experience will also be considered. Experience with VLSI design is desirable This opportunity comes with a very competitive salary and great stock options! Please forward your resume and salary expectations to: vickil@thepeoplewebinc.comArticle: 29912
Senior Engineer, Physical Design Position Type: Permanent Location: Markham, Ontario Contact Name: Kala Jenkins Contact E-mail: kala@thepeoplewebinc.com ** All Moving expenses are fully covered** Join our dynamic Physical Design Team and play a key role as a senior member. You will be responsible for the physical design of multi-million gate ASICs. Work will include floorplanning, hierachical timing driven place and route, clock treee synthesis, RC extraction and timing closure. Job Responsibilities: Include enhancing and redefining existing flows and methodologies. A thorough knowledge of physical design flows using Cadence or Avanti tools is a prerequisite. A Bachelor Degree or more in EE or equivalent with a minimum of 4 years physical design experience is required. This opportunity comes with a very competitive salary and great stock options! Please forward your resume and salary expectations to: vickil@thepeoplewebinc.comArticle: 29913
Senior Memory IC Designer Position Type: Permanent Location: Markham, Ontario Contact Name: Victoria Lee Contact E-mail: vickil@thepeoplewebinc.com ** All Moving expenses are fully covered** As a key member of a talented full custom circuit design team you will be responsible for specifying and developing SRAM design in deep sub-micron technology for a wide range of 3D and multimedia products. Participate in the complete ASIC development cycle from sub-system analysis to circuit design to product release. Must have proven expertise in designing SRAM circuits and embedded SRAM test and debug. The candidate will also be responsible for the qualification/maintainence of SRAM compilers. Working knowledge of IC fabrication process is certainly an asset. Successful candidate should possess excellent analytical capabilities and a strong desire to mentor. This position requires a Master's or PhD degree in Electrical Engineering or equivalent with a minimum of 3 years experience in SRAM design. This opportunity comes with a very competitive salary and great stock options! Please forward your resume and salary expectations to: vickil@thepeoplewebinc.comArticle: 29914
DV (Design Verification) Engineers Position Type: Permanent Location: Markham, Ontario Contact Name: Victoria Lee Contact E-mail: vickil@thepeoplewebinc.com ** All Moving expenses are fully covered** Design verification involves ASIC functional verification methods (methodology, S/W modelling, logic simulation, formal verification) to ensure robust, error free design are implemented. This job encompasses all these areas and offers candidates opportunities to develop their skills in these areas. The ideal candidate would possess a combined software and hardware background. The following is a synopsis of the various design verification areas: DV Methodology: Improving the system, methods, and process for ASIC design verification with an eye towards process efficiency, and verification coverage. Consider formal verification techniques and methodologies DV S/W Modelling: Deliver complex accurate functional S/W models (C++) of multimedia ASICs that serve as a reference for verifying ASIC designs. These qualified models also serve as a conduit for software development in our virtual ASIC environment in order to create software products for ASICs still under design. Drive the development of test plans, libraries, and tests necessary to exercise the design. DV Logic Simulation: Create supporting RTL simulation models in HDL to monitor the design behaviour and activity in order to verify correct design implementation at a transaction level. Implement the surrounding framework for supporting the logic simulation tools and environment. Experience/Knowledge (some areas but not all required) Good knowledge of ASIC design flow. Good knowledge of S/W object oriented design techniques. Basic knowledge of ASIC architecture, concepts and design principles and S/W engineering techniques (development, maintenance, source control). General understanding of hardware and software interaction within a system. Knowledge of gate level simulaton. Cell library modeling techniques with verilog or VHDL/VITAL. would be an asset,/li> Exposure to PCI/AGP bus, SDRAM, 1394, Digital Video Data Streams, Intel & AMD processor buses is an asset. OS Good working knowledge of UNIX (Solaris), Linux, Windows 2K Languages C/C++ HDL - VHDL or Verilog PERL Tools Shells (eg. tcsh) S/W development tools: gcc, VC++ (Developer Studio) VCS or ModelSim experience Simulator C API experience (Modelsim FLI or Verilog PLI preferred) Note: These skills broadly apply to all areas of the DV process. Potential candidates are not expected to possess skill in all these areas initially but should be capable of developing skills where deficient. This opportunity comes with a very competitive salary and great stock options! Please forward your resume and salary expectations to: vickil@thepeoplewebinc.comArticle: 29915
Peter Alfke schrieb: > > But if you know what you want to do, you can always design for that particular > situation, but first you must define your objective. Hey Peter, why dont you tell the guy the same you told us in munich?? You have a very good tutorial on this topic at your homepage. http://support.xilinx.com/support/techxclusives/SRL16-techxclusive2.htm Doesnt the left hand know what the right is doing ? ;-)) -- MFG FalkArticle: 29916
On Tue, 13 Mar 2001 19:58:16 -0800, Mark <mark.symonds@eng.monash.edu.au> wrote: >Hi All >Warning Newbie present!! > >Im a little lost as this is my first FPGA design. While the >below mentioned project works fine on a CPLD it gets >"glitched" when loaded into an FPGA. Probably just good luck that it is failing in the FPGA. You have a problem, and you see it with the FPGA. The CPLD is hiding it from you till you least expect it, then it will let it out too. Maybe when the design is in full production and you have shipped 1000's of them :-( >Its real simple and I suspect there is something very >basic Im missing. Imagine I know nothing about FPGAs. Maybe >I have a very simple circuit, power rails etc to the FPGA >and the I/Os arranged in banks of 8 to IDC headers. Connected >to one header is a 8bit piano switch bank switched to lo and >pulled hi via 10k resistors and the other is a bank of 8 LEDs. Decoupling caps to the FPGA power and ground pins? Is this wire-wrapped? How long are wires to FPGA VCC and GND pins? How long are wires from header to one side of switches? From other side of switches, how long is wire to GND? How long is wire from the pull-up resistors to VCC? How long is the wire from the pull-up resistors to the FPGA? Is there a single wire from each switch to GND, or are the switches all joined together with 1 wire to GND? Is there a single wire from each resistor to VCC, or are the resistors all joined together with 1 wire to VCC? Is the Clock signal wired up the same way as the 8 data bits? >The internal schmatic consists of one FD latch. the Q going >to an LED and the D going to a switch and the C going to a >second switch. >As expected the D is mirrored on the Q output on the low to >hi transition of the clock. This works fine. You dont have a de-bounce circuit, this will cause problems if your clock line ends up going to a counter or anything else that cares about the number of switch closures. >However if the C is held low any of the other 8 switches >(which remember are not internally connected or mentioned >in the sch) can cause the D to be reflected on the Q output. So all the above questions are because your problem is that you are managing to inject a short high pulse onto the clock line by the transient behavior on verious D lines. Thats why all the questions about wire length, and topology. >I realise this is a bit hard to visualise. I think I managed. >If anyone is interested I can send the project,sch or whatever. >FS 2.1i. please dont post schematics to this news group. The above questions should be sufficient. >Im going crazy not being able to work this out. The rest of >the project works fine. >Cheers Mark Philip Freidin Philip Freidin FliptronicsArticle: 29917
What scripts need to be run on Powerview Viewdraw 6.0 schematics to transport them to the XACT ver 5.2.1 environment. These are all UNIX based tools.Article: 29918
Dear Colleague: We are organising a Special Session on "Low-Power Electronics" in the 27th Annual Conference of the IEEE Industrial Electronics Society (IECON'01) in Denver, Colorado, U.S.A., and would like to invite research papers in this field. Papers will be peer-reviewed and the ones that are accepted will be presented and published in the Conference Proceedings. Details can be found in the pdf file to be found at http://www.isu.edu/~kantviti/announcements/IECON_CALL_2001.PDF. Please direct any questions to Vitit Kantabutra (vkantabu@computer.org) or Pasquale Corsonello (pascor@deis.unical.it). -- Vitit Kantabutra, Ph.D. Associate Professor of Computer Science College of Engineering Idaho State University Pocatello, Idaho 83209-8060 U.S.A. +1 208 282-3405Article: 29919
"The PeopleWeb Inc." wrote:
> Title: Senior I/O Designer
> Position Type: Permanent
> Location: Canada ( Markham, Ontario)
> Contact Name: Victoria Lee
> Contact E-mail: vickil@thepeoplewebinc.com
> ** All Moving expenses are fully covered**
>
O.k. I'm commuting from Barbados
>
> We are looking for an aggressive individual that will work within an
> integrated design team to craft leading edge I/O design for the next
> generation of Rage 3D graphics and multimedia products. A thorough
> understanding of the IC design process and tools.
>
I suppose you need agressive people for Rage graphics
>
> Must have a strong knowledge base in one of the following:
> This opportunity comes with a very competitive salary and great stock
> options!
>
Quoted on N
A
S
D
A
Q
|
|
\/
?
Article: 29920Boy, I sure hope that I don't upset anyone by asking if there is interest in my job posting! I am looking for a HW engineer for one of my favorite clients in Silicaon Valley. Take a look at the description!! If you are interested, shoot me an email so that I can call you and we can discuss the position. Please only contact me if you are a citizen or perm resident of the USA and you have experience in most of what they are asking for. (Salary is in the range of $100 - $120k. Great benefits and a great working environment. People who get a chance to work at this company LOVE it and never want to leave!) JOB REQUIREMENTS: 5 years of experience that includes 1)Lots of Embedded System Design (FPGA, ASIC and Micro controller firmware); 2) EMI issue resolution (including analog design skills with A/D and D/A); 3)High-volume product development experience that covers the complete life cycle; 4) Understanding of mechanical packaging design; 5) Power issues including low-cost power supplies, International power standards and connecting to an AC main.) Tricia Dolkas (650)964-6644 x126 tricia@lrc.comArticle: 29921
Nicolas Matringe <nicolas.matringe@IPricot.com> writes: > I just downloaded the Webpack and I tried to open a Virtex 300 design in > the floorplanner. I get an error message "missing or invalid speed grade > -6". The Floorpplanner doesn't have any speedgrade info on Virtex chips > bigger than XCV200, although it is said to support all the Virtex > family. What's missing? WebPACK does NOT support the Virtex parts. The only FPGAs WebPACK supports are the Spartan II and a single Virtex-E part, the XCV300E. It does not support the Virtex 300 (non-E version). You might be able to use it for Virtex parts that have matching Spartan II sizes (XCV50, XCV100, XCV150, XCV200), but only -5 and -6 speed grades are supported, and I'm not sure how closely the Virtex and Spartan II speed grades match.Article: 29922
Hello Everybody,
We have a doubt in instantiation of core generator.
We have a generated our customized block of block ram from core generator ,
which has a 128*32 of virtex family. Symbol for this block has also generated
which is present in the local library(library of project name).
But when we use this block in our design it has problem like
1) while synthesizing it says that the reference design( for all block ram of different size )
is not linked and
2) but even though we tryed to implement it, at that time all the block ram's are
implemented except the size of 128*32(here it is unable to place and route).
but in Xilinx manual they have given that we can have a size of 128*32.
i would to know why the blocks are not linking and why there is an error in the particular
size (128*32) while implementing.
thanx in advance,
manjunathan.
Article: 29923Manjunathan wrote: > <snip> > > but in Xilinx manual they have given that we can have a size of 128*32. > > i would to know why the blocks are not linking and why there is an error in the particular > size (128*32) while implementing. > The Xilinx data book clearly states that the widest BlockRAM implementation is 256 x 16. There is no dual-ported 128 x 32 BlockRAM in Virtex or Virtex-E. (There is 512 x 36 in Virtex-II) But there is hope: If you neede only a single-port RAM, you can implement a 256 x 16 BlockRAM but address the two ports in parallel, making the most significant address bit a 1 on one port, and a 0 on the other, and, voila, you have a 128 x 32 single-port BlockRAM. Peter Alfke, Xilinx ApplicationsArticle: 29924
Rick Filipkiewicz wrote: > > "The PeopleWeb Inc." wrote: > > > Title: Senior I/O Designer > > Position Type: Permanent > > Location: Canada ( Markham, Ontario) > > Contact Name: Victoria Lee > > Contact E-mail: vickil@thepeoplewebinc.com > > ** All Moving expenses are fully covered** > > > > O.k. I'm commuting from Barbados > > > > > We are looking for an aggressive individual that will work within an > > integrated design team to craft leading edge I/O design for the next > > generation of Rage 3D graphics and multimedia products. A thorough > > understanding of the IC design process and tools. > > > > I suppose you need agressive people for Rage graphics > The local Super-Valu had an outdoor sign up for many months: "visit our Aggressive Meat Department". I don't know what cracked me up most - the images that came to mind of rude, pushy butchers harassing customers or the aggressive meat itself assaulting them. Or maybe I was just amazed that an induhvidual could come up with such a dumb slogan. regards, tom
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