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"Allan Herriman" <allan_herriman.hates.spam@agilent.com> wrote in message
news:3AF21B12.3047C71C@agilent.com...
> Erik Widding wrote:
> >
> > This used to work, because back in 1984, DRAMs were much simpler.
>
> IIRC, redundant rows were used in Intel's 2164 64k x 1 DRAM, which came
> out before 1984. The technique was described in the 1983 Intel Memory
> data book.
Thanks for the fact. I didn't realize the process dated quite so far back
in production use. I would be interested to see the marketing spin on a
"new technology" such as this.
> Actually, just as hard disks have a table of bad sectors that the
> operating system knows to avoid, is there any theoretical reason why a
> list of bad resources on an FPGA die can't be fed to to the back end
> tools?
> (There are plenty of practical reasons why not, of course.)
^^^^^^^^^^^^^
Practical reasons why not, the first two that come to mind:
1. New place and route for each individual fpga.
2. Great deal of software engineering cost for the chip makers, so they
could sell partial good parts, at a discount from all goods, thus losing the
incremental revenue.
Regards,
Erik Widding
--
Birger Engineering, Inc. -------------------------------- 781.481.9233
38 Montvale Ave #260; Stoneham, MA 02180 ------- http://www.birger.com
Article: 30951??? For the big complex designs that are currenlty being designed (and that will only get bigger), records are IMHO the only to at least for now escape the explosion of signals that are going between modules. Also for complex data structures it make code much cleaner. Synthesis tools generally have no problem dealing with records. What might be a bit trickier is that fact that it become more difficulat to trace back in the netlist the original elements of the record, but since netlist hacking is on the way back anyway, that's a disadvantage that I am more than willing to live with. Why do you want to know exaclty how the synthesis tool handles them? Synopsys DC is very predictable in this: it puts the signals in the order of declaration... Tom > Hello Olivier, > > from my experience it is best not to use records for synthesis. One reason > is that you never know exactly how the synthesis tool handles them (as your > problems demonstrate). > > Best regards > Markus.Article: 30952
This is a multi-part message in MIME format. --------------02B0ED626BFC730FB4BC5BCE Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit If you are performing a Verilog simulation, it is possible you are seeing a pulse swallowing issue. Take a look at http://support.xilinx.com/techdocs/9872.htm and see if this applies to your situation. -- Brian "Roger.chen" wrote: > My design is quite large,the functional simulation is ok.When doing post timing,I found the output 200MHz clock of my clock module is constant "0", later I tried to do timing simulation of clock module seperately,the problem still exists. > one of my clock module input clock CLKIN is 50MHz, a DCM is used to generate CLK1X(50MHz),CLK2X(100MHz),CLK4X (200MHz).CLK4X is output signal DCM CLKFX through a BUFGMUX.the design is quite simple ,however, I met following problem during post timing simulation: > When I set CLKIN to 50MHz, CLK4X didn't appear,but CLKFX is ok(200MHz);CLKFX is the output of DCM and input of a BUFGMUX,CLK4X is output of this BUFGMUX and output of clock module. > but when I set CLKIN to 25MHz, CLK4X is ok, my clock module goes well. > Device family VitrtexII xc2v1000. > Developing tool: Foundation iSE 3.1i > I think the problem lies in BUFGMUX, but I dont konw what to do with. --------------02B0ED626BFC730FB4BC5BCE Content-Type: text/x-vcard; charset=us-ascii; name="brian.philofsky.vcf" Content-Transfer-Encoding: 7bit Content-Description: Card for Brian Philofsky Content-Disposition: attachment; filename="brian.philofsky.vcf" begin:vcard n:Philofsky;Brian x-mozilla-html:TRUE url:http://www.xilinx.com org:Xilinx Software Marketing;SLAM adr:;;2300 55th St;Boulder;CO;80301;USA version:2.1 email;internet:brian.philofsky@xilinx.com title:Sr Technical Marketing Engineer fn:Brian Philofsky end:vcard --------------02B0ED626BFC730FB4BC5BCE--Article: 30953
Huang <> wrote: : When I started routing my design, PAR terminated abnormally, with the following error information. : Routing active signals. : INTERNAL_ERROR:SpeedCalc:basndtiming.c:887:1.6 - Getnodeparms for node not on : signal : EXEWRAP detected a return code of '-1073741819' from program 'par' : Done: failed with exit code: 0005. This looks like a tool internal error, most likely not a problem with your design. We would have to investigate it further to determine the actual cause. Please open a case with Xilinx for this. Carl SternArticle: 30954
In article <3AF2A391.DB76D960@celogic.com>, Olivier MALLINGER
<omallinger@celogic.com> writes
>In an application, we try to use record type in an architecture with
>several levels.
<snip>
>If the signals are input, the use of record type doesn't make any
>problem nor in simulation, nor in synthesis.
>As ouput, many problem appear. The instantation in level 01 of a X type
>signal with X type output signals of level 011, 012 and 013 shows bus
>conflicts (whereas each agregate in the signal of level 01 is only
>driven by one signal in the sublevels).
>
>In simulation, we found a solution. It's to initialize all the signals
>with 'Z', to use the resolution function of std_logic type, which can
>resolve these conflicts because 'Z' is the lowest priority in this
>function.We use Innoveda Speedwave to simulate our design.
>
>In synthesis, the same problem appear but the bus conflict cannot be
>resolved and it's impossible to synthetize our design. We use FPGA
>Express to synthetize our design.
I think the problem is nothing directly to do with records or
hierarchy. The problem is that you must write your own
resolution function, something like this:
package myrecs is
type RecU is record -- A very simple record, for example
A, B: std_logic;
end record;
-- Type-name for an array of these records, needed later:
type RecU_A is array (natural range <>) of RecU;
-- Now create a resolved type to match the record type:
function resolved(V: RecU_A) return RecU;
subtype RecR is resolved RecU;
end;
-- This package body contains the resolution function.
package body myrecs is
function resolved(V: RecU_A) return RecU is
variable sA,sB: std_ulogic_vector(V'range);
variable R: RecU;
begin
-- Convert the array of records into separate arrays,
-- one array for each element of the record type:
for i in V'range loop
sA(i) := V(i).A;
sB(i) := V(i).B;
end loop;
-- We use the usual std_logic resolution function to resolve
-- each element of the record...
R.A := resolved(sA);
R.B := resolved(sB);
return R;
end;
end;
Some synthesis tools cannot deal with user-written resolution functions.
However, I tried this example with Leonardo Spectrum and it worked fine.
I'm not sure of the limits on this - possibly it works only because
I used the std_logic resolution function to do the hard work.
The synthesis tool has detailed knowledge of std_logic built in to
its code, but it has to work out how to handle the new resolution
function based on my VHDL.
I also tried it with FPGA Compiler 2 / FPGA Express (version 2000.11)
and it worked, but only when I added the pragma
-- pragma resolution_method three_state
to the resolution function. Perhaps this pragma will fix your problem.
HTH
--
Jonathan Bromley
DOULOS Ltd.
Church Hatch, 22 Market Place, Ringwood, Hampshire BH24 1AW, United Kingdom
Tel: +44 1425 471223 Email: jonathan.bromley@doulos.com
Fax: +44 1425 471573 Web: http://www.doulos.com
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Article: 30955my book "Component Design by Example ... a Step-by-Step Process Using VHDL with UART as Vehicle" has a full pledged UART. The TOC of the book is at my site, and so is an update of the FIFO. It consists of several partitions that can be tailored. --------------------------------------- Ben Cohen Publisher, Trainer, Consultant (310) 721-4830 http://www.vhdlcohen.com/ vhdlcohen@aol.com Author of following textbooks: * Component Design by Example ... a Step-by-Step Process Using VHDL with UART as Vehicle", 2001 isbn 0-9705394-0-1 * VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn 0-7923-8474-1 * VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn 0-7923-8115 --------------------------------------------------------------------------Article: 30956
Hi, I use xilinx foudation ISE timing analyzer( I set timing constraint, CLK=360MHz and turn on the option:perform hold/race checks(skew analysis) ) for my virtex II design, and the timing requirement can be met, but when I use the latest modelsim to do timing simulation, and I set the setup time and output delay the same as timing analyzer, i.e., 0.23ns and 0.4ns respectively, the outputs are wrong(red sign)( the function simultation is correct ). What is the reason? Which one should I trust, the timing analyzer or the modelsim? Thank you very much. Sincerely yours, tiderhArticle: 30957
"Matt Billenstein" <mbillens@mbillens.yi.org> writes: > All, I have one register in my design that is clocked by a signal not on a > GCLK pin... Right now I run it through and IBUF, then a BUFG and then to > the register, but it gets routed all over the place in doing this. Is it > possible to just run the signal from the IBUF to this one register? The > tools don't seem to like it, I get errors during translate saying the signal > has an illegal connection... > > I'm using foundation 3.1i sp7 and VHDL design entry. The synthesizer inserts a global clock buf, and the Xilin P&R can't do much about that. In Synplify, you can tell it to not put in a global buffer (if I remember correctly). Which synthesizre do you use? If you have more than 4 global clocks, the fifth clock will be "local", i.e. not using the BUFG. Now, why do you want to do this? For fun or for a reason? Homann -- Magnus Homann, M.Sc. CS & E d0asta@dtek.chalmers.seArticle: 30958
Is there a way of specifying OFFSET = IN AFTER and OFFSET = OUT BEFORE from the constraints editor (Alliance 3.1i)? I would rather have the tool do the arithmetic (clock cycle isn't fixed). ---- KeithArticle: 30959
>I have learned programmers do not necessarily make good hardware engineers. >It is a different mind set and discipline. There is much background that is >not required for programming that is required for digital design. Also for all the numbers of C++ programmers around these days, there are very few good ones who turn out solid reliable code. Software you can debug, but it gets harder with hardware; you cannot just pop in a few breakpoints here and there... Peter. -- Return address is invalid to help stop junk mail. E-mail replies to zX80@digiYserve.com but remove the X and the Y. Please do NOT copy usenet posts to email - it is NOT necessary.Article: 30960
Consider doing a software UART in the CPU - it will be free, and is very easy to do especially if you can limit it to half-duplex operation. Alternatively, you will find that programming a cheap micro like e.g. the Atmel 90S1200 ($1.50 1k+) to do it will cost a lot less than the FPGA. >Does anyone know of where I can find a free Verilog source code for a Serial >UART that can be used in a Xilinx XC4005XL FPGA? I am in need of such code >to add to a FPGA design I am making for remote access to the FPGA CPU... Peter. -- Return address is invalid to help stop junk mail. E-mail replies to zX80@digiYserve.com but remove the X and the Y. Please do NOT copy usenet posts to email - it is NOT necessary.Article: 30961
I am using an XESS XS40 prototyping board and I have a verilog program that, when synthesized, stores a 9 bit value in a register which is updated at certain points in time. Here's the problem: I need to get the data from this register into my PC through the parallel port. I don't have much experience with this, so I'm looking for code examples of how to read the data in on the PC, and also how I would go about sending the data out since, according to the docs, I can only use the 5 status pins of the parallel port to send data from the FPGA to the PC, but I have 9-bit addresses I need to send. I'm assuming I'll have to shift the data out bit by bit and also generate a clock signal on one of those 5 status pins, but I'm vague on the actual implementation. I'm sure many of you have either used these boards or have had to code something similar before, so any code examples, links to code examples, or general advice would be greatly appreciated. Thanks! VikArticle: 30962
Hello, I am looking for a VHDL/synthesis book. One similar to "Numerical methods in C" I looked at VHDL coding styles by Cohen, but I want to know if anyone had other suggestions SWArticle: 30963
Parallel port info, examples, links, and other neat stuff here: http://www.beyondlogic.org/ vikram m n rao wrote: <snipped> > > Here's the problem: I need to get the data from this register into my PC > through the parallel port. I don't have much experience with this, so I'm > looking for code examples of how to read the data in on the PC, and also Tom Burgess -- Digital Engineer Dominion Radio Astrophysical Observatory P.O. Box 248, Penticton, B.C. Canada V2A 6K3Article: 30964
VHDL for Logic Synthesis, by Rushton Logic Synthesis Using Synopsys Kurup and Abbasi "Su We" <sweather1999@yahoo.com> wrote in message news:M%GI6.109133$xN4.7204704@news1.sttls1.wa.home.com... > Hello, > I am looking for a VHDL/synthesis book. > One similar to "Numerical methods in C" > > I looked at VHDL coding styles by Cohen, but I want to know if anyone had > other suggestions > > SW > >Article: 30965
Steven, You can find the CompactPCI board on Xilinx FPGA at http://setltd.com/products/instrumental/CPCI/xdsp3mc/ At XDSP-3MC we can set up to 2 banks high-speed ZBT SRAM up to 8(16)Mb each with independent addressing. And in 3Q01 we will put on the market our new board with one Xilinx FPGA in BG560 and one SDRAM socket with up to 512MB SDRAM 100MHz. Regards,Article: 30966
Hi, James! You can see a wide set of PCI boards on Xilinx FPGA at http://setltd.com/products/instrumental Regards, VladimirArticle: 30967
Find the latest electrical/electronic engineering jobs http://a1ajobs.com/ee/ Use our archives to find your next job.. Easy keyword search engine. ASIC,RF,DSP,FPGA VHDL etc.. thanks for letting us post here..Article: 30968
On Mon, 30 Apr 2001 21:04:49 +0200, Jonas Thor <thor.NO@SPAM.sm.luth.se> wrote: >Hello! > >This is a not well defined question, but I'll ask anyway... I want to >measure, with high precision, the time between two rising edges of two >pulses. I have a reference clock, frequency F, of about 5-10 MHz, but >I need measurements much more accurate than 1/F. (The rising edges are >of course asynchronous to the reference clock.) > >What can I do in a FPGA get the best precison? What's the best I can >do without a DLL and with a DLL? > >Thanks for any advice! > >/ Jonas Thor Jonas, there are lots of sub-clock interpolation techniques. One runs a square wave through a tapped delay line, and latches the state of the taps when an event comes in. The data in this pattern can be decoded to get sub-clock resolution. LeCroy made a custom CMOS chip with the delay line in silicon, and got 0.5 ns resolution. Somebody in Hungary or somewhere has a trick using a standard FPGA... I'll look for the reference and post it if I can find it. There are lots of analog ramp interpolation tricks. Art of Electronics has a couple. You can also just average lots of events, if the timebase is asynchronous to the events themselves. My company makes time-to-digital converters down to 48 ps lsb, using fairly slow (like 25 MHz) clocks, and we're working on faster stuff, but I can't explain this in detail in public. Contact me (despam my address) and maybe I can help. Here's one... http://www.HIGHLANDTECHNOLOGY.com/DSS/V680DS.html JohnArticle: 30969
Hi, I have an old ISA board with an Altera FPGA configured as a frequency counter. I would like to extend the functionality of the board but have no FPGA experience. I do however have the original code (MAXPLUS II). Can anyone recommend a consultant? Philip.Article: 30970
In article <3AAD81C5.5CE25CD3@egr.msu.edu>, Terry <hicksthe@egr.msu.edu> wrote: > The system consists largely of two counters with ECL front ends with ECL > enables. The toggle rate that I would like to get out of the VirtexE is > about 350MHz. Is that easily within the reach of the VirtexE chip? I have a demo board in my lab at work where we are hitting the Virtex-E LVPECL I/O with parallel data at 200 Mbps with no problem. We designed in an extra data and clock line for funsies, and ran that to 1.2 Gbps data clocked DDR style with a 600 MHz clock. It actually worked, so I'd have no qualms about running up to 350 MHz. They're rated to 311 MHz, if I recall correctly, so you'll want to use a DDR input technique for 350 Mbps data.Article: 30971
Quiet Desperation wrote: > In article <3AAD81C5.5CE25CD3@egr.msu.edu>, Terry > <hicksthe@egr.msu.edu> wrote: > > > The system consists largely of two counters with ECL front ends with ECL > > enables. The toggle rate that I would like to get out of the VirtexE is > > about 350MHz. Is that easily within the reach of the VirtexE chip? > > I have a demo board in my lab at work where we are hitting the Virtex-E > LVPECL I/O with parallel data at 200 Mbps with no problem. I think the original question was for a counter. That's even easier. Just use a global clock. For higher frequency resolution you can use a ripple front-end, clocked from any near-by input, and then use a global clock at half or one quarter the frequency. There ar many ways... My goal is still a 1 GHz counter, and that works only with the prescaler in the Virtex-II DCM, which has been verified by our friend Austin to toggle at 1.1 GHz. Peter Alfke, Xilinx ApplicationsArticle: 30972
Well Ernst, if you still need that IP Interface i can write it for you in VHDL and have it implemented on XC4000 . let me know email : asimghr@yahoo.comArticle: 30973
On Sat, 05 May 2001 14:56:53 -0700, John Larkin <jjlarkin@highlandSNIPTHIStechnology.com> wrote: >One runs a square wave through a tapped delay line, and latches the >state of the taps when an event comes in. The data in this pattern can >be decoded to get sub-clock resolution. LeCroy made a custom CMOS chip >with the delay line in silicon, and got 0.5 ns resolution. Somebody in >Hungary or somewhere has a trick using a standard FPGA... I'll look >for the reference and post it if I can find it. I searched and came up with this. You probably meant this article? "Interpolating time counter with 100 ps resolution on a single FPGA device" Szplet-R; Kalisz-J; Szymanowski-R IEEE-Transactions-on-Instrumentation-and-Measurement. vol.49, no.4; Aug. 2000; p.879-83. / Jonas ThorArticle: 30974
On Sun, 06 May 2001 13:21:11 +0200, Jonas Thor <NoSpam.thor@sm.luth.se> wrote: >On Sat, 05 May 2001 14:56:53 -0700, John Larkin ><jjlarkin@highlandSNIPTHIStechnology.com> wrote: > > >>One runs a square wave through a tapped delay line, and latches the >>state of the taps when an event comes in. The data in this pattern can >>be decoded to get sub-clock resolution. LeCroy made a custom CMOS chip >>with the delay line in silicon, and got 0.5 ns resolution. Somebody in >>Hungary or somewhere has a trick using a standard FPGA... I'll look >>for the reference and post it if I can find it. > >I searched and came up with this. You probably meant this article? > >"Interpolating time counter with 100 ps resolution on a single FPGA >device" > >Szplet-R; Kalisz-J; Szymanowski-R > >IEEE-Transactions-on-Instrumentation-and-Measurement. vol.49, no.4; >Aug. 2000; p.879-83. > >/ Jonas Thor Jonas, Yeah, that sounds like it. Last time I heard from them, they were eager for licensing deals, so you might want to contact them. I have their lit in one of the many piles of paper on my desk, I think, so let me know if you can't track them down. John
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