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I'm in a situation where we have an ASIC on the motherboard which can be replaced, for IP development purposes, by an FPGA on a plug-in module. Unfortunately the module was thought of in the Virtex days, pre -E, & there isn't a whole lot of room inside the connector ring to put ranks of QuickQwitch level converters for the external 5V PCI & IO busses. The data sheet says that 5V tolerance can be re-gained with a 100R series res. I assume its to reduce current through the clamp diode. Does this work o.k. ? Is 100 a voodoo value that can be made smaller ?Article: 30676
The CIC's response curve is sinx/x, which is to say it is not shaped very nicely. Typically the CIC is cascaded with a shaping filter that a) limits the signal passband to a fraction of the CIC's first null and b) flattens the response in the passband. That shaping filter can be (and typically is) made into an interpolating or decimating filter using polyphase techniques. For low interpolation or decimation ratios, using a CIC brings little to the party. Also, one of the values of the CIC is that for higher decimation ratios (above about 16), the shape of the CIC filter referenced to the output sample rate is for all practical purposes constant, so the shaping filter does not have to be reprogrammed when the decimation/interpolation ratio is changed. At low CIC ratios, the changes in the curve shape are more pronounced, so the shaping filter also needs to be updated for a constant composite response. Paul Teagle wrote: > > Hi, > > I'm wondering why many of the newer (dedicated or FPGA) filter or > upconversion devices have CIC interpolators/filters, with a lower limit on > the amount of interpolation available, eg, many have a minimum interpolation > of 8. For an interpolation value say of 3, with a low pass response, are > there better (faster or more silicon-area efficient) ways to achieve this > than CIC ? > > I'm particularly interested in FPGA implementations of the filters, rather > than software. > > regards, > > Paul Teagle > CAE Electronics -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.comArticle: 30677
If your design is only making 10Mhz, you haven't done anything to target the design to the FPGA structure. As a first step, check to make sure you are using timing constraints. If not, the place and route tools are not trying hard enough. Beyond that, your design still has lots of room for improvement. You should try to tailor the design toward the 4 input look-up structure of the FPGA and use the registers as much as possible (pipeline the design where practical). Go into the timing analysis tools to determine where your worst case paths are, then start working on the design to eliminate those paths. Helen wrote: > > HI My design targeted at 50Mhz > however I could only get 10MHz > Is there any way to improve the maxium frequency? > Thanks a lot! -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.comArticle: 30678
hi, I was wondering if someone knew about companies that sell FPGA
prototyping kits for dynamically reconfigurable FPGAs (preferably XILINX
since our students are using the XESS XS40).
Also are there companies that develops kits for Atmel FPSLIC that
combines
FPGA with a microcontroller.
I would really appreciate your comments and experience in this field
PS: We would like to use the platforms to map Neural Net Algorithms
on the FPGAs
You can email me directly at sareibi@uoguelph.ca
Shawki
--
Shawki Areibi
Assistant Professor
School of Engineering
University of Guelph
Guelph, Ont, Canada N1G 2W1
Tel: (519) 824-4120
Fax: (519) 836-0227
Article: 30679Rick, The 100 ohms is there because the clamp diodes are left ON at all times to protect the output transistors. Reducing the value forces more current into the Vcco through the forward biased clamp diodes, and may cause the device's Vcco to rise beyond the 3.3 Vdc it is supposed to be at. This assumes your 5 V drives actually drives to 5 V. I would first look up the drive characteristic of the 5 V parts, and model them with their IBIS model (hopefully they are so old they don't have that problem). Based on the 100 ohms and the voltage drop across it, you may safely reduce the 100 ohms if the current is less than the 10 mA that we are looking at in the "pull all the way to 5 Vdc" case. Austin Rick Filipkiewicz wrote: > I'm in a situation where we have an ASIC on the motherboard which can be > replaced, for IP development purposes, by an FPGA on a plug-in module. > > Unfortunately the module was thought of in the Virtex days, pre -E, & > there isn't a whole lot of room inside the connector ring to put ranks > of QuickQwitch level converters for the external 5V PCI & IO busses. > > The data sheet says that 5V tolerance can be re-gained with a 100R > series res. I assume its to reduce current through the clamp diode. > > Does this work o.k. ? > > Is 100 a voodoo value that can be made smaller ?Article: 30680
Hi; WinCUPL is still alive. Logical Devices had just recently got it's ability to resale it back. I've just ordered 3 updated licenses/software media from them. -Bob Russell Shaw wrote: > > Hi, > > I can't seem to find a site that sells wincupl. Is it still supported? > > -- > ___ ___ > / /\ / /\ > / /__\ / /\/\ > /__/ / Russell Shaw, B.Eng, M.Eng(Research) /__/\/\/ > \ \ / Victoria, Australia, Down-Under \ \/\/ > \__\/ \__\/Article: 30681
I want to implement mixers, filters, and nco's in an FPGA for decoding QPSK signals and clock recovery. Would anyone direct me to some good books and sources for such implementations ? Thanks.Article: 30682
> > -The 32-bit phase accumulator can be fully pipelined by making it a group of > > 32 half adders, with the carries pipelined from one to the next. Then you > > need to delay the lower bits to match them with the upper bits; you can use > > the SRLs for this. This is bigger, but faster. Consider using bresenhams line algorithm instead of plain phase accumulation. This way you get rid of rounding error accumulation. If you take this into account you might be able to do this part with less than 32 Bit at equal quality. Furthermore: A non CORDIC way to build a sine oscillator is to both store the current sine and cosine value. One gives you the increment for the other, if multiplied with a constant. (Sine is the derivative of Cosine, and vice versa) This means that for a fixed freuqency you need two constant coefficient multipliers. For some constants these will be much smaller than the CORDIC solution. But not for all constants. Kolja SulimmaArticle: 30683
Hi Have anyone ever used Carry logic in the FPGA, I read some datasheet it is said"The fast carry logic can be accessed by placing special library symbols, or by using Xilinx Relationally placed Macros(RPMs) that already include these symbols. Can anyone tell me how to use those in Xilinx Foundation 3.li? Thanks a lotArticle: 30684
Thank you very much for your helps. Bob I did not try your design yet I just tried some module in the LogiBox, however the maxium frequency I could reach is only 45MhzArticle: 30685
Is there an app note or more in depth description of all the information given in the PAR timing.dly file written by Xilinx Foundation. I've looked at one for my project and although many nets seem to make sense there are a number which seem to have a driver with multiple (10-20) nodes that don't seem to be related to the driving net given. Thanks in advance, ChuckArticle: 30686
THe macros use the fast carry logic (see your previous post in this thread). The problem is most likely that you have a long combinatorial path leading to the controls for your counter, perhaps a big decode or something. The delay of the carry chain is added to any combinatorial logic in front of the counter fucntion. Try simplifying or pipelining your controls. You also don't mention the width (number of bits) of your counter. Finally, for maximum clock rate, the registers driving the counter's carry chain logic should be placed (by floorplanning) immediately adjacent to the counter, and if you are really pushing it, duplicated to reduce the fanout into the carry chain logic. For duplicating the controls, you'll have to roll your own macro. The primitives to use depend on the FPGA family. In the case of VIrtex, the carry chain is comprised of MUXCY's and XORCY's. Refer to the drawing of the slice structure in the databook to understand how these are connected. Inferring them depends on your design entry. For schematics it is just a matter of connecting the symbols. For HDLs, you essentially write a textual netlist describing how they get connected. Helen wrote: > > Thank you very much for your helps. > Bob I did not try your design yet > I just tried some module in the LogiBox, however the maxium frequency I could reach is only 45Mhz -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.comArticle: 30687
Hi,
Could someone explain to me what is the differences between Engineering
Spec, System Spec, or Architectural Spec in ASIC/FPGA related designs.
In particular, I would like to know how detail is the system spec
supposed to be in terms of the HW implementation of the design.
Thanks
Joseph
Article: 30688CICs are not very practical for interpolating or decimating by less than about the 4-8 samples range. Unfortunately there are not really simpler or faster alternatives the CIC is about as fast and simple as it gets. If a FIR filter is unfeasible you could try an IIR filter for roughly the same magnitude response with less area. "Ray Andraka" <ray@andraka.com> wrote in message news:3AE43603.9B830121@andraka.com... > The CIC's response curve is sinx/x, which is to say it is not shaped very > nicely. Typically the CIC is cascaded with a shaping filter that a) limits the > signal passband to a fraction of the CIC's first null and b) flattens the > response in the passband. That shaping filter can be (and typically is) made > into an interpolating or decimating filter using polyphase techniques. For low > interpolation or decimation ratios, using a CIC brings little to the party. > > Also, one of the values of the CIC is that for higher decimation ratios (above > about 16), the shape of the CIC filter referenced to the output sample rate is > for all practical purposes constant, so the shaping filter does not have to be > reprogrammed when the decimation/interpolation ratio is changed. At low CIC > ratios, the changes in the curve shape are more pronounced, so the shaping > filter also needs to be updated for a constant composite response. > > Paul Teagle wrote: > > > > Hi, > > > > I'm wondering why many of the newer (dedicated or FPGA) filter or > > upconversion devices have CIC interpolators/filters, with a lower limit on > > the amount of interpolation available, eg, many have a minimum interpolation > > of 8. For an interpolation value say of 3, with a low pass response, are > > there better (faster or more silicon-area efficient) ways to achieve this > > than CIC ? > > > > I'm particularly interested in FPGA implementations of the filters, rather > > than software. > > > > regards, > > > > Paul Teagle > > CAE Electronics > > -- > -Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email ray@andraka.com > http://www.andraka.com >Article: 30689
I have done this with a Xilinx SpartanXL (100-pin). I designed a device that fit into a compact flash card. I did the whole electronic design and VHDL implementation using a book from Amazon and the Compact Flash spec (FREE) from http://www.compactflash.org. The book was The PCMCIA Bible or Guide or something like that. The author was Michael Mora. When you get ready to fab the PCB, try a company called Electrotek. The did a great job with my 6-layer 0.018" boards. "Dan" <daniel.deconinck@sympatico.ca> wrote in message news:LQJC6.584388$Pm2.9563823@news20.bellglobal.com... > Hello, > > I would like to design a PCMCIA card. > > I have been to www.pcmcia.org The spec is very expensive. > > Is there any online information that would help me design a PCMCIA card? > > > Sincerely > Dan > > >Article: 30690
> I want to implement mixers, filters, and nco's in an FPGA for > decoding QPSK signals and clock recovery. > Would anyone direct me to some good books and sources > for such implementations ? I assume you understand the basic theory/math behind what you are doing? If so, then I assume you're just looking for FPGA coding/implementation tips, in which case you could probably just glean Xilinx's and Altera's designer/application notes to get a feel for what FPGA/CPLDs are good at (and what they're not so good at.) If you want more specific help, then you might want to tell us what you have in mind. For example, how fast the FPGA will be clocked, the RF input frequency, symbol rate, phase precision, etc.Article: 30691
Hi Helen If You use Schematics then place a MUXCY in the sheet. Best regards IvarArticle: 30692
Having done the old Altera vs Xilinx comparison a number of times before, the consensus seemed to be that the Xilinx architecture was better for artihmetic operations. The new Altera family, Mercury, seems to have a somewhat different structure to the previous Flex and Apex families, and still different to the Xilinx structure. Anyone like to comment one whether they reckon its better, worse or just different? Also, anyone think we might get more response from Altera (and less from Xilinx?) is this ng was called comp.arch.pld :-)?Article: 30693
martin.j.thompson@trw.com wrote: > Also, anyone think we might get more response from Altera > (and less from Xilinx?) is this ng was called comp.arch.pld :-)? I've had private emails from Altera support answering questions I've asked on this newsgroup. Apparently it's company policy not to post which I think is bloody ridiculous. Nial.Article: 30694
On Mon, 23 Apr 2001 23:35:56 -0800, ivar <ivar@stantech.dk> wrote: >Hi Helen >If You use Schematics then place a MUXCY in the sheet. Or if you use VHDL, then place a MUXCY in the architecture. ;-) See: http://toolbox.xilinx.com/docsan/3_1i/data/common/lib/chap07/lib07034.htm ---- KeithArticle: 30695
The issue is you normally only want to keep a fraction of the passband between DC and the first null...this region has a sinx/x shape. If you want a flat passband, you need to use an additional filter to cut down and shape the passband. Also, the stopband of a CIC is not very good for reasonable number of sections unless the passband is a relatively small fraction of the first null (meeting this condition folds the passband into the nulls). For low decimation ratios, you lose the advantages of using a CIC, so you get a pretty poor filter. Tony Kirke wrote: > > CICs are not very practical for interpolating or decimating by less than > about the 4-8 samples range. > Unfortunately there are not really simpler or faster alternatives the CIC is > about as fast and simple as it gets. > If a FIR filter is unfeasible you could try an IIR filter for roughly the > same magnitude response with less area. > > "Ray Andraka" <ray@andraka.com> wrote in message > news:3AE43603.9B830121@andraka.com... > > The CIC's response curve is sinx/x, which is to say it is not shaped very > > nicely. Typically the CIC is cascaded with a shaping filter that a) > limits the > > signal passband to a fraction of the CIC's first null and b) flattens the > > response in the passband. That shaping filter can be (and typically is) > made > > into an interpolating or decimating filter using polyphase techniques. > For low > > interpolation or decimation ratios, using a CIC brings little to the > party. > > > > Also, one of the values of the CIC is that for higher decimation ratios > (above > > about 16), the shape of the CIC filter referenced to the output sample > rate is > > for all practical purposes constant, so the shaping filter does not have > to be > > reprogrammed when the decimation/interpolation ratio is changed. At low > CIC > > ratios, the changes in the curve shape are more pronounced, so the shaping > > filter also needs to be updated for a constant composite response. > > > > Paul Teagle wrote: > > > > > > Hi, > > > > > > I'm wondering why many of the newer (dedicated or FPGA) filter or > > > upconversion devices have CIC interpolators/filters, with a lower limit > on > > > the amount of interpolation available, eg, many have a minimum > interpolation > > > of 8. For an interpolation value say of 3, with a low pass response, are > > > there better (faster or more silicon-area efficient) ways to achieve > this > > > than CIC ? > > > > > > I'm particularly interested in FPGA implementations of the filters, > rather > > > than software. > > > > > > regards, > > > > > > Paul Teagle > > > CAE Electronics > > > > -- > > -Ray Andraka, P.E. > > President, the Andraka Consulting Group, Inc. > > 401/884-7930 Fax 401/884-7950 > > email ray@andraka.com > > http://www.andraka.com > > -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.comArticle: 30696
I had tried many mail server, on my Windows NT or Windows 2000 server, my server connect through cable modem which assigned by DHCP server an IP address, my computer installed windows 2000, and I had tried Rockliffe Mailsite, Imail, etc , mail server. my computer is connect through cable modem to internet, ISP use DHCP server to assign an IP address on my computer but got same problem, when I use my own configed mail server to send mail, all message will go to holding, and system event viewer show, no response from any DNS server when searching for domain..." but I got no problem to send and receive email which domain configed under my own DNS(on my NT server). any help will be much appreciated. thanks tsArticle: 30697
Hi,
I'm using the rc1000pp board from celoxica with a virtex 1000 fpga.
Currently I'm trying to configure it using the XHWIF interface instead of
the c libraries that came with the board.
The following c code works:
PP1000SetClockRate(Handle, PP1000_VCLK, 10e6);
PP1000ConfigureFromFile(Handle, "config.bit");
However the following java code does not:
XHWIFwEvents.setClockFrequency(10);
XHWIFcon.loadBitFile("config.bit",0);
xhwif.clockOn();
con.softReset(0);
The problem only seems to occur when the design requires a global reset.
Does anyone know the difference between: PP1000ConfigureFromFile and
XHWIFcon.loadBitFile ?
Thanks,
Viv
Article: 30698--------------B743596690021C9F8F1958E9 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit For Digital Processing Fundamentals: "Modern Quadrature Amplitude Modulation" Principles and Applications for Fixed and Wireless Channels, W.T. Webb and L Hanzo "Principles of Digital Transmission, With Wireless Applications" Sergio Benedetto and Ezio Biglieri "Digital Communications" John G. Proakis "Frequency Synthesizers, Theory and Design" Mannassewitch For IP and Cores for FPGA's for your building blocks, see the website http://www.xilinx.com/xlnx/xil_prodcat_systemsolution.jsp?iLanguageID=1&iCountryID=1&ioid=-8281&isiod=-8621&ipoid=19245 One comment on digital solutions for RF & Wireless, is that you will need a good simulation environment. The MatLab simulation tool can now be used to develop IP http://www.xilinx.com/products/logicore/dsp/matlab_final.pdf http://www.xilinx.com/xcell/xl37/xcell37_16.pdf Don't forget to model your system clock jitter, as it directly degrades the sampling, especially if you sample at the IF. Most people use a very low jitter PECL oscillator directly connected to the IF A/D, and also feed the same clock to the FPGA. By doing this, the data are sampled with the least possible uncertainty, and the FPGA can then go about its business in an entirely digital fashion. Austin --------------B743596690021C9F8F1958E9 Content-Type: text/html; charset=us-ascii Content-Transfer-Encoding: 7bit <!doctype html public "-//w3c//dtd html 4.0 transitional//en"> <html> For Digital Processing Fundamentals: <p>"Modern Quadrature Amplitude Modulation" Principles and Applications for Fixed and Wireless Channels, W.T. Webb and L Hanzo <p>"Principles of Digital Transmission, With Wireless Applications" <br>Sergio Benedetto and Ezio Biglieri <p>"Digital Communications" John G. Proakis <p>"Frequency Synthesizers, Theory and Design" Mannassewitch <p>For IP and Cores for FPGA's for your building blocks, see the website <p> <a href="http://www.xilinx.com/xlnx/xil_prodcat_systemsolution.jsp?iLanguageID=1&iCountryID=1&ioid=-8281&isiod=-8621&ipoid=19245">http://www.xilinx.com/xlnx/xil_prodcat_systemsolution.jsp?iLanguageID=1&iCountryID=1&ioid=-8281&isiod=-8621&ipoid=19245</a> <p>One comment on digital solutions for RF & Wireless, is that you will need a good simulation environment. The MatLab simulation tool can now be used to develop IP <p> <a href="http://www.xilinx.com/products/logicore/dsp/matlab_final.pdf">http://www.xilinx.com/products/logicore/dsp/matlab_final.pdf</a> <p> <a href="http://www.xilinx.com/xcell/xl37/xcell37_16.pdf">http://www.xilinx.com/xcell/xl37/xcell37_16.pdf</a> <p>Don't forget to model your system clock jitter, as it directly degrades the sampling, especially if you sample at the IF. Most people use a very low jitter PECL oscillator directly connected to the IF A/D, and also feed the same clock to the FPGA. By doing this, the data are sampled with the least possible uncertainty, and the FPGA can then go about its business in an entirely digital fashion. <p>Austin</html> --------------B743596690021C9F8F1958E9--Article: 30699
I am building a QPSK communication controller using a FPGA. It will contain the QPSK modulation module, QPSK demodulation module, and the MAC module. The MAC is almost finish. The problem areas is the demodulator which requires mixers, nco's, Costas loop for clock recovery. I don't have any clue as how to implement those functions. The rf inputs are baseband I & Q, 8 bits of each, and the bit rate will be 10 Mbits/s. >>On Mon, 23 Apr 2001 22:12:57 -0700, Anonymous Idiot <anonymous_idiot@nowhere.com> wrote: >> I want to implement mixers, filters, and nco's in an FPGA for >> decoding QPSK signals and clock recovery. >> Would anyone direct me to some good books and sources >> for such implementations ? > >I assume you understand the basic theory/math behind what you >are doing? If so, then I assume you're just looking for FPGA >coding/implementation tips, in which case you could probably >just glean Xilinx's and Altera's designer/application notes >to get a feel for what FPGA/CPLDs are good at (and what they're >not so good at.) > >If you want more specific help, then you might want to tell >us what you have in mind. For example, how fast the FPGA >will be clocked, the RF input frequency, symbol rate, >phase precision, etc.
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