Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Yes, nothing at all shows. I didn't touch any jumpers on the board except for M0 and M2. Initially, I was able to program the counter.mcs file that's on the Insight web page, and the LCD would increment. So that proved the hardware was OK. The problem had to be either in the Insight source files, or something to do with my configuration of Webpack. But now, not even their version of counter.mcs will work. I think the hardware died. Of course, it returns "Programming succeeded !". But no. I did find one thing I was doing wrong. When you make the PROM file, it shows a dialog and asks you to pick the PROM type. Initially I was just clicking OK. But it gives the "PC" (PLCC) type as the default, and it's actually the SO20. But fixing that didn't make it work. I think the hardware died at this point. Unfortunately. Jason Berringer wrote: > > "Blank LCD" meaning nothing at all showing? It may sound stupid, but did you > put on all the jumpers on the headers beside the LCD, the lines from the > FPGA are not hardwired to the LCD, they must be jumpered to make it work, > otherwise your process sounds correct. I have the same board and have had no > trouble with it or the code. > > Jason > > "jeff" <jeff@none.com> wrote in message news:3CB3CDC1.5F92@none.com... > > I've been trying to make the counter demo work with > > Insight's $125 Spartan II demo board, but it fails. > > All I get is a blank LCD. It should have incrementing > > numbers. > > > > I got the Verilog source for the counter demo here: > > http://208.129.228.206/solutions/kits/xilinx/spartan-ii.html > > > > I created a project in Webpack 4.2, and it compiled OK. > > > > In the process called "Generate Programming File", I > > opened the property box, and selected CCLK as the startup > > clock. I ran the process, and then went to Generate > > Prom File, and made the counter.mcs file. > > > > Then I went back again, and set the startup to JTAG clock. > > I ran the process, which made a counter.bit file with > > the JTAG clock. I didn't make a prom file, because this > > file is for the Spartan II chip. > > > > (I'm sure I selected the clocks correctly, because if I > > don't the iMPACT program tells me). > > > > After that, I clicked on Configure Device. I have the board > > jumpered for JTAG mode (M1 jmpr on, M0 & M2 off). I clicked > > on Initialize chain, and it shows a 18V01 and a XCV100. > > I assign counter.mcs to the 18V01 and counter.bit to the > > next chip. After I do that, the XCV100 changes to a > > XC2S100. Now I right-click on the 18V01 and tell it > > to program. It succeeds. > > > > Now I unplug power from the board, and re-jumper it for > > Master Serial mode, which is M0,M1,M2 jumpers all on. > > I plug in power, fully expecting the LCD to start incrementing > > but it doesn't. Nothing happens. Can anyone tell me > > what I'm doing wrong ? > > > > > > -----= Posted via Newsfeeds.Com, Uncensored Usenet News =----- > > http://www.newsfeeds.com - The #1 Newsgroup Service in the World! > > -----== Over 80,000 Newsgroups - 16 Different Servers! =----- -----= Posted via Newsfeeds.Com, Uncensored Usenet News =----- http://www.newsfeeds.com - The #1 Newsgroup Service in the World! -----== Over 80,000 Newsgroups - 16 Different Servers! =-----Article: 41926
>We're currently using ChipScope in the lab, to debug some Virtex II >parts. The functionality is impressive, but the speed is somewhat >lacking. When we try to use ChipScope logic in parts running at 125 >MHz, we can't meet timing. Simplifying the trigger conditions helps >somewhat, but not enough. > >Does anyone who's worked with ChipScope have some tips for speeding it >up? Other than not looking at the timing reports, that is... I haven't worked with it. Have you tried making your own trigger condition - a single signal is the ultimate simple condition. Then you get to pipeline and/or floorplan things as much as you need to meet timing. -- These are my opinions, not necessarily my employer's. I hate spam.Article: 41927
Falk Brunner wrote: > > "jeff" <jeff@none.com> schrieb im Newsbeitrag news:3CB3CDC1.5F92@none.com... > > [ trouble with Spartan-II board ] > > At first, your design flow sounds correct. But have you also jumpered the > DIN pin correctly. You can choose between DIN feed by the PROM of serial > download cable. I checked that, and it's jumpered correctly. I also made sure that I configured the PROM file for a serial prom, using MCS format, and for a XC18V01, which is what's on the demo board. > But remember. If you are generating a *.bit file which is later converted to > *.mcs for programming into the FLASH, you need to select CCLK as startup > clock. IMPACT will complain because it finds your *.bit file with a CCLK > startuip clock, but just ignore this. Click Initialize Chain and programm > your *.mcs into the FLASH. JTAG as startup clock is only required (possible) > if you are directly downloading to the FPGA via JTAG. I've got that right. I don't think that was the problem. Not sure at this point. I think the hardware may have died, since even Insight's own COUNTER.MCS file will not work anymore. Maybe I need to buy a new XC18V01 prom and change it out. > > -- > MfG > Falk -----= Posted via Newsfeeds.Com, Uncensored Usenet News =----- http://www.newsfeeds.com - The #1 Newsgroup Service in the World! -----== Over 80,000 Newsgroups - 16 Different Servers! =-----Article: 41928
>I am not sure if this suggestion is going to save your design, but to >get close to 32-bit 33MHz PCI's maximum theoretical bandwidth (133MB/s), >you have to do initiator (bus master) transfers. >If the microprocessor (CPU) is sinking data into your card, you will >only get a fraction (probably 1/4 or 1/5) of the 133MB/s number. It depends upon implementation details. If the CPU merges writes then you can get slightly better performance when the CPU pushes the bits out to the PCI card. You don't have to wait for the bus turnaround or read access delay in the RAM chips. If the CPU/memory system doesn't prefetch the next cache line in a burst, doing reads from a PCI card will be pretty slow. -- These are my opinions, not necessarily my employer's. I hate spam.Article: 41929
Hi,
I have problems when I want to do a post-synthesis pre-place and
route simulation in Modelsim. I have synthetized a VHDL design in a
apex20ke (an FPGA family of Altera), and I have obtained another VHDL
design which is an FPGA-independent netlist ready for place and
route.This post-synthesis design exported from the synthesis tool give
me errors when I simulate it. Should I compile another library in my
work directory,first?Where could I find the entity´s architectures,
wich are instantiated in this vhdl design?
Thanks, a lot.
Itsaso Zuazua
Article: 41930prasadkdnvs@rediffmail.com (K PRASAD) writes: > I am impelmenting dsp algorithms in fpga. > i am new to the field. > this is my first project. > i don't know what would be the gate count of the design before > coding in vhdl for synthesis Think about how many registers you need to store the data in your algorithms. Homann -- Magnus Homann, M.Sc. CS & E d0asta@dtek.chalmers.seArticle: 41931
maxedman3503@yahoo.com (Max Edmand) writes: > Could someone please give a hint how to instantiate built in > multipliers that Xilinx claims are available in Virtex 2000E? The dedicated multipliers are only in Virtex-II (and II Pro). Homann -- Magnus Homann, M.Sc. CS & E d0asta@dtek.chalmers.seArticle: 41932
How can I devide a 18 bit_vector by a 6 bit _vector? I want to do this in VHDL and I use the free webpack. greetz motArticle: 41933
=====================================================================
Workshop on Cryptographic Hardware and Embedded Systems 2002
(CHES 2002)
www.chesworkshop.org
Hotel Sofitel, San Francisco Bay (Redwood City), USA
August 13 - 15, 2002
Third and Final Call for Papers
General Information
The focus of this workshop is on all aspects of cryptographic hardware
and security in embedded systems. The workshop will be a forum of new
results from the research community as well as from the industry. Of
special interest are contributions that describe new methods for
efficient hardware implementations and high-speed software for
embedded systems, e.g., smart cards, microprocessors, DSPs, etc. We
hope that the workshop will help to fill the gap between the
cryptography research community and the application areas of
cryptography. Consequently, we encourage submissions from academia,
industry, and other organizations. All submitted papers will be
reviewed.
This will be the fourth CHES workshop. CHES '99 and CHES 2000 were
held at WPI, and CHES 2001 was held in Paris. The number of
participants has grown to more than 200, with attendees coming from
industry, academia, and government organizations. The topics of CHES
2002 include but are not limited to:
* Computer architectures for public-key and secret-key cryptosystems
* Efficient algorithms for embedded processors
* Reconfigurable computing in cryptography
* Cryptographic processors and co-processors
* Cryptography in wireless applications (mobile phone, LANs, etc.)
* Security in pay-TV systems
* Smart card attacks and architectures
* Tamper resistance on the chip and board level
* True and pseudo random number generators
* Special-purpose hardware for cryptanalysis
* Embedded security
* Device identification
Instructions for Authors
Authors are invited to submit original papers. The preferred
submission form is by electronic mail to
submission@chesworkshop.org. The submissions must be ANANYMOUS, with
no author names, affiliations, acknowledgments, or obvious
references. Papers should be formatted in 12pt type and not exceed 12
pages (not including the title page and the bibliography). Please
submit the paper in Postscript or PDF, together with an extra file
containing the email and physical address of the authors, and an
indication of the corresponding author. We recommend that you generate
the PS or PDF file using LaTeX, however, MS Word is also
acceptable. All submissions will be refereed. Only original research
contributions will be considered. Submissions must not substantially
duplicate work that any of the authors have published elsewhere or
have submitted in parallel to any other conferences or workshops that
have proceedings.
Important Dates
Submission Deadline: May 1st, 2002.
Acceptance Notification: July 1st, 2002.
Final Version due: August 1st, 2002.
Workshop: August 13th - 15th, 2002.
NOTE: The CHES dates August 13th - 15th are the Tuesday through
Thursday preceeding CRYPTO 2002 which starts on the evening of
Sunday, August 18th.
Mailing List
If you want to receive emails with subsequent Call for Papers and
registration information, please send a brief mail to
mailinglist@chesworkshop.org.
Program Committee
Beni Arazi, Ben Gurion University, Israel
Jean-Sebastien Coron, Gemplus Card International, France
Kris Gaj, George Mason University, USA
Craig Gentry, DoCoMo Communications Laboratories, USA
Jim Goodman, Lumic Electronics, Canada
M. Anwar Hasan, University of Waterloo, Canada
David Jablon, Phoenix Technologies, USA
Peter Kornerup, Odense University, Denmark
Pil Joong Lee, Pohang Univ. of Sci. & Tech., Korea
Preda Mihailescu, University of Paderborn, Germany
David Nacchache, Gemplus Card International, France
Bart Preneel, Universite Catholique de Louvain, Belgium
Jean-Jacques Quisquater, Universite Catholique de Louvain, Belgium
Erkay Savas, rTrust Technologies, USA
Joseph Silverman, Brown University and NTRU Cryptosystems, Inc., USA
Jacques Stern, Ecole Normale Superieure, France
Berk Sunar, Worcester Polytechnic Institute, USA
Colin Walter, Computation Department - UMIST, U.K.
Organizational Committee
All correspondence and/or questions should be directed to either of
the Organizational Committee Members:
Burt Kaliski
(Program Chair)
RSA Laboratories
20 Crosby Drive
Bedford, MA 01730, USA
Phone: +1 781 687 7057
Fax: +1 781 687 7213
Email: bkaliski@rsasecurity.com
Cetin Kaya Koc
(Local Organization)
Dept. of Electrical & Computer Engineering
Oregon State University
Corvallis, Oregon 97331, USA
Phone: +1 541 737 4853
Fax: +1 541 737 8377
Email: Koc@ece.orst.edu
Christof Paar
(Publicity Chair)
Electrical Eng. & Information Sciences Dept.
Ruhr-Universitaet Bochum
44780 Bochum, Germany
Phone: +49 234 32 23988
Fax: +49 234 32 14444
Email: cpaar@crypto.ruhr-uni-bochum.de
Workshop Proceedings
The post-proceedings will be published in Springer-Verlag's Lecture
Notes in Computer Science (LNCS) series. In order to be included in
the proceedings, the authors of an accepted paper must guarantee to
present their contribution at the workshop.
Article: 41934People, who may represent topic list for compare ASIC and FPGA for design realization? My interest is highligt a basics features, tips & tricks, specific of FPGA... If it is a old question, give me a href...Article: 41935
"sweir" <weirsp@yahoo.com> wrote: > Paul, why are you comparing a declaration with instantiations? > Personally, I prefer simple names and appropriate comments > in the source code. I listed the function declaration (as opposed to its instantiation) to highlight the fact that my function does not take or return std_logic_vector. I didn't find fnEncBin to be a self descriptive name. Its behavior is like a type converter so I created a new type and chose a name consistent with existing type converters. The instance alone doesn't tell the whole story: o <= fnEncBin(a) ; vs. o <= to_unsigned(a) ; That's a small change but don't forget the declarations: signal a : std_logic_vector(7 downto 0); signal o : std_logic_vector(2 downto 0); vs. signal a : OneHot(7 downto 0); signal o : unsigned(2 downto 0); My version has the usual benefits of compile-time type checking. Comments near the function declaration are great but, unlike function signatures, compilers ignore comments (most of the time). My view is based on the idea that OneHot and unsigned both represent integer values as an array of bits but that their encodings are different. Functions like to_integer(OneHot) and to_OneHot(integer,integer) might also come in handy. Paul.Butler@ni.comArticle: 41936
I'm trying to get to the bottom of my my broken (re)installation. So I know I've got them intact please could somebody (preferably Xilinx) tell me if these MD5 checksums for the installer .exe and .xwp files are ok. This is what I've got a6adf98a144ede655f893a2250ff798d WebPACK_42wp00_b.xwp 18d3014471d35fd4505c9968b8202c84 WebPACK_42wp00_c.xwp 5d02a46338bba5f5646c732bd1d97fd3 WebPACK_42wp00_g.xwp e884ec6ba5752c1d728163eb2654d34a WebPACK_42wp00_installer.exe 79ec535bdbba26a08ffd883b3ec60649 WebPACK_42wp00_j.xwp 0cdefa3f005f8773b450c0c7b2281eb2 WebPACK_42wp00_k.xwp cbcfa0af0df2aed72e28a7c7b7ea1196 WebPACK_42wp00_m.xwp 84be26aab50d4159ca2325c74296ec4d WebPACK_42wp00_o.xwp Cheers, JonArticle: 41937
Hi all, I need to design a special mini version of a HDLC controller for a E1 PCM bus. The HDLC controller shall provide flag recognition, bit stuffing, but no CRC checking is required. What I lack are general infos regarding the timings, and the format on such a E1 PCM bus. Where can I find some useful 'engineering-ready' infos for that topic in order to implement the HDLC controller easily ... Any hint or link is very welcome, thank's`! markusArticle: 41938
Hello, Does anybody knows when the Virtex II pro boards will be available for sale? regards, CyrilleArticle: 41939
Markus, U can find free HDLC controller source code at www.opencores.com along with links on HDLC documentation. -Vikram Markus Meng wrote: > Hi all, > > I need to design a special mini version of a HDLC controller > for a E1 PCM bus. The HDLC controller shall provide flag > recognition, bit stuffing, but no CRC checking is required. > > What I lack are general infos regarding the timings, and the > format on such a E1 PCM bus. Where can I find some useful > 'engineering-ready' infos for that topic in order to implement > the HDLC controller easily ... > > Any hint or link is very welcome, thank's`! > > markusArticle: 41940
Hi all, Well, I've finally taken the plunge and started to play the the Webpack software - and my first attempt has a DCM in it. From the docs I've seen, it would appear that I have to specify the various setup parameters for the DCM in both "attribute" form and "generic" form! Is this really the case in this day and age (and software - Synplify 7.0 and Modelsim 5.5)? Sounds like a recipie for disastrous simulation/synthesis mismatches to me! Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt, Solihull, UK http://www.trw.com/conektArticle: 41941
Hello, I'm planning to buy the Spartan-II T 200 PCI eval kit (DS-KIT-2S200-PAK-EURO) from Insight Electronics, but since a board without a good description and service is no good choice to get started, I'm interested your experience with Insight and especially the demo kit. Additionally, has somebody already tried to implement den PCI core from OpenCores? Will this core work on this board? How does it look like about documentation of the P160 expansion module? Does the kit include some description about it, e. g. infos about timing contraints? I hope to receive a lot of feedback, thanks Martin MCzamai@gmx.netArticle: 41942
I know there is anecdotal evidence of people frying an FPGA by loading illegal configuration patterns - eg when using evolutionary techniques, but does anyone know of any published work on this? Cheers.Article: 41943
Hi all, i'm trying to download a simple code on Spartan II Demo Board (by Insight) via JTAG cable. The problem is that iMPACT detects a xcv100 instead of xc2s100, warns me and if i go ahead and try to program i receive a lot of difference. This is the log (if it can be helpful...): Checking for System Ace MPM device... ---------------------------------------------------------------------- Position PartName Version FileName 1 xc18v01 0 NOT YET ASSIGNED 2 xcv100 3 NOT YET ASSIGNED ---------------------------------------------------------------------- Validating chain... Boundary-scan chain validated successfully. '2': IDCODE is '00110000011000010100000010010011' '2': IDCODE is '30614093' (in hex). Can someone help me to solve ? Thanks a lot, regards -- Stefano Mora email: stefano.mora@*libero.it (remove *)Article: 41944
Hi Martin, I'm afraid so, you still have specify attributes for synthesis and generics for the functional simulation. Cheers, Jonathan Martin Thompson wrote: > Hi all, > > Well, I've finally taken the plunge and started to play the the > Webpack software - and my first attempt has a DCM in it. From the > docs I've seen, it would appear that I have to specify the various > setup parameters for the DCM in both "attribute" form and "generic" > form! > > Is this really the case in this day and age (and software - Synplify > 7.0 and Modelsim 5.5)? Sounds like a recipie for disastrous > simulation/synthesis mismatches to me! > > Cheers, > Martin > > -- > martin.j.thompson@trw.com > TRW Conekt, Solihull, UK > http://www.trw.com/conektArticle: 41945
Hi Herbie, Check out this solution record: http://support.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=8436 Cheers, Jonathan Herbie wrote: > I know there is anecdotal evidence of people frying an FPGA by loading > illegal configuration patterns - eg when using evolutionary techniques, but > does anyone know of any published work on this? > > Cheers.Article: 41946
"jeff" <jeff@none.com> schrieb im Newsbeitrag news:3CB51A2E.1401@none.com... > I've got that right. I don't think that was the problem. Not sure > at this point. I think the hardware may have died, since even Insight's > own COUNTER.MCS file will not work anymore. Maybe I need to buy a new > XC18V01 prom and change it out. Hmm, this is rather unlikely. The borad takes a lo of stress before giving up (bu won wihsand a 48V/4A power supply ;-) Some ime ago, I was working on a projec using Xapp58, JAG download vias a microconroller. I messed up a lot of things, also the PROM. When things go wrong, the board draws a lot of current because the PROM does strange things. Solution. Set the mode pns to serial slave and clear the PROM. Then try to configure the FPGA directly, not by progamming the PROM. -- MfG FalkArticle: 41947
"Frank de Groot" <franciad@online.no> schrieb im Newsbeitrag news:1F2t8.3420$cm1.89947@news4.ulv.nextra.no... > Due to the nature of my application, I am afraid I can't let the FPGA handle > anything else but inner loop stuff. > The rest is horribly complex and typically suited for a regular processor. > But I'll look into it. Maybe you can increase performance by pipelining the algorithm, so that you can feed a (almost) constant data stream into the FPGA, buffer with FIFOs, and read back the results, which are just delayed due to pipelining. -- MfG FalkArticle: 41948
The patent has to do with adding the reconfigurable logic in parallel with the current chip function. Basically a system where you can seem like the device designed for the socket then behave like a fpga the next, take over the system and do what you want. The idea is to build a chip that you could just drop into an existing slot/socket and it would have a built-in reconfigurable subsystem, yet it could do exactly what the original chip was supposed to do. The vision is to take a Pentium out of the socket and be able to plug in a reconfigurable computer (which today would include a Pentium IV, a Virtex II Pro and a custom controller....) As far as patent rights go, a patent only gives you the right to stop someone from selling a product if there is a violation. Steve "Metastabl" <silentmusic@hotmail.com> wrote in message news:d782eac7.0204101645.3a72a66e@posting.google.com... > "Steve Casselman" <sc.nospam@vcc.com> wrote in message news:<_AEs8.1784$2_6.924707050@newssvr14.news.prodigy.com>... > > I hate to keep saying this but it seems people with patents get no respect. > > If you read my patent > > http://www.delphion.com/details?pn=US06178494__ You will see that the > > Pilchard board falls under that patent. I explicitly site Rams of all kinds. > > Remember the patent issued in 2000 I put it in 11/96 and have all of it in > > my note book from 12/94. The people from Honk Kong are doing great work but > > ..... > > > > Steve Casselman, CEO > > Virtual Computer Corporation > > > > > > >invented in Hong Kong, was available for Windows. The Pilchard is a FPGA > > > board that plugs into a DIMM slot. > > So you've patented the idea of hanging a chip off of a memory bus? > There's plenty of prior art for that - and as far as I can tell that's > all that the Pilchard board does. Putting any chip on a memory bus is > obvious to electrical engineers, so what makes your idea non-obvious? > > What about Nuron? Intel bought them, so they have deep pockets. Did > they license your patent? If not then are you suing Intel?Article: 41949
hi,
Does anyone know where to get a complete price list for all the Xilinx's
FPGAs (Virtex 2, Virtex E, Spartan 2 E, etc)? The price list doesn't have
to be accurate 'cause I just want to get an idea which FPGAs I am going to
use in the new design in term of processing power and $$$.
Thanks
Jim
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z