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Or - is your I/O speed at about the device limits? If you're using a 60 MHz sampling rate, for instance, you could use cheap CPLDs to mutiplex four channels into one for a 240MHz sampling stream into 1/4 the pincount !!! Huge difference. Even a 2x change is huge. Use small devices that can support LVDS for multiple channels and you can pump up the speed dramatically in the Virtex-II devices with a fraction of the cost of the XC2V6000. Nicholas Weaver wrote: > In article <a9m9g1$28d$1@helle.btinternet.com>, UK Gary <deton8@aol.com> wrote: > >I need to design something where the FPGA must have about 1000 I/O pins. > >What is my cheapest option? The design must fit into a single FPGA, but > >apart from that and the pin count I don't have any special requirements. > > Why? Could you possibly split the design into 2 or 4 parts, with some > of the parts using high speed dedicated IOs to interconnect them? > Harder design, but it may be MUCH cheaper. > -- > Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 42251
Austin Lesea wrote > Near perfect bypassing is a cap from 0.1uF to 0.01 uF (not much difference) > 604 surface mount, with at least two vis at each end abutting the pads to > the power planes, along with some lo esr tantalums (maybe 1 390 uF or larger) > per IO bank. Maybe better to use 'reverse geometry' caps, such as 0508?Article: 42252
Along with the earlier suggested "set dont_touch" and the likes, you could also drive that output from a register in such a manner that the sythesis tool cannot know that it is a constant and optimize it out. Something like a programmable address register or GPIO register. Regards "William L Hunter Jr" <wlhunterjr@attbi.com> wrote in message news:<ugcv8.237269$Yv2.68162@rwcrnsc54>... > Hi > > I am doing a Virtex-II design using ISE 4.2.01 and FPGA Express 3.6.1. I > have a few pins on my top level entity configured as outputs which are used > to set the address of some external devices. In my architecture, I assign > these outputs a '0'. FPGA express is optimizing out this connection. If I > look at the synthesis optimized schematic viewer the connection to gnd and > output pad are missing. How do you connect outputs to GND in VHDL? I have > always assigned them a '0' in the VHDL and this always worked. Any ideas on > what could be wrong?? > > Thanks in advance > BillArticle: 42253
This is Java JRE on P4. See http://java.sun.com/products/jdk/1.1/jre/download-jre-windows.htmlArticle: 42254
"Reverse geometry" helps but it's just another little part of a very ugly science. It's sad how much "rule of thumb" has propagated through our designs resulting in some pretty ugly results, either in way too much cost for their function (I question the 390uF tantalum, personally) or not enough oomph at certain frequencies. A verrrry expensive tool from one of the big CAD houses can provide better insight into decoupling. One thing that became apparent from the demo is that the single value caps may not help as much as we think. Using .1 and .01uF caps near each other, for instance, can give you a resonance between the resonant frequencies you wouldn't expect. If you want lowest impedance across a wide frequency range it may be more important to have distributed SRF (series resonant frequency) values than it is to have bluk capacitance. The issues addressed in the demo gave a good correspondence to my gut feel from my decoupling and electromagnetics experience and background. The rules of thumb help but there is no golden bullet. We might do better to have a mix of values for our overall capacitance on a per-part basis rather than a per-power/ground pair basis. There are even lower inductance capacitors available (the InterDigitated Capacitors from AVX for instance) but it really comes down to finding the lowest impedance across the frequencies of interest. Tim wrote: > Austin Lesea wrote > > > Near perfect bypassing is a cap from 0.1uF to 0.01 uF (not much difference) > > 604 surface mount, with at least two vis at each end abutting the pads to > > the power planes, along with some lo esr tantalums (maybe 1 390 uF or larger) > > per IO bank. > > Maybe better to use 'reverse geometry' caps, such as 0508?Article: 42255
Greg, I am sorry to hear that you were disappointed in Programmable World 2002. Within Xilinx, I am known to be the harshest critic of marketing BS in public seminars, and I have ( successfully?) fought for more and more technical "meat". Originally, I had been concerned about PW2002, therefore I attended in San Jose. And I came away excited, happy, and even proud. The world has changed since the late 'eighties. Then we were a little-known company, and had to tell the audience about all those neat features, from LUTs and carry chains through LUT-RAMs and SRL16s, to the on-chip termination resistors, and about many generations of software fixes and improvements. Now, there are many new avenues to transmit information, from CDs to the Web, to this newsgroup. We are already known and respected in the engineering community, and most designers know that we have great features, usually better thought-out than those of the competition. Having won the attention, and perhaps even the hearts and minds of most design engineers, we now face a new challenge: We have to convince engineering and corporate management to change their mindset, to adopt multi-gigabit transceivers and on-chip PowerPC for their next-generation designs. Or to give up on ASICs. And in the larger companies, such decisions are usually not made at the design engineer's level. So we have to sell our capabilities higher up the corporate ladder. FPGAs are not glue-logic anymore, they are now part of high-impact architectural, system-level, and business decisions. So we have to change the tone of our story, to appeal to a new audience. We still have lots of detailed technical info, app notes, cores, books and CDs and also training sessions and FAEs, ready to explore the finer details; and many of these details are really utilized by the software automatically. So, please, keep coming to our Seminars and Events, but also use all the other ways to inform yourself about Xilinx products and solutions. The era of FPGAs has just begun... BTW, we just finished a great quarter, increasing our sales 20% quarter-to-quarter, thanks to satisfied customers, like the ones in this newsgroup. We weathered the storm without any lay-offs, just with belt-tightening. That's something to be proud of, and thankful to you, our customers. Peter Alfke ================================= Greg Neff wrote: > Yesterday I attended PW2002 in Toronto. I have attended Xilinx > promotional seminars since the days of the XC2000. Until now, I have > found that the Xilinx seminars provided enough technical information > to make the marketing content tolerable. PW2002 was a radical shift > toward marketing glitz, at the expense of useful technical content. > > <snip> > > Apparently, this seminar was not targeted at engineers. I'll keep > that in mind the next time I get an invite to a Xilinx seminar. > > =================================== > Greg Neff > VP Engineering > *Microsym* Computers Inc. > greg@guesswhichwordgoeshere.comArticle: 42256
John, We have done, and are doing, some pretty extensive tests of this common wisdom (which may be neither wise, nor common). So far, mixing up the caps to prevent resonances isn't nearly as helpful as minimizing L to begin with. A bad bypass layout is not improved by chosing various cap values. A really good bypass layout is slightly improved by chossing Jo (caps at resonance) with the main frequencies in use (1st, 3rd, 5th harmonics). The reverse geometry is better, and the inter-digitated caps are even better. Austin John_H wrote: > "Reverse geometry" helps but it's just another little part of a very ugly science. > It's sad how much "rule of thumb" has propagated through our designs resulting in > some pretty ugly results, either in way too much cost for their function (I > question the 390uF tantalum, personally) or not enough oomph at certain > frequencies. > > A verrrry expensive tool from one of the big CAD houses can provide better insight > into decoupling. One thing that became apparent from the demo is that the single > value caps may not help as much as we think. Using .1 and .01uF caps near each > other, for instance, can give you a resonance between the resonant frequencies you > wouldn't expect. If you want lowest impedance across a wide frequency range it may > be more important to have distributed SRF (series resonant frequency) values than > it is to have bluk capacitance. > > The issues addressed in the demo gave a good correspondence to my gut feel from my > decoupling and electromagnetics experience and background. > > The rules of thumb help but there is no golden bullet. We might do better to have > a mix of values for our overall capacitance on a per-part basis rather than a > per-power/ground pair basis. > > There are even lower inductance capacitors available (the InterDigitated Capacitors > from AVX for instance) but it really comes down to finding the lowest impedance > across the frequencies of interest. > > Tim wrote: > > > Austin Lesea wrote > > > > > Near perfect bypassing is a cap from 0.1uF to 0.01 uF (not much difference) > > > 604 surface mount, with at least two vis at each end abutting the pads to > > > the power planes, along with some lo esr tantalums (maybe 1 390 uF or larger) > > > per IO bank. > > > > Maybe better to use 'reverse geometry' caps, such as 0508?Article: 42258
In article <3CBF331E.4BA38EE5@xilinx.com>, Austin Lesea <austin.lesea@xilinx.com> wrote: >Don't forget about the EasyPath program: up to 70% off for a part that does >exactly what you want it to do. Ahh, NIFTY. :) There has always been idle talk in the past about Xilinx doing that, but it's nice to see it finely. And it makes sense too, there are probably LARGE clases of errors which can be mapped around for a specific design. >I will say that in 12" fab, in a few months, the yield will be much improved >(from whatever it is today - 'good' or 'bad' - do not assume anything, as it >is nothing but idle speculation, or unfounded rumors from disgruntled >competitors). But of course. >Intel already announced that fab in 12" resulted in better gross margins. No >secret here. Not suprising, actually. So much of the costs is per wafer, not per die, that 12" wafers help. And since defects tend to be with the square of the die size, process shrinking is SUCH a win. -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 42259
I fixed it today. I replaced the XC2S100 with a XC2S50,
and all of a sudden, I was able to download a file to it
and it ran ! Then I replaced the XC18V01 and now I could
download an mcs file to it, and it ran. Finally it works
just like it should have, on Day One. (This is with the
counter demo, from Insight's web page).
Because I changed from an XC2S100 to a 50, I had to change
the device and recompile everything. I didn't change
anything else. I have no idea how the original chips died,
since the only jumpers I ever changed were M0 and M2, to
go between JTAG mode and Master Serial mode on the FPGA.
You know, this $125 board from Insight cost me a heck of
lot more than that, in my time. If anyone else wants to
buy one from Insight, I would recommend that you get the
board without an FPGA installed (that's an option), and
put one in yourself. Then at least you know you've
probably got a good one. And you should buy some extra
SPROMs as well.
For anyone who does this, here are a few notes that they
don't tell you about. (Though they are in various Xilinx
appnotes). I'm assuming you're using the Xilinx Webpack.
1. Right-click on the process called "Generate Programming
File". Set the startup clock to CCLK. Now run the
process. Then click on Generate Prom File. Set the
Prom properties to Single Prom, Serial, XC18V01, MCS-86,
checksum FF, and save those as the Default. Then
click on File -- Create Prom. Save it as counter.mcs.
Now you have created the Prom file (.mcs) with the
proper clock (CCLK). Close the window.
2. Now right-click on "Generate Programming File" again,
and go to Properties again, and then Startup Options,
and change the Startup Clock to JTAG Clock. Now
right-click on "Generate Programming File" and select
run. Now you have created counter.bit with a JTAG clock.
This file is for the FPGA.
3. Now DON'T click on Generate PROM File. Click on
"Configure Device" and tell it to Initialize Chain.
It should find the XC18V01 and the FPGA. It will prompt
you to assign a file to each. Assign counter.mcs to
the XC18V01 and counter.bit to the FPGA. Then right-click
on whichever chip you wish to program, and program it.
(The mode jumpers should be in JTAG mode, if you wish to
program the FPGA -- M0 & M2 off, M1 on). If you program
the FPGA, then the LCD should start counting immediately.
If you program the XC18V01, you'll need to shut off the
power, and put the jumpers back into Master Serial mode
(M0,M1,M2 all on), then re-apply power and the LCD should
start counting. When you program the XC18V01, I think all
the default options are OK. You don't need to select
"D4 = CF" -- at least I didn't, and it worked OK.
---
Brendan Bridgford wrote:
>
> Jeff,
>
> My suggestion would be to start debugging the problem by programming the
> FPGA through the JTAG chain. Don't worry about programming the part
> from the PROM at this point.
>
> -Generate the .bit file with startup clock set for JTAG Clock and
> readback/reconfiguration enabled, as you mentioned.
> -Set the Mode pins for Boundary Scan mode
> -Launch iMPACT and initialize the chain. The Spartan-II will appear as
> a Virtex because they use the same IDCODEs.
> -You can assign the $xilinx\xc18v00\data\xc18v01.bsd file (BSDL file) to
> the PROM instead of a .mcs file for the purpose of bypassing the PROM.
> -Assign the .bit file to the Spartan-II as you did before
> -Right-click on the Spartan-II and program it.
>
> At this point, the critical question is whether or not the DONE pin went
> high. If it did, configuration was successful, and the problem is
> somehow related to the design or your board setup. Make sure that your
> oscillator is hooked up and oscillating, and make sure that any enable
> signals are correctly driven. Check your design.pad file (the PAD
> report) and make sure that design clock input is locked to the correct
> pin, and that the LED outputs are locked to the correct pins.
>
> Hope this helps!
>
> --Brendan
>
> jeff wrote:
>
> > I've been trying to make the counter demo work with
> > Insight's $125 Spartan II demo board, but it fails.
> > All I get is a blank LCD. It should have incrementing
> > numbers.
> >
> > I got the Verilog source for the counter demo here:
> > http://208.129.228.206/solutions/kits/xilinx/spartan-ii.html
> >
> > I created a project in Webpack 4.2, and it compiled OK.
> >
> > In the process called "Generate Programming File", I
> > opened the property box, and selected CCLK as the startup
> > clock. I ran the process, and then went to Generate
> > Prom File, and made the counter.mcs file.
> >
> > Then I went back again, and set the startup to JTAG clock.
> > I ran the process, which made a counter.bit file with
> > the JTAG clock. I didn't make a prom file, because this
> > file is for the Spartan II chip.
> >
> > (I'm sure I selected the clocks correctly, because if I
> > don't the iMPACT program tells me).
> >
> > After that, I clicked on Configure Device. I have the board
> > jumpered for JTAG mode (M1 jmpr on, M0 & M2 off). I clicked
> > on Initialize chain, and it shows a 18V01 and a XCV100.
> > I assign counter.mcs to the 18V01 and counter.bit to the
> > next chip. After I do that, the XCV100 changes to a
> > XC2S100. Now I right-click on the 18V01 and tell it
> > to program. It succeeds.
> >
> > Now I unplug power from the board, and re-jumper it for
> > Master Serial mode, which is M0,M1,M2 jumpers all on.
> > I plug in power, fully expecting the LCD to start incrementing
> > but it doesn't. Nothing happens. Can anyone tell me
> > what I'm doing wrong ?
> >
> > -----= Posted via Newsfeeds.Com, Uncensored Usenet News =-----
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Article: 42260I think there might be some funny business with the way you have the DLL hooked up. Here's the way I think it should be hooked done: xtal enters fpga on some pin, logic divides clock down to correct frequency. Drive new clock off chip to run external logic. On the PCB route the clock from the FPGA to the other chip(s) using this clock and then back to an input on FPGA, call this input pin clk_in. This should be one of the special clock input pins on the FPGA. Use a DLL with clk_in hooked up to the CLKIN pin of the DLL, the output of the DLL drives a global buffer which drives the on-chip clock signals. The output of the global buffer also hooks up to the CLKFB pin of the DLL. The on-chip clock that drives the IOB's and such should be very closely aligned with the clock driving the other chips on the board, better than 100ps. The input flip-flops in the IOBs have a delay by default (virtexE I think, virtex2 for sure), this corrects for any negative hold time. This should work up to the highests speeds of the part. Opps, having written this whole thing, it sounds like your clock is 5MHz. I think the min speed for the DLL to lockup properly is 10MHz. Hmm... jeff "Falk Brunner" <Falk.Brunner@gmx.de> wrote in message news:<a9mt8d$4jldq$2@ID-84877.news.dfncis.de>... > Hello everyone, > > Iam afraid Iam missing a major point in FPGA clock routing. > I have a Virtex-E (300), feed a clock from a Xtal (36 MHz) into a global > clock input, divide it down by 8 by means of a DLL and provide this clock to > a clock buffer. A big part of my design runs at this ~5Mhz clock. So far, so > good. But now comes the tricky part. I have some block which handles a > interface with another device (its a UTOPIA2). All output signals use IO > FFs. The clock is simply routed to an IO pin and from there to the other > chip. The interface is fully synchronous, everything works on the rising > edge. > I expected, that the datas are slightly delayed behing the clock, by the > clock-2-output time of the IOB FF, but they were NOT!!!! > The clock IS delayed by ~3 ns behind the data!!!! > First question, how does this happen? I thougt the clock nets are low skew, > means the clock arrives at all cell at the same time. But the P&R tools tell > me, that the clock is driving non-clock load, which can cause skew trouble > (and it does :-( > Second, what is the clean approach for clock distribution (without DLL > usage) > At the moment, I use a registers clocked on the other (falling) edge to > "simulate" the right phase relation between clock and data.Article: 42261
jeff wrote:
>
> I fixed it today. I replaced the XC2S100 with a XC2S50,
> and all of a sudden, I was able to download a file to it
> and it ran ! Then I replaced the XC18V01 and now I could
> download an mcs file to it, and it ran. Finally it works
> just like it should have, on Day One. (This is with the
> counter demo, from Insight's web page).
>
> Because I changed from an XC2S100 to a 50, I had to change
> the device and recompile everything. I didn't change
> anything else. I have no idea how the original chips died,
> since the only jumpers I ever changed were M0 and M2, to
> go between JTAG mode and Master Serial mode on the FPGA.
>
> You know, this $125 board from Insight cost me a heck of
> lot more than that, in my time. If anyone else wants to
> buy one from Insight, I would recommend that you get the
> board without an FPGA installed (that's an option), and
> put one in yourself. Then at least you know you've
> probably got a good one. And you should buy some extra
> SPROMs as well.
>
I recently programmed my Insight Electronics Spartan-II PCI card
through ISE WebPACK 4.2's iMPACT, but at least I didn't have the
problems you encountered.
Because I was using iMPACT for the first time (I have used WebPACK
3.3WP8.0's programmer in the past, and I haven't burned a Configuration
PROM for 8 months.), I wasn't too familiar with it, so when iMPACT
warned me that the .bit file's Startup Clock wasn't JTAG's clock (Very
misleading if the user only wants to program the Configuration PROM.), I
just simply listened to it, and regenerated a .bit file and a .mcs file
with JTAG's clock as the Startup Clock.
I burned only the Spratan-II PCI card's XC18V01-VQ44 Configuration PROM,
and put my card into another computer, but the card didn't function at
all.
After about 10 minutes of troubleshooting, I realized that I shouldn't
use JTAG's clock for configuring the Spartan-II, so I regenerated the
.bit file and .mcs file again this time with Configuration PROM's
internal clock (CCLK) as the Startup Clock.
When I burned the Configuration PROM again, and put the card into the
same computer, the card worked perfectly fine.
Anyhow, unlike you, when I configured the card, I always kept the
configuration mode to Master-Serial mode, and I never configured the
FPGA directly.
I feel sorry that you had to go through what you described, but
I don't agree with you that users should buy the board only with the
FPGA.
I don't know how you did it, but I don't have the skill, the equipment,
or the money to solder a PQFP package, and I believe most people don't,
so I think it is more desirable for most users to buy a board with all
the QFP chips already mounted.
It might be possible that the board might have been DOA, or you could
have zapped the chip accidentally if you didn't properly ground yourself
when working with your board.
Anyway, was it possible to return the board for a new one?
Kevin Brace (In general, don't respond to me directly, and respond
within the newsgroup.)
Article: 42262Kevin Brace wrote: (snip) > I feel sorry that you had to go through what you described, but > I don't agree with you that users should buy the board only with the > FPGA. > I don't know how you did it, but I don't have the skill, the equipment, > or the money to solder a PQFP package, and I believe most people don't, > so I think it is more desirable for most users to buy a board with all > the QFP chips already mounted. I used Chip Quik to pull it. That stuff works great. Digikey has it now. p/n SMD1-ND. http://www.digikey.com/ It leaves a mess on the board, but you can wipe it up with a cotton swab and alcohol. I used a soldering iron with a mini-wave tip (Pace) to install it. It wasn't easy, since it was my first time, but I did do it. (Hint: use plenty of flux, and more flux). I agree it's not for everyone. If I had a staff of techs to do it, I would have gladly given it to them. > It might be possible that the board might have been DOA, or you could > have zapped the chip accidentally if you didn't properly ground yourself > when working with your board. It's possible, but that's never happened to me with any other board. > Anyway, was it possible to return the board for a new one? Since I made it work, I'm keeping it now. -----= Posted via Newsfeeds.Com, Uncensored Usenet News =----- http://www.newsfeeds.com - The #1 Newsgroup Service in the World! -----== Over 80,000 Newsgroups - 16 Different Servers! =-----Article: 42263
"Falk Brunner" <Falk.Brunner@gmx.de> wrote in message news:<a9mt8d$4jldq$2@ID-84877.news.dfncis.de>... > Hello everyone, > > Iam afraid Iam missing a major point in FPGA clock routing. > I have a Virtex-E (300), feed a clock from a Xtal (36 MHz) into a global > clock input, divide it down by 8 by means of a DLL and provide this clock to > a clock buffer. A big part of my design runs at this ~5Mhz clock. So far, so > good. But now comes the tricky part. I have some block which handles a > interface with another device (its a UTOPIA2). All output signals use IO > FFs. The clock is simply routed to an IO pin and from there to the other > chip. The interface is fully synchronous, everything works on the rising > edge. > I expected, that the datas are slightly delayed behing the clock, by the > clock-2-output time of the IOB FF, but they were NOT!!!! > The clock IS delayed by ~3 ns behind the data!!!! > First question, how does this happen? I thougt the clock nets are low skew, > means the clock arrives at all cell at the same time. But the P&R tools tell > me, that the clock is driving non-clock load, which can cause skew trouble > (and it does :-( > Second, what is the clean approach for clock distribution (without DLL > usage) > At the moment, I use a registers clocked on the other (falling) edge to > "simulate" the right phase relation between clock and data. This is probably because the clock has to be routed from the global clock net to the IOB using normal routing thus delaying the clock at the pad. One thing I do in Virtex devices is to use DDRIOBs to generate clocks off-chip. This gives a very low skew between the clock and data off chip. This might not help you since you want the clock edge before the data. Here is an idea I just got: What if you used a DDRIOB to generate the clock on a clock input pin and used that clock to drive a global clock net used to clock your data out. This should give some delay, but I can't remember if it is possible to do in a Virtex-E (I am pretty sure you can do it in a Virtex-II). You could ofcourse use a normal output pin and route (on the PCB) the clock back to a clock input pin. Well, enough ramblings for now. Søren A.MøllerArticle: 42264
Alan Fitch <alan.fitch@doulos.com> wrote in message news:<Q9PxaJAurpt8YBYz@doulos.co.uk>... > In article <22f10f27.0204111935.2d488e51@posting.google.com>, K PRASAD > <prasadkdnvs@rediffmail.com> writes > >hello > >i am new to vhdl and digital design. > >if we just observe the following code > > > >case1) > > > > p1 : process > > begin > > if clk'event and clk ='1' then > > for i in 0 to 9 loop > > result <= mul1 * mul2; -- mul1 and mul2 and result are defined > > --as signals earlier > > end loop; > > end p1; > > > >case2) p1 : process > > variable result; > > begin > > if clk'event and clk ='1' then > > for i in 0 to 9 loop > > result := mul1 * mul2; -- unlike in case1 ONLY mul1 and mul2 > > -- are defined as signals > > end loop; > > end p1; > > > > so if we observe the two codes the loop will be executed in just one clock > > cycle in case2 whereas in case1 only for one i(loop index) it will be executed. > > i think i am clearing in saying this. > > now my doubt is > > > > if we synthesise both the codes what makes the difference? > > > > also should i need to initialise any counter in case1 and get the > > functionality as in case2? > > how should we interpret the result of the synthesis? > > also if i use only variables in my modelling > > then will it be synthesized accurately? > > > >can anyone help me. > >thank u > >prasad. > > The "trick" with loops is to "unroll" the loop. > > So instead of for i in 0 to 9 loop, think of it as > > case1) > > result <= mul1 * mul2; -- i = 0 > result <= mul1 * mul2; > result <= mul1 * mul2; > result <= mul1 * mul2; > result <= mul1 * mul2; > result <= mul1 * mul2; > result <= mul1 * mul2; > result <= mul1 * mul2; > result <= mul1 * mul2; > result <= mul1 * mul2; -- i =9 > > Now you have made 10 assignments to the same signal, but NO TIME HAS > PASSED - all assignments schedule events 1 delta cycle in the future. > Then, because of the way signals work, each later assignment cancels the > previous assignment - so the code is equivalent to writing > > result <= mul1 * mul2; > > Note this is because you are in a process, and statements execute > sequentially in a process. > > On our courses, we call this "last assignment wins", i.e. when making > multiple assignments to a signal in a process all in the same delta > cycle. > > Finally, because you are making a signal assignment in a clocked > process, result will become a set of flip-flops. > > case2) > > result := mul1 * mul2; -- i = 0 > result := mul1 * mul2; > result := mul1 * mul2; > result := mul1 * mul2; > result := mul1 * mul2; > result := mul1 * mul2; > result := mul1 * mul2; > result := mul1 * mul2; > result := mul1 * mul2; > result := mul1 * mul2; -- i =9 > > In this case, result updates straight away because it is a variable. > > By the end of the loop, result contains mul1 * mul2. > > However this time, nothing will happen. Why? Because you have not > assigned result to a signal, and variables are local to the process. So > result cannot be seen outside the process, hence the synthesis tool > should optimise it away. > > > For synthesis of signals in a clocked process : > > In clocked processes a signal assignment results in flip-flops > > For synthesis of variables in a clocked process : > > In a clocked process, if you read a variable value then assign it, > you get a flip-flop. > > In a clocked process, if you assign a variable then read it, you get > a piece of wire. > > > > In your example above, you get a piece of wire, but then it is not seen > outside the process so it gets optimised to nothing. > > > Regarding your questions, neither example is a counter, if I've > understood you correctly. > > And yes, you can use variables as long as you understand the rules > above, and remember to copy its value into a signal if you want to see > it outside the process. > > I hope this helps, > > Alan > > > hai ALAN thank u very much now what about the timing issues how many clock cycles will they require for the two loops.As u said if i assign the variable to a signal to view it outside the process,then how will the synthesizer implement the variable and optimise it? can the multiplication takes place (for the ten times) in the single clock.?how will the multiplication takes place for ten times as mulitplier itself will take one clock cycle for a single mulitplication?how will it be synthesized. i think i am clear to u? regards kprasad > --Article: 42265
Hi there, I have a new project starting ; that's a new board to design with a Virtex-II FG456-XC2V1000. It is meant to work quite fast (200 MHz) ; I did an estimation of the power required by the Core. I can't really get the 1.5 Volts from a linear regulator without using a big heat sink. I would like to do the power supply around a synchronous switcher. It's got an efficiency of around 85% and generates ripples on the output lines of 10mV. Could the ripples affect the stability of the Virtex-II ? Thanks for your help. Philippe.Article: 42266
Hello all, I use a Virtex-E for my design. I have an external clock 155MHz that I pass through a CLKDLLE to acquire the divide by 2 clock. The timing analyzer reports no timing errors but when I timing simulate the design in modelsim (5.2) I get large clock skew between the DLL clocks. The CLK0 rising edge is delayed about 4.2 ns (clock race) with respect of the CLKIN clock!! This clk0 signal is the input of a BUFG whose output is the CLKFB of the CLKDLLE. The external 155 clock uses a LVDS_DLL pin... (should I use the inverted signal for feedback?) The clock divided by two is delayed for less than 1 ns.. Is this a simulation error or an implementation error? Any help is very very wellcome! Best Regards, HarrisArticle: 42267
note for the above post...in the timing simulation I use the sdf file. Xilinx suggests not to use it to see if the DLL work correctly.. if I dont use the sdf.file the clkdiv clock has large delay (clock race also) "H.L" <alphaboran@yahoo.no-spam.com> wrote in message news:a9orem$2fe2$1@ulysses.noc.ntua.gr... > Hello all, > I use a Virtex-E for my design. I have an external clock 155MHz that I pass > through a CLKDLLE to acquire the divide by 2 clock. The timing analyzer > reports no timing errors but when I timing simulate the design in modelsim > (5.2) I get large clock skew between the DLL clocks. > > The CLK0 rising edge is delayed about 4.2 ns (clock race) with respect of > the CLKIN clock!! This clk0 signal is the input of a BUFG whose output is > the CLKFB of the CLKDLLE. The external 155 clock uses a LVDS_DLL pin... > (should I use the inverted signal for feedback?) > > The clock divided by two is delayed for less than 1 ns.. > > Is this a simulation error or an implementation error? Any help is very very > wellcome! > > Best Regards, > Harris > > >Article: 42268
> I have read that there is a limitation to the number of adjacent output > drivers that can switch at the same time in an FPGA. There are rules > stated in terms of SSO(simultaneous switching outputs) pads between > power/gnd pins. Can anyone please elaborate on that.. High currents, generated when multiple outputs switch from high to low simultaneously can cause ground bounce. The transition causes the charge stored in the load capacitances to flow into the device: a voltage Lx(dI/dT) between board ground and device ground causes the relative ground level for low outputs to bounce. Here some suggestions given by Altera for FPGA design: - add de-coupling capacitors for VCC/GND pairs. - limit load capacitance with a bus driver IC. - place switching pins next to a ground pin and distribute them evenly through the device. - use virtual ground, i.e. create an output pin in your design that drives low (ground) and connect it to the board ground. - many devices have a slow slew rate option for output drivers.. this decreases dI/dT. I hope this is a pertinent answer. MarcoArticle: 42269
In article <a9m29j$4dlk1$1@ID-41871.news.dfncis.de>, steffen.thieringer@nmb.co.uk says... > >Hello newsgroup! >I am looking for a 8051 Core to implement in an Xilinx Spartan2 FPGA. >The task for it is a control of a sensorless brushless DC motor. >The software for the processor is already done but needs to be speeded up. >So i need pwm, capture/compare units, several timers ans so on... >I have several in my mind but not yet found 'the one'. >I am not looking for freeware, but if there are some out there, please let >me know:-) > Hello Steffen, I have links to several but at this Moment i know the licence only for one. 1. http://www.oregano.at/services/8051.htm no Performance data known This is under the LGPL 2. http://www.cs.ucr.edu/~dalton/i8051/ in a XILINX V300PQ240 Virtex FPGA the maximum clock speed is 11.6 MHz. I have not found licence information but it seems to be free 3. http://www.8051.free.fr/ seems to be based on the core from dalton or is the same ( I don't know, I speak no french ) 4. http://www.opencores.org/projects/8051/ ongoing project, misses some peripherals according to website in alpha state I have a list with links at the website of our Linux User Group http://www.lug-kiel.de/links/details/hdl.html#cpu_8051 with kind regards Klaus LeissArticle: 42270
Is it available in PDF? Damir "Hari Devanath" <harid@xilinx.com> wrote in message news:3CBDE120.82B83123@xilinx.com... > Hi Prashanth, > In particular, if you want to write HDL for Xilinx devices, this is a good > place to start: > http://toolbox.xilinx.com/docsan/xilinx4/data/docs/sim/preface.html > Hari. > > Prashant wrote: > > > hi, > > I read in a post previously that VHDL/Verilog programming style > > differs when being written for an FPGA from being written for an ASIC. > > Is there any website which mentions these differences ? I'm looking to > > see what should I take care of when programming for an FPGA. > > > > Thanks, > > Prashant >Article: 42271
Hi,
I have a design where the input clock is driven from one of two sources
depending on board configuration i.e. either from osc. A or from osc. B.
The two oscillators are never connected at the same time.
Each of the two input clocks are connected to one DCM respectively.
The clk0 output from the two DCMs are connected to an BUFGMUX which is
used to select which of the two input that should be used for the
internal clock. Is it possible to use the status output from the DCM(s)
to determine which clock input to use, i.e. control the BUFGMUX?
FPGA
+-------------------------------------------+
| +----------------+ |
+-----+ | | +---+ fb | |
| osc.| _ | +-|DCM| | |
| A |----->(_)---|-->|in |---+ + | |
+-----+ | | | |__|\ | |
| +---+ | \_|___internal_clk |
+-----+ | +---+ __| / | |
| osc.| _ | |DCM| | |/| | |
| B |----->(_)---|-->|in |---+ | | |
+-----+ | +-| |--------+ | |
| | +---+ status(1)| |
| | | |
| +----------------+ |
| fb |
| |
+-------------------------------------------+
Thanks in advance
Patrik Eriksson
--
Patrik Eriksson | patrik.eriksson@netinsight.net
Net Insight AB | phone: +46 8 685 04 89
Västberga Allé 9 | fax: +46 8 685 04 20
SE-126 30 STOCKHOLM, Sweden | http://www.netinsight.net
Article: 42272I'm using ModelSim XE. On starting the simulation it goes through all the loading up process OK and then closes with the message below :- Internal error : bad pointer access ........... Closing vsim vsim is exiting with code 11 Trouble with peer processes (0), exiting. Anybody seen/solved this one. Maybe my design is to big for XE at 27k statements??? Would it bomb out in this way? Thanks ! Phil PS. Why don't software packages give a website reference to a list of error messages with a longer and less cryptic explantation of what the error message means. eg. "Error Code 1175 see www.mentor....." -- Posted via Mailgate.ORG Server - http://www.Mailgate.ORGArticle: 42273
In article <22f10f27.0204190051.47231cda@posting.google.com>, K PRASAD
<prasadkdnvs@rediffmail.com> writes
>Alan Fitch <alan.fitch@doulos.com> wrote in message news:<Q9PxaJAurpt8YBYz@doulo
>s.co.uk>...
>> In article <22f10f27.0204111935.2d488e51@posting.google.com>, K PRASAD
>> <prasadkdnvs@rediffmail.com> writes
>> >hello
>> >i am new to vhdl and digital design.
>> >if we just observe the following code
>> >
>> >case1)
>> >
>> > p1 : process
>> > begin
>> > if clk'event and clk ='1' then
>> > for i in 0 to 9 loop
>> > result <= mul1 * mul2; -- mul1 and mul2 and result are defined
>> > --as signals earlier
>> > end loop;
>> > end p1;
>> >
>> >case2) p1 : process
>> > variable result;
>> > begin
>> > if clk'event and clk ='1' then
>> > for i in 0 to 9 loop
>> > result := mul1 * mul2; -- unlike in case1 ONLY mul1 and mul2
>> > -- are defined as signals
>> > end loop;
>> > end p1;
>> >
>> > so if we observe the two codes the loop will be executed in just one clock
>> > cycle in case2 whereas in case1 only for one i(loop index) it will be
>executed.
>> > i think i am clearing in saying this.
>> > now my doubt is
>> >
>> > if we synthesise both the codes what makes the difference?
>> >
>> > also should i need to initialise any counter in case1 and get the
>> > functionality as in case2?
>> > how should we interpret the result of the synthesis?
>> > also if i use only variables in my modelling
>> > then will it be synthesized accurately?
>> >
>> >can anyone help me.
>> >thank u
>> >prasad.
>>
>> The "trick" with loops is to "unroll" the loop.
>>
>> So instead of for i in 0 to 9 loop, think of it as
>>
>> case1)
>>
>> result <= mul1 * mul2; -- i = 0
>> result <= mul1 * mul2;
>> result <= mul1 * mul2;
>> result <= mul1 * mul2;
>> result <= mul1 * mul2;
>> result <= mul1 * mul2;
>> result <= mul1 * mul2;
>> result <= mul1 * mul2;
>> result <= mul1 * mul2;
>> result <= mul1 * mul2; -- i =9
>>
>> Now you have made 10 assignments to the same signal, but NO TIME HAS
>> PASSED - all assignments schedule events 1 delta cycle in the future.
>> Then, because of the way signals work, each later assignment cancels the
>> previous assignment - so the code is equivalent to writing
>>
>> result <= mul1 * mul2;
>>
>> Note this is because you are in a process, and statements execute
>> sequentially in a process.
>>
>> On our courses, we call this "last assignment wins", i.e. when making
>> multiple assignments to a signal in a process all in the same delta
>> cycle.
>>
>> Finally, because you are making a signal assignment in a clocked
>> process, result will become a set of flip-flops.
>>
>> case2)
>>
>> result := mul1 * mul2; -- i = 0
>> result := mul1 * mul2;
>> result := mul1 * mul2;
>> result := mul1 * mul2;
>> result := mul1 * mul2;
>> result := mul1 * mul2;
>> result := mul1 * mul2;
>> result := mul1 * mul2;
>> result := mul1 * mul2;
>> result := mul1 * mul2; -- i =9
>>
>> In this case, result updates straight away because it is a variable.
>>
>> By the end of the loop, result contains mul1 * mul2.
>>
>> However this time, nothing will happen. Why? Because you have not
>> assigned result to a signal, and variables are local to the process. So
>> result cannot be seen outside the process, hence the synthesis tool
>> should optimise it away.
>>
>>
>> For synthesis of signals in a clocked process :
>>
>> In clocked processes a signal assignment results in flip-flops
>>
>> For synthesis of variables in a clocked process :
>>
>> In a clocked process, if you read a variable value then assign it,
>> you get a flip-flop.
>>
>> In a clocked process, if you assign a variable then read it, you get
>> a piece of wire.
>>
>>
>>
>> In your example above, you get a piece of wire, but then it is not seen
>> outside the process so it gets optimised to nothing.
>>
>>
>> Regarding your questions, neither example is a counter, if I've
>> understood you correctly.
>>
>> And yes, you can use variables as long as you understand the rules
>> above, and remember to copy its value into a signal if you want to see
>> it outside the process.
>>
>> I hope this helps,
>>
>> Alan
>>
<snip>
>>
>> hai ALAN thank u very much
>
>now what about the timing issues
>how many clock cycles will they require
>for the two loops.
As written above, both will execute in the simulator in no time, i.e.
the new value will become available one delta after the clock edge.
>As u said if i assign the variable to
>a signal to view it outside the process,then
>how will the synthesizer implement the variable and optimise it?
>
In the example above, the signal assignment will result in a register,
the variable will just cause a piece of wire.
>can the multiplication takes place (for the ten times)
>in the single clock.?
In simulation it can. In hardware, it depends on your clock speed.
>how will the multiplication takes place for
>ten times as mulitplier itself will take one clock cycle
>for a single mulitplication?
As I said above, you've just repeated one statement 10 times.
Effectively only one of those statements has an effect, the other 9 are
being ignored (overwritten).
>how will it be synthesized.
You should get one multiplier followed by register.
Regards
Alan
--
Alan Fitch
DOULOS Ltd.
Church Hatch, 22 Market Place, Ringwood, Hampshire BH24 1AW, United Kingdom
Tel: +44 1425 471223 Email: alan.fitch@doulos.com
Fax: +44 1425 471573 Web: http://www.doulos.com
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Article: 42274Hi, in my design I'm using the Altera parameterized RAM function named lpm_ram_dq. MAX+PLUS II software automatically implements suitable portions in the EABs of a FPGA device (ACEX 1K). I'm using a HEX File containing initial values for the memory to be passed to the compiler. After configuring the SRAM-based device, by a serial configuration device, the initialization memory data is loaded properly except the last memory location. Have you ever found such problem? Maybe a wrong parameters setting? Thank you for suggestions. Marco
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