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"XU QIJUN" <qijun677@oki.com> schrieb im Newsbeitrag news:3d1298bf$1@news.starhub.net.sg... > Forgot to mention, my CLKIN = 16.0 MHz. CLK8X will yield 128 MHz. [ clock multiplication x8 using DLLs] Three things. First, the minimum input frequency for the DLLs is 25 MHz. It will work at lower frequencies (I once reached 13 MHz) but noone will guarentee this. So this trick is for the lab only, not a shipping product. Second, a cascade of 3 DLL generates lot of jitter (according to the datasheet, the will be +/-600 ps jitter, since 1 DLL has +/- 200 ps) Third, in the case of 3 DLLs, the P&R tools are not smart enought to place the DLLs itself. So you must provide location constraints for the components in the UCF. They look like this INST dll_inst_name LOC="DLL0"; The same for the IBUFG. Have a look at the ISE/Webpack docu, Constraints Guide/ Chapter L (LOC constraint). -- MfG FalkArticle: 44501
"Kevin Brace" <ihatespam99kevinbraceusenet@ihatespam99hotmail.com> schrieb im Newsbeitrag news:aetk8h$uuv$1@newsreader.mailgate.org... > Falk, are you saying that you got more modules than the two modules in > question, and at least one of those modules also instantiate another > blackbox? > Does your design hierarchy look something like this? > > > Module A > / \ > Module B(BB) Module C(BB) > | > Module D(BB) > Right. > > I have never tried this, but if you want Module B to retreat > Module D as a blackbox, you will have to declare another blackbox in > Module B when it is synthesized. > During NGDBUILD, you will also have to point to Module D's netlist > because when Module B is read by NGDBUILD, it will demand a netlist for > Module D. This is done. > Not sure. > It is probably better or maybe the only way to resolve the issue at > NGDBUILD level. How? This is the question of today. -- MfG FalkArticle: 44502
"cfk" <cfk_alter_ego@pacbell.net> schrieb im Newsbeitrag news:TSIQ8.6690$ll2.353811755@newssvr21.news.prodigy.com... > add them properly. I can add IOSTANDARD's and LOC's with no problem to the > UCF, but now timing has become an issue. As always, any suggestions will be > greatly appreciated. UCF is fine. Start with NET my_clk period=30ns; (33 MHz PCI) -- MfG FalkArticle: 44503
On 21 Jun 2002 10:41:19 -0700, jfu1650@hotmail.com (Johnny Fu) wrote: >Hi, > >I am trying to find a way to prevent the Max+Plus II 9.4 compiler from >performing any logic minimization on a VHDL design similar to the one >below: > > A B C >input ----|>*-------|>*--------|>*----- output > >Using Synplify 7.1, I can synthesize the design and keep all the >appropriate nets. However, even after specifying a WYSIWYG global >logic synthesis compilation option in Max+PlusII; taps A, B, and C are >no longer connected together and appear as separate input and output >paths. The logic for B and C are also minimized as B is driven purely >by the input (and the internal and-or-xor structure) without the >presence of the two inverters before it and C is driven by a single >inverter instead of three. Therefore, A, B, and C in a time >simulation all change value at the same time without any delay between >them (since they are no longer connected). Are there any other options >that I can try for preventing logic minimization? I am compiling for >an Altera Max7000AE chip. Thanks. You could try taking the signal *through* the IO pin associated with the macrocell. Your synthesiser should not optimise these out. You'll need to fool it into thinking that the pins are actually bidirectional (so that it takes feedback from the pin, and not from the internal signal). A similar technique was mentioned here: http://groups.google.com/groups?threadm=3c940eff.11412009%40netnews.agilent.com Regards, Allan.Article: 44504
one of the constraints is that the system uses COTS hardware, because things do get bumped around here (sometimes even blown away) and we need to either keep spares or be able to get a new one overnight. "Jay" <kayrock66@yahoo.com> wrote in message news:d049f91b.0206202205.48616c9e@posting.google.com... > It may be overpriced but can you design, build, debug ONE card for > that price? As engineers I think we get caught up sometimes in part > cost or tend to be optimists on our ability to finish a task quickly. > You kind of have to be to tackle some of the problems we get handed. > > kolja@bnl.gov (Kolja Sulimma) wrote in message news:<25c81abf.0206161242.261776e4@posting.google.com>... > > This card will likely do the job for you. > > But for your simple application it is extremely overpriced. > > > > If I understand your application correctly, 24 counters of 24 Bits > > should fit into a Spartan-II 200 Device together with a PCI core and a > > FIFO. > > > > Kolja Sulimma > > > > > > > > "Pat Ford" <pat.ford@nrc.ca> wrote in message news:<aeco9f$oi8$1@moonstone.imsb.nrc.ca>... > > > They do BUT each card will only do 8 channels and the cost is high, and > > > they don't support the range of OS's that we are looking at. > > > We are looking at the Nallatech > > > Strathnuey kit with the XCV1000 fpga, any have opinions on this card? > > > http://www.nallatech.com/products/dime_select/strathnuey/index.asp > > > thanks for your help so far > > > Pat > > > > > > "Jay" <kayrock66@yahoo.com> wrote in message > > > news:d049f91b.0206131216.10a6fa2d@posting.google.com... > > > > I don't want to spoil your fun but this sounds like something that > > > > might already be available. Look at those PC intrumentation guys like > > > > National Instruments and the like, they may have something you can use > > > > or that can be gated.Article: 44505
Thomas <ThoLei@gmx.net> wrote in message news:<ee77011.-1@WebX.sUN8CHnE>... > Hi @ all! > > I am a complete Newbie to FPGA´s, but now i must work with them. I have a Spartan II Demo Board (Insight) with XC2S100 FPGA and want to use ISE Webpack for programming it. I have searched for documentations, tutorials but have not found yet any good results. Does anyone have suggestions where to find good eplainations using ISE Webpack??? > > Thank you, Thomas > > PS: Could you please answer as well via Email? Our tutorials are geared at CPLDs but they show quite a bit of the Webpack functions: http://www.al-williams.com/pictutor Regards, Al Williams AWCArticle: 44506
Picky, Picky... Actually I suspected that was coming. Just as I get a handle on a part, they stop recomending it. Actually, two years ago, that part was recommended by an apps engineer at a particulr distributor. He said that it was more available than the Virtex series. I designed it in and now who knows whether I will be able to get it in the future. My newest design uses the Spartan2E. I hope that will be around for a while. Working within a university setting is a little different and our FPGA boards in the the EDA labs were 4013's until this fall. Now they finally "upgraded" to SpartanXL's in Sept of 2001. Oh well... Ray Andraka wrote: > Right, but that is not recommended for new designs at this point. > > Theron Hicks wrote: > > > "Ray Andraka" <ray@andraka.com> wrote in message > > news:3D120F32.7321A03@andraka.com... > > > SpartanII and Virtex have 5v tolerant 3.3v I/O. > > So does SpartanXL > > -- > --Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email ray@andraka.com > http://www.andraka.com > > "They that give up essential liberty to obtain a little > temporary safety deserve neither liberty nor safety." > -Benjamin Franklin, 1759Article: 44507
I would suggest upgrading your Nios and SOPC Builder. Newer versions of SOPC Builder are much more powerful when it comes to multi-master systems. The current product versions are Nios v2.1 and SOPC Builder 2.5. --->Alan "Ryan" <ryans@cat.co.za> wrote in message news:<3d133f61.0@obiwan.eastcoast.co.za>... > HI > > Thanks for the pointer. I have downloaded the file but I am having > difficulty opening each Nios core, ie SOPC won't load up. Any suggestions? > > Thanks > Ryan > > "Vincent JADOT" <vjadot@digitalsurf.fr> wrote in message > news:3d119950$0$24013$4d4eb98e@read.news.fr.uu.net... > > Hi > > > > there is an example to download of 2 nios on a chip (excalibur kit) at > this > > address: > > http://cnfm.cnfm.fr/ALTERA/ExcaliburN/Arbitrage.zip > > > > it 's on a french site, http://cnfm.cnfm.fr/ALTERA/Excalibur.htm, it's for > > examples and update for the ALTERA french university program. So it's in > > french, but i think it's understandable for english people. > > > > Excuse my english, i'm a french student. > > > > > > > > > > > > "Ryan" <ryans@cat.co.za> a écrit dans le message news: > > 3d12031a.0@obiwan.eastcoast.co.za... > > > Hi > > > > > > I am working with an Altera Excalibur Nios development board version > 1.1. > Is > > > it possible to configure the PLD (20K200) with more than 1 Nios cpu? > What > I > > > would like to do is configure 1 cpu to be a master and the others as > slaves. > > > The master will then control the processess executed on the slaves etc. > > > Ideally the slaves will not have to make use of external SRAM of FLASH. > Is > > > this concept possible and how can it be implemented? If not, have you > any > > > suggestions on what other route to consider? > > > > > > Thanks > > > Ryan > > > > > > > > > >Article: 44508
Hi all, has anyone implemented Baugh-Wooley multiplier (parallel/serial )using Handel-C?Article: 44509
According to Spartan-II datasheet the min input frequency to a DLL is 25 MHz. 16 MHz will most likely cause a problem even if you are able to overcome the error given to you by the tools.Article: 44510
"Muthu" <muthu_nano@yahoo.co.in> wrote in message news:28c66cd3.0206202239.60ce2324@posting.google.com... > Hi, > > where can i get the xilinx's 4.1i's Latest webpack? and how to updatae the webpack? It's 4.2WP20 now (113 Mb!). You can get it from the Xilinx web site. I'm in the process of downloading it, only 1.5 hours or so to go. 8-( AFAIK Webpacks are not upgradeable, you have to download the new version. Leon -- Leon Heller, G1HSM leon_heller@hotmail.com http://www.geocities.com/leon_heller Low-cost Altera Flex design kit: http://www.leonheller.comArticle: 44511
Hi, I am trying to prevent the Max+Plus II 9.4 compiler from performing any type of logic reduction on a VHDL design similar to the one below: ---|>*--- = inverter input------|>*A-------|>*B---------|>*C-------output I am able to synthesize the design in Synplify 7.1 and keep all the nets after synthesis. However, when I compile the implementation in Max+Plus II, taps A, B and C are no longer in a chain and instead are driven only by the input, minimized logic, and the internal and-or-xor sturcture of the device. So B is only driven by the input and the and-or-xor structure without any inverters because the output logic is the same as with two inverters. Also, C is now only driven with one inverter since that is logically equivalent to driving with 3 inverters. This reduction still occurs even after I try assigning a WYSIWYG global logic synthesis to the design. I am using an Altera Max7000AE chip. I have contacted Altera about this issue but have yet to hear a solution so any help would be much appreciated. Thanks. -JohnnyArticle: 44512
Faulk, See comments below: Falk Brunner wrote: > "Kevin Brace" <ihatespam99kevinbraceusenet@ihatespam99hotmail.com> schrieb > im Newsbeitrag news:aetk8h$uuv$1@newsreader.mailgate.org... > > > Falk, are you saying that you got more modules than the two modules in > > question, and at least one of those modules also instantiate another > > blackbox? > > Does your design hierarchy look something like this? > > > > > > Module A > > / \ > > Module B(BB) Module C(BB) > > | > > Module D(BB) > > > > Right. > If you have successfully created EDIF files for modules B, C and D and successfully instantiated them as black boxes then all that is required is to have all of the EDIF files in the same directory when NGDBuild is run. NGDBuild will recognize the missing components in each EDIF file as it is read in. In this case the default behavior of NGDBuild is to look in the project directory to fill in the missing components with some type of netlist (EDIF, NGO, NGC). If NGDBuild can not do this then it will fail with an unexpanded error meaing it can not expand (translate) the component (which is a black box) that is not defined. > > > > > I have never tried this, but if you want Module B to retreat > > Module D as a blackbox, you will have to declare another blackbox in > > Module B when it is synthesized. > > During NGDBUILD, you will also have to point to Module D's netlist > > because when Module B is read by NGDBUILD, it will demand a netlist for > > Module D. > > This is done. > > > Not sure. > > It is probably better or maybe the only way to resolve the issue at > > NGDBUILD level. > > How? This is the question of today. > > -- > MfG > Falk SteveArticle: 44513
It's not simple supply and demand. You hire a smart guy that does something useful and his company makes better products, the entire market segment grows, the pool gets bigger. That's how we got here in the first place. "Simple" supply and demand keeps the pool the same size. If you work in a field where your stock goes up if your competitor does something good, you want all of the smart people in the pool. It's classic, there's always a dumb guy that thinks it's a zero sum gain and wants to raise the drawbridge. It's almost always the wrong thing to do. (I don't think any of you are dumb guys). I hope the guy gets a job, invents a widget, and makes us all a little richer. jeff kayrock66@yahoo.com (Jay) wrote in message news:<d049f91b.0206202146.46dece2f@posting.google.com>... > Ya, but the more people enter the job pool in your specific field, the > cheaper the salaries for everyone in that field will be. Just simple > supply and demand. Lets just call H1-B what it is: a labor subsidy > for high tech, approved by corrupt politicians.Article: 44514
One of the reasons Leo may have reported much less LE is the fact that LEO can extract RAM and ROM and implement it in embedded memory blocks. I don't know whether Quartus can do that. Regarding newer versions of Leo: I use 2002a_49. It has some quirks fixed so it is worth a try... Endric -- Bridges2Silicon, Inc. Endric Schubert, PhD 471 E. Evelyn Ave. Sunnyvale, CA 94086 www.bridges2silicon.com "Paul Baxter" <pauljnospambaxter@hotnospammail.com> wrote in message news:3d006605$0$236$cc9e4d1f@news.dial.pipex.com... > > Since LS-Altera is free (Albeit the GUI is buggy.) even for QII Web > > Edition users (Although I rather get a free crippled ModelSim instead.), > > there really is no reason to use Quartus II native synthesis tool at all > > other than maybe some beginners may appreciate it because they won't > > have to import an EDIF netlist from LS-Altera. > > I echo the sentiment NOT to use quartus for synthesis, just place and route > with the edif output from leonardo. > If you use the buggy (but useable) gui you can even do the quartus place and > route from within Leo. > > I would however use Q2 to generate PAR constraints as you can get more > detailed than using Leo alone. > > I'm still using Leo 2001_1d, anyone any comments on the newest release? > > > >Article: 44515
A hardware guy in my company recently mentioned that he has 2 "bad" Xilinx Virtex2 devices now. In one device there seems to be a stuck-at-1 memory bit (he found that out when using 100% block RAM) the other seems to have a internal connection problem: One and the same bit file works fine on one device but not on the "bad" device. I just wonder, has anybody had similar experiences and how do you find those problems in the lab? Endric -- Bridges2Silicon, Inc. Endric Schubert, PhD 471 E. Evelyn Ave. Sunnyvale, CA 94086 www.bridges2silicon.com Direct: (408) 245 8513 Fax: (408) 245 2960 Mobile: (408) 221 6139Article: 44516
Yeah, that one. :) I bounce back and forth between at least 3 synthesizers, I can't remember their names, and I have trouble spelling them as well. On Thu, 20 Jun 2002 01:25:55 -0500, Kevin Brace <ihatespam99kevinbraceusenet@ihatespam99hotmail.com> wrote: > > >Spam Hater wrote: >> >> No. >> >> My license for 1.5 does not expire. Supposidly. >> >> IIRC, 2.x has an annual license. Wish I recalled wrong, as I would >> like to upgrade. >> >> I never upgraded because I was told that I could NOT get a permanent >> license for versions >= 2.x I was told that the Synplicity folks were >> forcing them to do that. >> > > > Isn't the firm you are talking about Synopsys instead of >Synplicity which used to supply a Xilinx specific version of FPGA >Express to Xilinx? > > >Kevin Brace (In general, don't respond to me directly, and respond >within the newsgroup.)Article: 44517
I don't blame the applicants either. Like me, they have families to feed too. To Jakob: You must live in a fantasy land. There are so many employers abusing the system that it is absurd. On 20 Jun 2002 22:46:04 -0700, kayrock66@yahoo.com (Jay) wrote: > >I don't blame the applicants, heck, I'd be first line if I lived in >the second world and someone offered me a way out. >Article: 44518
I am using a BlockSelectRam instance and want access to the generics to initialise it, set read/write modes etc. The "Virtex II User Guide" includes a sample VHDL template. This includes code for simulation (using generics) & synthesis (using attributes). Generics & attributes are named identically. When I try to compile it (for simulation, using ModelSim), the compiler sees (as one would expect) both generics & attributes, so it reports the names are re-defined. For synthesis, there is clearly no problem, as the "-- pragma translate off/on" lines will hide the generics. Is there (or should I need) a similar mechanism to hide the attributes in simulation?Article: 44519
In general you shouldn't try to exploit the asynch timing nature of programmable logic. The timing can vary greatly from run to run (CPLDs the exception) and you end up fighting the tools. What is it that you are trying to achieve with your circuit? Regards jfu1650@hotmail.com (Johnny Fu) wrote in message news:<787cec10.0206210941.12c86426@posting.google.com>... > Hi, > > I am trying to find a way to prevent the Max+Plus II 9.4 compiler from > performing any logic minimization on a VHDL design similar to the one > below: > > A B C > input ----|>*-------|>*--------|>*----- output > > Using Synplify 7.1, I can synthesize the design and keep all the > appropriate nets. However, even after specifying a WYSIWYG global > logic synthesis compilation option in Max+PlusII; taps A, B, and C are > no longer connected together and appear as separate input and output > paths. The logic for B and C are also minimized as B is driven purely > by the input (and the internal and-or-xor structure) without the > presence of the two inverters before it and C is driven by a single > inverter instead of three. Therefore, A, B, and C in a time > simulation all change value at the same time without any delay between > them (since they are no longer connected). Are there any other options > that I can try for preventing logic minimization? I am compiling for > an Altera Max7000AE chip. Thanks.Article: 44520
Jay wrote: > > In general you shouldn't try to exploit the asynch timing nature of > programmable logic. The timing can vary greatly from run to run > (CPLDs the exception) and you end up fighting the tools. What is it > that you are trying to achieve with your circuit? Correct, but there are also times when it is required. In many instances, this is a relative delay, so unit to unit spreads are not important. > > Hi, > > > > I am trying to find a way to prevent the Max+Plus II 9.4 compiler from > > performing any logic minimization on a VHDL design similar to the one > > below: > > > > A B C > > input ----|>*-------|>*--------|>*----- output > > > > Using Synplify 7.1, I can synthesize the design and keep all the > > appropriate nets. However, even after specifying a WYSIWYG global > > logic synthesis compilation option in Max+PlusII; taps A, B, and C are > > no longer connected together and appear as separate input and output > > paths. The logic for B and C are also minimized as B is driven purely > > by the input (and the internal and-or-xor structure) without the > > presence of the two inverters before it and C is driven by a single > > inverter instead of three. Therefore, A, B, and C in a time > > simulation all change value at the same time without any delay between > > them (since they are no longer connected). Are there any other options > > that I can try for preventing logic minimization? I am compiling for > > an Altera Max7000AE chip. Thanks. Looking in the MAX+II help, under Minimization, it shows <name>: MINIMIZATION = (FULL|PARTIAL|DEFAULT|NULL) but they do seem confused if the keyword is none or null :) You did try this ? -jgArticle: 44521
Do what Steven Elzinga of Xilinx said.
Declare a blackbox in Module B for Module D (Which you already did.).
Then copy all the relevant EDIF netlist to the work directory of the top
module, or specify all the locations (Macro Search Path of NGDBUILD) the
relevant EDIF netlists are located (You can specify multiple paths.).
I recommending specifying the macro search paths, so that each time you
update the EDIF netlists, you won't have to copy them to the work
directory of the top module.
Kevin Brace (In general, don't respond to me directly, and respond
within the newsgroup.)
Article: 44522Hi! > wget --http-user <your user ID> --http-passwd <your passwd> > http://direct.xilinx.com/direct/webpack/FILE You can use the "-c" option of wget to continue a download. For other options (wget has looots of them) use "wget --help" and "man wget". Bye HansiArticle: 44523
> Pipelined architecture is used to implement parts of a more > general processor, such as the multiplier or divider of a > processor. Usually the pipeline is relatively short, as this > specifies the latency. > -- glen >"Usually the pipeline is relatively short, as this specifies the latency." so how do u relate it to synchronous/asynchronous logic? do u think a divider in systolic logic is asynchonous and in piplined architecture it is synchronous?? and which type of architecture is preferable for fast processing? ---sushantArticle: 44524
Kayrook: You are making a good argument for using COTS prototyping boards instead of doing your own desing. I agree with this. But for an application that needs nothing but 24 IO Pins and somthing like 300 Slices an XCV1000 plus a XC2S150 plus USB plus DAC plus ADC is an overkill. There are PCI prototyping boards at 20% of the price. They offer less, but they offer enough for the given application. A plus of the Strathnuey is that you do not need to take care of the PCI bus as it has a seperate FPGA for this. Kolja Sulimma kayrock66@yahoo.com (Jay) wrote in message news:<d049f91b.0206202205.48616c9e@posting.google.com>... > It may be overpriced but can you design, build, debug ONE card for > that price? As engineers I think we get caught up sometimes in part > cost or tend to be optimists on our ability to finish a task quickly. > You kind of have to be to tackle some of the problems we get handed. > > kolja@bnl.gov (Kolja Sulimma) wrote in message news:<25c81abf.0206161242.261776e4@posting.google.com>... > > This card will likely do the job for you. > > But for your simple application it is extremely overpriced. > > > > If I understand your application correctly, 24 counters of 24 Bits > > should fit into a Spartan-II 200 Device together with a PCI core and a > > FIFO. > > > They do BUT each card will only do 8 channels and the cost is high, and > > > they don't support the range of OS's that we are looking at. > > > We are looking at the Nallatech > > > Strathnuey kit with the XCV1000 fpga, any have opinions on this card? > > > http://www.nallatech.com/products/dime_select/strathnuey/index.asp > > > thanks for your help so far > > > Pat
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