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By applying 5V without powering the FPGA, I killed an IOB of an XC4005A several years ago. (BTW: It took hours) Since that time, I always try to avoid powering I/O lines before powering the FPGA. In some rare cases where this is not possible, I use series resistors. - Manfred "Andrew Bridger" <andrew.bridger@paragon.co.nz> schrieb im Newsbeitrag news:7939158e.0206252307.2bfbadab@posting.google.com... > Hi, > What are the consequences, if any, of applying an external > voltage(4.3V max) to FPGA(Spartan II, XC2S50-5PQ208C) I/O pins for an > extended period of time(seconds/minutes/hours), while the FPGA VCCO > and VCCINT are not powered? > > When I apply 4.3V to a single FPGA I/O I get VCCO coming up to around > 0.58V and VCCINT stays at 0V. > > On page 1 of module 3(DC and Switching Characteristics) of the data > sheet, under Absolute Maximum ratings, the relevant specifications > seem to be > 1)Vin - Input voltage relative to GND, -0.5v to 5.5V for 5V tolerant > I/O which I meet, and -0.5 to VCCO +0.5 for non-5v tolerant I/O which > I do not meet. But I'm not sure if my I/O are classed as 5V tolerant > or not when there is no power supplied to VCCO and VCCINT? > 2)Note 3 says Vin should not exceed VCCINT by more than 3.6v over > extended periods of time, which again I fail to meet. > > Do I have a problem? > > I think I understand why spec 1) exists. The high side output FET of > an FPGA I/O has an inherent diode from the FPGA I/O pin to VCCO?(or > perhaps not for LVTTL). If the FPGA I/O pin gets driven too high then > this diode can conduct excessive current? Is this correct? > > Thanks in advance. > AndrewArticle: 44701
rickman wrote: > I think people have misunderstandings of how the Xilinx software is > licensed. I am pretty sure I have read in this newsgroup postings from > Xilinx representatives that the Xilinx software will continue to operate > after the license has run out. Only the support is ended. That is correct. The expiration of the software is only in the wording of the license agreement. There is *no* physical licensing mechanism that might prevent a user from continuing to maintain existing designs in the indefinite future, as long as you need it, as long as you want. No problem! Peter Alfke, Xilinx Applications > >Article: 44702
"a.j." <andrej.jancura@tu-ilmenau.de> wrote in message news:aff01m$e6n$1@piggy.rz.tu-ilmenau.de... > Hi, > > few days ago the oscilator implementation with external RC has been > discussed in the list. Now I'd like ask you, if it possible to make the > oscilator only with external 32kHz crystal in Xilinx 95xx and CoolRunner > series. Thank you. I don't think this is feasible, as they need a very specific type of oscillator, unlike the usual 1 MHz to 20 MHz crystal. Crystal manufacturers should have the details of the oscillator requirements for this type of crystal on their web sites. Leon -- Leon Heller, G1HSM leon_heller@hotmail.com http://www.geocities.com/leon_heller Low-cost Altera Flex design kit: http://www.leonheller.comArticle: 44703
They will, provided the synthesizer recognizes it and does not destroy it optimizing it due to input bits
that are constant. Synplify can have troubles doing the construction correctly if you are doing something
a bit more complicated like a mux-add, gated add or scaling accumulator. If you code it exactly the way it
should go in hardware (don't use if inside the process), it seems to do OK in most cases. Synplify also
has a bad habit of doing optimizations that can make a mess of the carry chain if one or more of the bits
are constant. For the most consistent results, we generally instantiate an adder out of our library rather
than trusting the tools to do the right thing.
Jay wrote:
> I'm pretty sure that all the modern synthesizers will infer the
> optimum ripple carry using dedicated resources type adders. Synopsys
> Design Compiler even will if you are using the Xilinx designware
> libraries. Don't instantiate unless you have no choice, and in this
> case, you do.
>
> Regards
>
> kkdeep@mailcity.com (kuldeep) wrote in message news:<a0f016a9.0206242214.8845d5c@posting.google.com>...
> > Hi,
> > 1. is there any coding guidelines to use carry chains in xilinx fpga
> > (Virtex E) or i have to use coregen.
> > 2. is there any better method of coding a 12 bit adder than using
> > sum <= input1 + input2
> > where sum, input1 and input2 are vectors.
> >
> > TIA
> > regards
> > Kuldeep
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 44704Yes you'll are absolutely rigtt!!!! how stupid of I, we have only use up 2 out of the 12 DCM...........there are no excuse why I miss it :( any way the DCM will solve 10 out of 12 channel, as for the 2 channel some hand place route should not be a problem thanks all pyng "Falk Brunner" <Falk.Brunner@gmx.de> wrote in message news:<afcnid$cs91h$1@ID-84877.news.dfncis.de>... > "spyng" <ospyng@yahoo.com> schrieb im Newsbeitrag > news:b34a8c79.0206260526.18c87c8@posting.google.com... > > > we could indirectly control the skew of the clock by setting a small > > maxdelay, and max skew on the individual clock net. short delay > > indirectly lead to small skew..... I hope. > > > > It will be great as Falk as point out if only we have min delay... > > > > have a 8 time clock and sample the input data into a shift reg is out > > too, because the data is coming at 100 Mhz ddr with a data window of 3 > > ns, therefore need 400 Mhz, but x2v4000 -4 DCM max out at 360 Mhz, > > aleast this is what the data sheet say. > > Man, if you have a Virtex2 (I didnt realize this at first) you can use a DCM > to make a fixed phase shift on your clock. Adjust it to you needs and you > will be fine. No need for oversampling etc. > > > sure hope we have define the interfacing spec better ..... > > @100 Mhz, you better know what you are doing.Article: 44705
a.j. wrote: > > Hi, > > few days ago the oscilator implementation with external RC has been > discussed in the list. Now I'd like ask you, if it possible to make the > oscilator only with external 32kHz crystal in Xilinx 95xx and CoolRunner > series. Thank you. No. -jgArticle: 44706
> I think it is because the device is too hot, I touch the device with > my finger, it is very very very hot, > > so if any one have any sugession? It may be that you have set the unused output pins to "driving ground". You can find this out by opening the "Processing" menu and selecting the "Compiler settings" item. On the dialog that shows up, select the "Chips&Devices" tab, and on that screen, click the "Device & pin options" button. On the dialog that pops up there, select the "Unused pins" tab. There you can see whether they are set to drive ground. To see whether this is a problem, select "as input, tri-stated", recompile, and try it again. Who said the Quartus user interface was simple ;-) If the devices is still so hot at 20MHz, you may also want to look at the JTAG pins. Under some circumstances, if they are left floating, especially the TMS and TCK pin, EMI causes these lines to float and generate a lot of heat. Best regards, Ben TwijnstraArticle: 44707
Peter Alfke wrote: > > rickman wrote: > > > I think people have misunderstandings of how the Xilinx software is > > licensed. I am pretty sure I have read in this newsgroup postings from > > Xilinx representatives that the Xilinx software will continue to operate > > after the license has run out. Only the support is ended. > > That is correct. > The expiration of the software is only in the wording of the license agreement. > > There is *no* physical licensing mechanism that might prevent a user from > continuing to maintain existing designs in the indefinite future, as long as > you need it, as long as you want. No problem! > > Peter Alfke, Xilinx Applications I don't mean to offend you or anyone else at Xilinx, but this is a pretty silly licensing scheme. Does anyone at Xilinx have an explanation for why they word the license this way? How does this benefit Xilinx? Support has always been optional at extra charge after the first year. Heck, with some EDA vendors, support is optional the FIRST year! So what motivated Xilinx to "word" the license for time limited rights? -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 44708
Hi, I want to lock some logic in an Xilinx FPGA using RLOC. I want to use the RLOC attibute in the VHDL file, but a problem occur when the instantiatiated logic is defined in a generate loop since the label of the instantiated logic is not defined. Do anyone know about a workaround for this problem. Tanks, JohnArticle: 44709
Kevin Neilson wrote: > I might have to take back my statement. I'm now having problems whereby the > placer won't place everything, but the router will go ahead and route the > items that were placed (?). I see that everything routed, so I think > everything's cool, but upon closer examination I find that everything that > was PLACED was routed, but there are still unplaced items. I've been > informed (though it hasn't been verified because we upgraded all the > workstations in our office to XP) that this only happens on XP. > > -Kevin Step 1: By hook or by crook get hold of a copy of NT4 & SP6a. Step 2: Spend the time & effort to rebuild & re-install. Step 3: Take your sysadmin (or whoever else is responsible for this) out into the car park and give him/her a severe ``Talking to, know wot I mean Guv'' [see "Lock, Stock, and Two Smoking Barrels" for details]. Step 4: Inform the rest of the office that, due to the stress of the negotiations in Step 3, said sysadmin will be taking a few weeks off ... Note: If you don't use the GUI then NT4 in S1 can be replaced by Linux+Wine/VMWARE.Article: 44710
Richard Iachetta wrote: > In article <afc37o$d16$1@dennis.cc.strath.ac.uk>, aeu96186@yahoo.co.uk > says... > > > > Hello, > > > > I am just writing a presentation in part of which I explain the benefits of > > pipelining in FPGAS - increased clock rates due to short critical paths > > means higher bandwidth in terms of spectrum and throughput etc. etc... > > > > It occurred to me however that, because registers are "free" in Xilinx > > slices, why would there ever be a case where we would want to not use the > > registers? I know that we might not need to since the required system rate > > may be low but that would not stop us from using them? Is it a power > > consumption issue? > > > > So the questions: > > > > Under what circumstances would it be advantageous to not use the registers? > > > > Under what circumstances is it unavoidable that we must not use the > > registers? > > > > Thanks for your time, > > > > Ken > > It depends on your application but I think in general you want to produce a > result in as few clock cycles as possible to minimize latency. Pipes are > never always full so latency usually comes into play. > > This is especially true for any memory controller design (DRAM or SRAM) where latency => CPU stalled waiting for data/instructions => lower overall performance. For example by pipelining you might get your SDRAM controller up from (say) 100MHz to (say) 133MHz but the overall system performance might actually degrade ... the 133Mhz is still a marketing plus though :-).Article: 44711
http://support.xilinx.com/support/techsup/sw_updates/series4/42i/sp3/42i_sp3_readme_pc.htm You must be registered to access this page. Francois Choquette andrew.bridger@paragon.co.nz (Andrew Bridger) wrote in message news:<7939158e.0206251515.6a7c2f28@posting.google.com>... > Hi, > Where can I find the release notes, or information describing the bugs > fixed etc, for 4.2i service pack 3? (and SP1 and SP2 for that > matter.) > I have searched the Xilinx site and the closest I came was finding > release notes for 4.1i service pack 1. > > Is this information available for 4.2i? > > Thanks > AndrewArticle: 44712
The error will not be in degrees, but in nano- or rather picoseconds. Assume 100 MHz, one degree is 28 picoseconds. It would be a miracle if you could generate and use these signal without a 100 ps uncertainty. Even the delay difference from the chip boundary to different balls can be 50 ps, and a cm of pc-board is 70 ps, an inch is 170 ps. Nothing is simultaneous! Peter Alfke, Xilinx Applications ====================================== Bill wrote: > Hi, > > I need to use some DCM's for clocks which are external to the virtex II > chip. I need to output the 0 and 180 (two output pins worth). My > question is this: Will I be able to keep an exact 180 degree period after > routing, or does the routing cause delays such that the true signals might > be different by several degrees? > > Thanks, > > Bill > > ______________________________________________________________________ > Posted Via Uncensored-News.Com - Still Only $9.95 - http://www.uncensored-news.com > <><><><><><><> The Worlds Uncensored News Source <><><><><><><><> >Article: 44713
Rick Filipkiewicz wrote: > > Note: If you don't use the GUI then NT4 in S1 can be replaced by > Linux+Wine/VMWARE. If using VMWare, then the GUI should work fine. If using Wine, then most of the GUI editors should work (fpga_editor, constraints editor, floorplanner), just not the design manager. Admittedly, I am using some personal patches to make fpga_editor work smoother. It is available here (intended for current wine CVS): http://www.leewardfpga.com/fpga.diff -- My real email is akamail.com@dclark (or something like that).Article: 44714
In order for it to work, you need to put the attribute in the declarations
section of the generate, not in the architecture declarations. This works fine
under synplicity. Last time I tried it in XST, XST did not support declarations
inside the generate yet.
GEN:for i in 0 to n generate
atttribute RLOC of U1:label is "x0y0";
begin
U1:....
John Daae wrote:
> Hi,
>
> I want to lock some logic in an Xilinx FPGA using RLOC. I want to use the
> RLOC attibute in the VHDL file, but a problem occur when the instantiatiated
> logic is defined in a generate loop since the label of the instantiated
> logic is not defined. Do anyone know about a workaround for this problem.
>
> Tanks,
>
> John
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 44715Hi Ray, XST support it now. I'm using it a lot in MicroBlaze which now goes through XST. XST has actually made a lot of progress in the VHDL language support the = last 6 months. Sometimes it's actually more true to the LRM than synplicity. G=F6ran Ray Andraka wrote: > In order for it to work, you need to put the attribute in the declarati= ons > section of the generate, not in the architecture declarations. This wo= rks fine > under synplicity. Last time I tried it in XST, XST did not support dec= larations > inside the generate yet. > > GEN:for i in 0 to n generate > atttribute RLOC of U1:label is "x0y0"; > begin > U1:.... > > John Daae wrote: > > > Hi, > > > > I want to lock some logic in an Xilinx FPGA using RLOC. I want to use= the > > RLOC attibute in the VHDL file, but a problem occur when the instanti= atiated > > logic is defined in a generate loop since the label of the instantiat= ed > > logic is not defined. Do anyone know about a workaround for this prob= lem. > > > > Tanks, > > > > John > > -- > --Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email ray@andraka.com > http://www.andraka.com > > "They that give up essential liberty to obtain a little > temporary safety deserve neither liberty nor safety." > -Benjamin Franklin, 1759Article: 44716
Has anyone seen any of these symptoms? (V2, ISE 4.2i sp3) -In a fairly full part, the placer refuses to place a small number of slices because it says that it has tried to place them in slices which are already occupied (by LOC constraints in the UCF). There are free slices available, but the placer doesn't seem to want to use these; only those that are already occupied. -Despite not being fully placed, the router goes ahead and routes. All nets route and meet timing, except of course the nets associated with unplaced slices. The router displays some errors noting that these nets have not been routed. -Trace informs me that a few nets didn't meet timing because of a hold time violation due to a large (~1ns) positive clock skew. Examination shows that these nets originate at flops that weren't placed. I'm not sure how trace analyzes paths that don't exist. -KevinArticle: 44717
Hi Femi,
I hope you'll reconsider the BurchED board also :)...
http://www.burched.com.au/B5Spartan2.html
There are some points that make the B5-Spartan2e+
board a great choice:
* Low cost, high performance (5A regulators, excellent supply decoupling)
* 1 - 100MHz header programmable oscillator (select *any* frequency)
* 300K gate device! (XC2S300E)
* Works with the free Xilinx WebPACK design software
* Wide range of resource plug-on modules to select from
* Very easy to add plug-on modules later, as they become available,
or as you change to a project that requires different resources
We have a USB plug-on module planned, so you could
easily plug that on later, if you didn't need the USB straight away.
Our boards are programmed via the included parallel port
download pod cable and board, which has the unique
"lock configuration switch" and schmitt buffering for
*very reliable* use with long cables...
http://www.burched.com.au/B5CableCloseup.html
Even with the full bunlde of plug-on modules, as with our
Super-Value-Pack, the value for money is great -
very competitive pricewise, and easy to use...
http://www.burched.com.au/B5SuperValuePack.html
Whichever way you go, good luck with your choice, and
have fun with looking at the features of the various boards
available. Enjoy your shopping for an FPGA board!
Best regards
Tony Burch
http://www.BurchED.com
Low cost FPGA boards, for System-On-Chip
prototyping and education
"FEMI" <femioye@hotmail.com> wrote in message
news:afcrbj$8f4$1@venus.btinternet.com...
> Hi All,
>
> Its me again, I have looking for a board to buy for 3weeks now, and I
think
> I am inclined towards the XESS Board. I want to hear whether from other
> users of this board or any other board. My only grim with this board is
lack
> of USB interface and gate_count per $.
> Other boards I am considering are Digilab2 or Trenz(TE....)
>
> Iwould also like to confirm whether FPGA can be programmed via
USB/parallel
> port adapter.
>
> Pls Help as I need to get on with things b4 Jul.
>
> Cheers.
>
> Femi
>
>
Article: 44718
That's good news. I knew it was on the slate for inclusion and that it had a fairly
high priority.
Goran Bilski wrote:
> Hi Ray,
>
> XST support it now.
>
> I'm using it a lot in MicroBlaze which now goes through XST.
> XST has actually made a lot of progress in the VHDL language support the last 6
> months.
> Sometimes it's actually more true to the LRM than synplicity.
>
> Göran
>
> Ray Andraka wrote:
>
> > In order for it to work, you need to put the attribute in the declarations
> > section of the generate, not in the architecture declarations. This works fine
> > under synplicity. Last time I tried it in XST, XST did not support declarations
> > inside the generate yet.
> >
> > GEN:for i in 0 to n generate
> > atttribute RLOC of U1:label is "x0y0";
> > begin
> > U1:....
> >
> > John Daae wrote:
> >
> > > Hi,
> > >
> > > I want to lock some logic in an Xilinx FPGA using RLOC. I want to use the
> > > RLOC attibute in the VHDL file, but a problem occur when the instantiatiated
> > > logic is defined in a generate loop since the label of the instantiated
> > > logic is not defined. Do anyone know about a workaround for this problem.
> > >
> > > Tanks,
> > >
> > > John
> >
> > --
> > --Ray Andraka, P.E.
> > President, the Andraka Consulting Group, Inc.
> > 401/884-7930 Fax 401/884-7950
> > email ray@andraka.com
> > http://www.andraka.com
> >
> > "They that give up essential liberty to obtain a little
> > temporary safety deserve neither liberty nor safety."
> > -Benjamin Franklin, 1759
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 44719Marc, You probably already know about this, but check out the following link; http://toolbox.xilinx.com/docsan/xilinx4/data/docs/cgd/e2.html reference table 10-1 cgd.pdf Newman > Anyone know of any limitations to these constraints (reasons they > won't work or stuff they won't cover)?Article: 44720
Roland, In a 10K100E design, there was a Megafunction async fifo that actually had both clock inputs tied to the same global clock. Maxplus reported no timing errors, but a back annotated sim indicated some setup and hold violations. With some pain, I found that the data path delay from one flop to another was maybe 1 ns, but the clock skew was 2.1 which put it in the violation zone. I called Altera, and they said to make sure that the associated RAM and support logic was grouped close together in the floor planner. I would have thought that grouping flops closer together would tend to reduce the datapath delay, making the datapath delay smaller if the clock skew remained the same. I'm suspecting that something funny is happening in the LPMs associated with the Megafunction. That project is on hold for me, so I have no further data. The point of my story is that the back annotated sim indicated a problem where the timing analyzer did not using MaxplusII Newman "Roland Manders" <roland.manders@philips.com> wrote in message news:<3d1b1d7b$0$223$4d4ebb8e@read-nat.news.nl.uu.net>... > Hi, > > I have the following problem. > > After synthesizing a design with leonardo Maxplus is used to place and route > the > design everything functions as it should. > > However using the same *.edf file in Quartus after fitting and performing > timing > analysis the the following message is produced: > > ->Warning: Circuit may not operate. 1629 non-operational path(s) clocked by > clock clk have clock skew larger than the data delay. See the Compilation > Report for details. > > I have tried the solution as Altera has given with setting the LPM memories > used to a REGISTERED data in (it was already set to REGISTERED). > > Anyone any idea how to solve this problem. And why does Maxplus not give any > warning/errors..... > > Kind regards, > RolandArticle: 44721
Hello, I have a client with one of my Xilinx designs, visiting London to show off the card. He needs a new PROM to be burnt. Is there a service provider near London UK that can do this ? The parts is a Spartan II XC2S50-6PQ208C so a XC17S50APD8C or larger SPROM will work. Sincerely Daniel DeConinck Toronto CanadaArticle: 44722
Look in the Xilinx Data Book, under UK Distributors. Call Avnet at 44-1438-788-500 Cedar at 44-1844-278-278 Memec at 44-1844-261-919 Microcall at 44-1296-330-061 or Xilinx at 44-870-7350-603 someone should be able to help you. Peter Alfke, Xilinx Applications ===================== Dan wrote: > Hello, > > I have a client with one of my Xilinx designs, visiting London to show off > the card. He needs a new PROM to be burnt. Is there a service provider near > London UK that can do this ? > > The parts is a Spartan II XC2S50-6PQ208C so a XC17S50APD8C or larger SPROM > will work. > > Sincerely > Daniel DeConinck > Toronto CanadaArticle: 44723
I suggest generating a 2x clock on-chip and generating the out of phase off-chip clocks using the flip-flops in the IOBs. Run FPGA editor on a blank die and pick two adjacent IOBs for the output clocks and lock them down in a constraint file. This way the skew contributed by the FPGA is limited to the clock skew of a global clock buffer and IOB variation that you don't have any control over. I did something very similar to this with an xc2v1000 the skew was better than my ability to measure it, maybe 100ps or so. Like Peter points out, the big skew is more likely to come from PCB issues or unbalanced loading of the two clock nets. on the PCB. jeff "Bill" <not@home.com> wrote in message news:<3d1b73b4_6@news.uncensored-news.com>... > Hi, > > I need to use some DCM's for clocks which are external to the virtex II > chip. I need to output the 0 and 180 (two output pins worth). My > question is this: Will I be able to keep an exact 180 degree period after > routing, or does the routing cause delays such that the true signals might > be different by several degrees? > > Thanks, > > Bill > > > > ______________________________________________________________________ > Posted Via Uncensored-News.Com - Still Only $9.95 - http://www.uncensored-news.com > <><><><><><><> The Worlds Uncensored News Source <><><><><><><><>Article: 44724
Hi, I've done a bunch of 4000XL and SpartanXL projects. To configure these critters, we just connect PROG-, CCLK, and DIN to a few uP parallel port bits. After powerup, we pull up PROG-, wait a bit, than shift in the serial config stream, slave serial mode. We have been using Foundation software to produce a .RBT ascii config file. We wrote a little utility that builds eprom images from a Motorola S28 hex file (for the 68332 uP code) and one or more .RBT files (it bit-packs the RBT data into the eprom image, so the uP can access it and load the FPGA.) OK so far. So, if we cut over to the ISE software and use a Spartan2, does this all still work? I looked over the S2 config app notes, and they seem immensely complex. Does the RBT file contain the entire serial bit stream we need, commands and all, just like in the good old days? I'm working on a project that has zero slack time (actually, *less* than zero) and I don't want any nasty surprises. Thanks, John
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